1ae4eba83SShawn Guo// SPDX-License-Identifier: GPL-2.0
22f20182eSJiancheng Xue/*
32f20182eSJiancheng Xue * DTS File for HiSilicon Poplar Development Board
42f20182eSJiancheng Xue *
52f20182eSJiancheng Xue * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
62f20182eSJiancheng Xue */
72f20182eSJiancheng Xue
82f20182eSJiancheng Xue/dts-v1/;
92f20182eSJiancheng Xue
102f20182eSJiancheng Xue#include <dt-bindings/gpio/gpio.h>
112f20182eSJiancheng Xue#include "hi3798cv200.dtsi"
12bb61c536SShawn Guo#include "poplar-pinctrl.dtsi"
132f20182eSJiancheng Xue
142f20182eSJiancheng Xue/ {
152f20182eSJiancheng Xue	model = "HiSilicon Poplar Development Board";
162f20182eSJiancheng Xue	compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
172f20182eSJiancheng Xue
182f20182eSJiancheng Xue	aliases {
192f20182eSJiancheng Xue		serial0 = &uart0;
202f20182eSJiancheng Xue		serial2 = &uart2;
212f20182eSJiancheng Xue	};
222f20182eSJiancheng Xue
232f20182eSJiancheng Xue	chosen {
242f20182eSJiancheng Xue		stdout-path = "serial0:115200n8";
252f20182eSJiancheng Xue	};
262f20182eSJiancheng Xue
272f20182eSJiancheng Xue	memory@0 {
282f20182eSJiancheng Xue		device_type = "memory";
292f20182eSJiancheng Xue		reg = <0x0 0x0 0x0 0x80000000>;
302f20182eSJiancheng Xue	};
312f20182eSJiancheng Xue
322f20182eSJiancheng Xue	leds {
332f20182eSJiancheng Xue		compatible = "gpio-leds";
342f20182eSJiancheng Xue
352f20182eSJiancheng Xue		user-led0 {
364c7c3110SManivannan Sadhasivam			label = "green:user1";
372f20182eSJiancheng Xue			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
382f20182eSJiancheng Xue			linux,default-trigger = "heartbeat";
392f20182eSJiancheng Xue			default-state = "off";
402f20182eSJiancheng Xue		};
412f20182eSJiancheng Xue
422f20182eSJiancheng Xue		user-led1 {
434c7c3110SManivannan Sadhasivam			label = "green:user2";
442f20182eSJiancheng Xue			gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
452f20182eSJiancheng Xue			linux,default-trigger = "mmc0";
462f20182eSJiancheng Xue			default-state = "off";
472f20182eSJiancheng Xue		};
482f20182eSJiancheng Xue
492f20182eSJiancheng Xue		user-led2 {
504c7c3110SManivannan Sadhasivam			label = "green:user3";
512f20182eSJiancheng Xue			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
524c7c3110SManivannan Sadhasivam			linux,default-trigger = "mmc1";
532f20182eSJiancheng Xue			default-state = "off";
542f20182eSJiancheng Xue		};
552f20182eSJiancheng Xue
562f20182eSJiancheng Xue		user-led3 {
574c7c3110SManivannan Sadhasivam			label = "green:user4";
582f20182eSJiancheng Xue			gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;
594c7c3110SManivannan Sadhasivam			linux,default-trigger = "none";
604c7c3110SManivannan Sadhasivam			panic-indicator;
612f20182eSJiancheng Xue			default-state = "off";
622f20182eSJiancheng Xue		};
632f20182eSJiancheng Xue	};
6432fa0176SShawn Guo
6532fa0176SShawn Guo	reg_pcie: regulator-pcie {
6632fa0176SShawn Guo		compatible = "regulator-fixed";
6732fa0176SShawn Guo		regulator-name = "3V3_PCIE0";
6832fa0176SShawn Guo		regulator-min-microvolt = <3300000>;
6932fa0176SShawn Guo		regulator-max-microvolt = <3300000>;
7032fa0176SShawn Guo		gpio = <&gpio6 7 0>;
7132fa0176SShawn Guo		enable-active-high;
7232fa0176SShawn Guo	};
732f20182eSJiancheng Xue};
742f20182eSJiancheng Xue
75e83474c6SShawn Guo&ehci {
76e83474c6SShawn Guo	status = "okay";
77e83474c6SShawn Guo};
78e83474c6SShawn Guo
79bb61c536SShawn Guo&emmc {
80bb61c536SShawn Guo	pinctrl-names = "default";
81bb61c536SShawn Guo	pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
82bb61c536SShawn Guo		     &emmc_pins_3 &emmc_pins_4>;
83bb61c536SShawn Guo	fifo-depth = <256>;
84bb61c536SShawn Guo	clock-frequency = <200000000>;
85bb61c536SShawn Guo	cap-mmc-highspeed;
86bb61c536SShawn Guo	mmc-ddr-1_8v;
87bb61c536SShawn Guo	mmc-hs200-1_8v;
88bb61c536SShawn Guo	non-removable;
89bb61c536SShawn Guo	bus-width = <8>;
90bb61c536SShawn Guo	status = "okay";
91bb61c536SShawn Guo};
92bb61c536SShawn Guo
932f20182eSJiancheng Xue&gmac1 {
942f20182eSJiancheng Xue	status = "okay";
952f20182eSJiancheng Xue	#address-cells = <1>;
962f20182eSJiancheng Xue	#size-cells = <0>;
972f20182eSJiancheng Xue	phy-handle = <&eth_phy1>;
982f20182eSJiancheng Xue	phy-mode = "rgmii";
992f20182eSJiancheng Xue	hisilicon,phy-reset-delays-us = <10000 10000 30000>;
1002f20182eSJiancheng Xue
1012f20182eSJiancheng Xue	eth_phy1: phy@3 {
1022f20182eSJiancheng Xue		reg = <3>;
1032f20182eSJiancheng Xue	};
1042f20182eSJiancheng Xue};
1052f20182eSJiancheng Xue
1062f20182eSJiancheng Xue&gpio1 {
1072f20182eSJiancheng Xue	status = "okay";
108a1fb73d7SLinus Walleij	gpio-line-names = "GPIO-E",	"",
1092f20182eSJiancheng Xue			  "",		"",
110a1fb73d7SLinus Walleij			  "",		"GPIO-F",
111a1fb73d7SLinus Walleij			  "",		"GPIO-J";
1122f20182eSJiancheng Xue};
1132f20182eSJiancheng Xue
1142f20182eSJiancheng Xue&gpio2 {
1152f20182eSJiancheng Xue	status = "okay";
116a1fb73d7SLinus Walleij	gpio-line-names = "GPIO-H",	"GPIO-I",
117a1fb73d7SLinus Walleij			  "GPIO-L",	"GPIO-G",
118a1fb73d7SLinus Walleij			  "GPIO-K",	"",
1192f20182eSJiancheng Xue			  "",		"";
1202f20182eSJiancheng Xue};
1212f20182eSJiancheng Xue
1222f20182eSJiancheng Xue&gpio3 {
1232f20182eSJiancheng Xue	status = "okay";
1242f20182eSJiancheng Xue	gpio-line-names = "",		"",
1252f20182eSJiancheng Xue			  "",		"",
126a1fb73d7SLinus Walleij			  "GPIO-C",	"",
127a1fb73d7SLinus Walleij			  "",		"GPIO-B";
1282f20182eSJiancheng Xue};
1292f20182eSJiancheng Xue
1302f20182eSJiancheng Xue&gpio4 {
1312f20182eSJiancheng Xue	status = "okay";
1322f20182eSJiancheng Xue	gpio-line-names = "",		"",
1332f20182eSJiancheng Xue			  "",		"",
134a1fb73d7SLinus Walleij			  "",		"GPIO-D",
1352f20182eSJiancheng Xue			  "",		"";
1362f20182eSJiancheng Xue};
1372f20182eSJiancheng Xue
1382f20182eSJiancheng Xue&gpio5 {
1392f20182eSJiancheng Xue	status = "okay";
1402f20182eSJiancheng Xue	gpio-line-names = "",		"USER-LED-1",
1412f20182eSJiancheng Xue			  "USER-LED-2",	"",
142a1fb73d7SLinus Walleij			  "",		"GPIO-A",
1432f20182eSJiancheng Xue			  "",		"";
1442f20182eSJiancheng Xue};
1452f20182eSJiancheng Xue
1462f20182eSJiancheng Xue&gpio6 {
1472f20182eSJiancheng Xue	status = "okay";
1482f20182eSJiancheng Xue	gpio-line-names = "",		"",
1492f20182eSJiancheng Xue			  "",		"USER-LED-0",
1502f20182eSJiancheng Xue			  "",		"",
1512f20182eSJiancheng Xue			  "",		"";
1522f20182eSJiancheng Xue};
1532f20182eSJiancheng Xue
1542f20182eSJiancheng Xue&gpio10 {
1552f20182eSJiancheng Xue	status = "okay";
1562f20182eSJiancheng Xue	gpio-line-names = "",		"",
1572f20182eSJiancheng Xue			  "",		"",
1582f20182eSJiancheng Xue			  "",		"",
1592f20182eSJiancheng Xue			  "USER-LED-3",	"";
1602f20182eSJiancheng Xue};
1612f20182eSJiancheng Xue
1622f20182eSJiancheng Xue&i2c0 {
1632f20182eSJiancheng Xue	status = "okay";
1642f20182eSJiancheng Xue	label = "LS-I2C0";
1652f20182eSJiancheng Xue};
1662f20182eSJiancheng Xue
1672f20182eSJiancheng Xue&i2c2 {
1682f20182eSJiancheng Xue	status = "okay";
1692f20182eSJiancheng Xue	label = "LS-I2C1";
1702f20182eSJiancheng Xue};
1712f20182eSJiancheng Xue
1722f20182eSJiancheng Xue&ir {
1733d5191a1SShawn Guo	linux,rc-map-name = "rc-hisi-poplar";
1742f20182eSJiancheng Xue	status = "okay";
1752f20182eSJiancheng Xue};
1762f20182eSJiancheng Xue
177e83474c6SShawn Guo&ohci {
178e83474c6SShawn Guo	status = "okay";
179e83474c6SShawn Guo};
180e83474c6SShawn Guo
18132fa0176SShawn Guo&pcie {
18232fa0176SShawn Guo	reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
18332fa0176SShawn Guo	vpcie-supply = <&reg_pcie>;
18432fa0176SShawn Guo	status = "okay";
18532fa0176SShawn Guo};
18632fa0176SShawn Guo
1874dcf0f9aSShawn Guo&sd0 {
1884dcf0f9aSShawn Guo	bus-width = <4>;
1894dcf0f9aSShawn Guo	cap-sd-highspeed;
1904dcf0f9aSShawn Guo	status = "okay";
1914dcf0f9aSShawn Guo};
1924dcf0f9aSShawn Guo
1932f20182eSJiancheng Xue&spi0 {
1942f20182eSJiancheng Xue	status = "okay";
1952f20182eSJiancheng Xue	label = "LS-SPI0";
1962f20182eSJiancheng Xue};
1972f20182eSJiancheng Xue
1982f20182eSJiancheng Xue&uart0 {
1992f20182eSJiancheng Xue	status = "okay";
2002f20182eSJiancheng Xue};
2012f20182eSJiancheng Xue
2022f20182eSJiancheng Xue&uart2 {
2032f20182eSJiancheng Xue	status = "okay";
2042f20182eSJiancheng Xue	label = "LS-UART0";
2052f20182eSJiancheng Xue};
2062f20182eSJiancheng Xue/* No optional LS-UART1 on Low Speed Expansion Connector. */
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