1a1369029SAntoine TenartAlpine MSIX controller 2a1369029SAntoine Tenart 3a1369029SAntoine TenartSee arm,gic-v3.txt for SPI and MSI definitions. 4a1369029SAntoine Tenart 5a1369029SAntoine TenartRequired properties: 6a1369029SAntoine Tenart 7a1369029SAntoine Tenart- compatible: should be "al,alpine-msix" 8a1369029SAntoine Tenart- reg: physical base address and size of the registers 9a1369029SAntoine Tenart- interrupt-controller: identifies the node as an interrupt controller 10a1369029SAntoine Tenart- msi-controller: identifies the node as an PCI Message Signaled Interrupt 11a1369029SAntoine Tenart controller 12a1369029SAntoine Tenart- al,msi-base-spi: SPI base of the MSI frame 13a1369029SAntoine Tenart- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 14a1369029SAntoine Tenart 15a1369029SAntoine TenartExample: 16a1369029SAntoine Tenart 17a1369029SAntoine Tenartmsix: msix { 18a1369029SAntoine Tenart compatible = "al,alpine-msix"; 19a1369029SAntoine Tenart reg = <0x0 0xfbe00000 0x0 0x100000>; 20a1369029SAntoine Tenart interrupt-parent = <&gic>; 21a1369029SAntoine Tenart interrupt-controller; 22a1369029SAntoine Tenart msi-controller; 23a1369029SAntoine Tenart al,msi-base-spi = <160>; 24a1369029SAntoine Tenart al,msi-num-spis = <160>; 25a1369029SAntoine Tenart}; 26