1f8043872SChris BootBroadcom BCM2835 SPI0 controller
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3f8043872SChris BootThe BCM2835 contains two forms of SPI master controller, one known simply as
4f8043872SChris BootSPI0, and the other known as the "Universal SPI Master"; part of the
5f884ab15SAnatol Pomozovauxiliary block. This binding applies to the SPI0 controller.
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7f8043872SChris BootRequired properties:
8a11bc0e1SFlorian Fainelli- compatible: Should be one of "brcm,bcm2835-spi" for BCM2835/2836/2837 or
9a11bc0e1SFlorian Fainelli  "brcm,bcm2711-spi" for BCM2711 or "brcm,bcm7211-spi" for BCM7211.
10f8043872SChris Boot- reg: Should contain register location and length.
11f8043872SChris Boot- interrupts: Should contain interrupt.
12f8043872SChris Boot- clocks: The clock feeding the SPI controller.
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14f8043872SChris BootExample:
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16f8043872SChris Bootspi@20204000 {
17f8043872SChris Boot	compatible = "brcm,bcm2835-spi";
18f8043872SChris Boot	reg = <0x7e204000 0x1000>;
19f8043872SChris Boot	interrupts = <2 22>;
20f8043872SChris Boot	clocks = <&clk_spi>;
21f8043872SChris Boot	#address-cells = <1>;
22f8043872SChris Boot	#size-cells = <0>;
23f8043872SChris Boot};
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