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Searched refs:SD1CKCR (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/board/renesas/alt/
H A Dalt.c47 #define SD1CKCR 0xE6150078 macro
56 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()
H A Dalt_spl.c26 #define SD1CKCR 0xE6150078 macro
365 writel(SD_97500KHZ, SD1CKCR); in board_init_f()
/openbmc/u-boot/board/renesas/silk/
H A Dsilk.c48 #define SD1CKCR 0xE6150078 macro
57 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()
H A Dsilk_spl.c26 #define SD1CKCR 0xE6150078 macro
379 writel(SD_97500KHZ, SD1CKCR); in board_init_f()
/openbmc/u-boot/board/renesas/koelsch/
H A Dkoelsch.c52 #define SD1CKCR 0xE6150078 macro
64 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()
/openbmc/u-boot/board/renesas/gose/
H A Dgose.c50 #define SD1CKCR 0xE6150078 macro
62 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()
/openbmc/u-boot/board/renesas/lager/
H A Dlager.c61 #define SD1CKCR 0xE6150078 macro
73 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()