1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/alt/alt.c
4 *
5 * Copyright (C) 2014, 2015 Renesas Electronics Corporation
6 */
7
8 #include <common.h>
9 #include <malloc.h>
10 #include <dm.h>
11 #include <dm/platform_data/serial_sh.h>
12 #include <environment.h>
13 #include <asm/processor.h>
14 #include <asm/mach-types.h>
15 #include <asm/io.h>
16 #include <linux/errno.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/gpio.h>
19 #include <asm/arch/rmobile.h>
20 #include <asm/arch/rcar-mstp.h>
21 #include <asm/arch/mmc.h>
22 #include <asm/arch/sh_sdhi.h>
23 #include <netdev.h>
24 #include <miiphy.h>
25 #include <i2c.h>
26 #include <div64.h>
27 #include "qos.h"
28
29 DECLARE_GLOBAL_DATA_PTR;
30
s_init(void)31 void s_init(void)
32 {
33 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
34 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
35
36 /* Watchdog init */
37 writel(0xA5A5A500, &rwdt->rwtcsra);
38 writel(0xA5A5A500, &swdt->swtcsra);
39
40 /* QoS */
41 qos_init();
42 }
43
44 #define TMU0_MSTP125 BIT(25)
45 #define MMC0_MSTP315 BIT(15)
46
47 #define SD1CKCR 0xE6150078
48 #define SD_97500KHZ 0x7
49
board_early_init_f(void)50 int board_early_init_f(void)
51 {
52 /* TMU */
53 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
54
55 /* Set SD1 to the 97.5MHz */
56 writel(SD_97500KHZ, SD1CKCR);
57
58 return 0;
59 }
60
61 #define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
62
board_init(void)63 int board_init(void)
64 {
65 /* adress of boot parameters */
66 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
67
68 /* Force ethernet PHY out of reset */
69 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
70 gpio_direction_output(ETHERNET_PHY_RESET, 0);
71 mdelay(20);
72 gpio_direction_output(ETHERNET_PHY_RESET, 1);
73 udelay(1);
74
75 return 0;
76 }
77
dram_init(void)78 int dram_init(void)
79 {
80 if (fdtdec_setup_mem_size_base() != 0)
81 return -EINVAL;
82
83 return 0;
84 }
85
dram_init_banksize(void)86 int dram_init_banksize(void)
87 {
88 fdtdec_setup_memory_banksize();
89
90 return 0;
91 }
92
93 /* KSZ8041RNLI */
94 #define PHY_CONTROL1 0x1E
95 #define PHY_LED_MODE 0xC000
96 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)97 int board_phy_config(struct phy_device *phydev)
98 {
99 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
100 ret &= ~PHY_LED_MODE;
101 ret |= PHY_LED_MODE_ACK;
102 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
103
104 return 0;
105 }
106
reset_cpu(ulong addr)107 void reset_cpu(ulong addr)
108 {
109 struct udevice *dev;
110 const u8 pmic_bus = 7;
111 const u8 pmic_addr = 0x58;
112 u8 data;
113 int ret;
114
115 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
116 if (ret)
117 hang();
118
119 ret = dm_i2c_read(dev, 0x13, &data, 1);
120 if (ret)
121 hang();
122
123 data |= BIT(1);
124
125 ret = dm_i2c_write(dev, 0x13, &data, 1);
126 if (ret)
127 hang();
128 }
129
env_get_location(enum env_operation op,int prio)130 enum env_location env_get_location(enum env_operation op, int prio)
131 {
132 const u32 load_magic = 0xb33fc0de;
133
134 /* Block environment access if loaded using JTAG */
135 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
136 (op != ENVOP_INIT))
137 return ENVL_UNKNOWN;
138
139 if (prio)
140 return ENVL_UNKNOWN;
141
142 return ENVL_SPI_FLASH;
143 }
144