1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/alt/alt_spl.c
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 */
7
8 #include <common.h>
9 #include <malloc.h>
10 #include <dm/platform_data/serial_sh.h>
11 #include <asm/processor.h>
12 #include <asm/mach-types.h>
13 #include <asm/io.h>
14 #include <linux/errno.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h>
17 #include <asm/arch/rmobile.h>
18 #include <asm/arch/rcar-mstp.h>
19
20 #include <spl.h>
21
22 #define TMU0_MSTP125 BIT(25)
23 #define SCIF2_MSTP719 BIT(19)
24 #define QSPI_MSTP917 BIT(17)
25
26 #define SD1CKCR 0xE6150078
27 #define SD_97500KHZ 0x7
28
29 struct reg_config {
30 u16 off;
31 u32 val;
32 };
33
dbsc_wait(u16 reg)34 static void dbsc_wait(u16 reg)
35 {
36 static const u32 dbsc3_0_base = DBSC3_0_BASE;
37
38 while (!(readl(dbsc3_0_base + reg) & BIT(0)))
39 ;
40 }
41
spl_init_sys(void)42 static void spl_init_sys(void)
43 {
44 u32 r0 = 0;
45
46 writel(0xa5a5a500, 0xe6020004);
47 writel(0xa5a5a500, 0xe6030004);
48
49 asm volatile(
50 /* ICIALLU - Invalidate I$ to PoU */
51 "mcr 15, 0, %0, cr7, cr5, 0 \n"
52 /* BPIALL - Invalidate branch predictors */
53 "mcr 15, 0, %0, cr7, cr5, 6 \n"
54 /* Set SCTLR[IZ] */
55 "mrc 15, 0, %0, cr1, cr0, 0 \n"
56 "orr %0, #0x1800 \n"
57 "mcr 15, 0, %0, cr1, cr0, 0 \n"
58 "isb sy \n"
59 :"=r"(r0));
60 }
61
spl_init_pfc(void)62 static void spl_init_pfc(void)
63 {
64 static const struct reg_config pfc_with_unlock[] = {
65 { 0x0090, 0x00000000 },
66 { 0x0094, 0x00000000 },
67 { 0x0098, 0x00000000 },
68 { 0x0020, 0x00000000 },
69 { 0x0024, 0x00000000 },
70 { 0x0028, 0x40000000 },
71 { 0x002c, 0x00000155 },
72 { 0x0030, 0x00000002 },
73 { 0x0034, 0x00000000 },
74 { 0x0038, 0x00000000 },
75 { 0x003c, 0x00000000 },
76 { 0x0040, 0x60000000 },
77 { 0x0044, 0x36dab6db },
78 { 0x0048, 0x926da012 },
79 { 0x004c, 0x0008c383 },
80 { 0x0050, 0x00000000 },
81 { 0x0054, 0x00000140 },
82 { 0x0004, 0xffffffff },
83 { 0x0008, 0x00ec3fff },
84 { 0x000c, 0x5bffffff },
85 { 0x0010, 0x01bfe1ff },
86 { 0x0014, 0x5bffffff },
87 { 0x0018, 0x0f4b200f },
88 { 0x001c, 0x03ffffff },
89 };
90
91 static const struct reg_config pfc_without_unlock[] = {
92 { 0x0100, 0x00000000 },
93 { 0x0104, 0x4203fc00 },
94 { 0x0108, 0x00000000 },
95 { 0x010c, 0x159007ff },
96 { 0x0110, 0x80000000 },
97 { 0x0114, 0x00de481f },
98 { 0x0118, 0x00000000 },
99 };
100
101 static const struct reg_config pfc_with_unlock2[] = {
102 { 0x0060, 0xffffffff },
103 { 0x0064, 0xfffff000 },
104 { 0x0068, 0x55555500 },
105 { 0x006c, 0xffffff00 },
106 { 0x0070, 0x00000000 },
107 };
108
109 static const u32 pfc_base = 0xe6060000;
110
111 unsigned int i;
112
113 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
114 writel(~pfc_with_unlock[i].val, pfc_base);
115 writel(pfc_with_unlock[i].val,
116 pfc_base | pfc_with_unlock[i].off);
117 }
118
119 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
120 writel(pfc_without_unlock[i].val,
121 pfc_base | pfc_without_unlock[i].off);
122
123 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
124 writel(~pfc_with_unlock2[i].val, pfc_base);
125 writel(pfc_with_unlock2[i].val,
126 pfc_base | pfc_with_unlock2[i].off);
127 }
128 }
129
spl_init_gpio(void)130 static void spl_init_gpio(void)
131 {
132 static const u16 gpio_offs[] = {
133 0x1000, 0x2000, 0x3000, 0x4000, 0x5000
134 };
135
136 static const struct reg_config gpio_set[] = {
137 { 0x2000, 0x24000000 },
138 { 0x4000, 0xa4000000 },
139 { 0x5000, 0x0004c000 },
140 };
141
142 static const struct reg_config gpio_clr[] = {
143 { 0x1000, 0x01000000 },
144 { 0x2000, 0x24000000 },
145 { 0x3000, 0x00000000 },
146 { 0x4000, 0xa4000000 },
147 { 0x5000, 0x0084c380 },
148 };
149
150 static const u32 gpio_base = 0xe6050000;
151
152 unsigned int i;
153
154 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
155 writel(0, gpio_base | 0x20 | gpio_offs[i]);
156
157 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
158 writel(0, gpio_base | 0x00 | gpio_offs[i]);
159
160 for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
161 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
162
163 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
164 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
165 }
166
spl_init_lbsc(void)167 static void spl_init_lbsc(void)
168 {
169 static const struct reg_config lbsc_config[] = {
170 { 0x00, 0x00000020 },
171 { 0x08, 0x00002020 },
172 { 0x30, 0x2a103320 },
173 { 0x38, 0xff70ff70 },
174 };
175
176 static const u16 lbsc_offs[] = {
177 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
178 };
179
180 static const u32 lbsc_base = 0xfec00200;
181
182 unsigned int i;
183
184 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
185 writel(lbsc_config[i].val,
186 lbsc_base | lbsc_config[i].off);
187 writel(lbsc_config[i].val,
188 lbsc_base | (lbsc_config[i].off + 4));
189 }
190
191 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
192 writel(0, lbsc_base | lbsc_offs[i]);
193 }
194
spl_init_dbsc(void)195 static void spl_init_dbsc(void)
196 {
197 static const struct reg_config dbsc_config1[] = {
198 { 0x0018, 0x21000000 },
199 { 0x0018, 0x11000000 },
200 { 0x0018, 0x10000000 },
201 { 0x0280, 0x0000a55a },
202 { 0x0290, 0x00000001 },
203 { 0x02a0, 0x80000000 },
204 { 0x0290, 0x00000004 },
205 };
206
207 static const struct reg_config dbsc_config2[] = {
208 { 0x0290, 0x00000006 },
209 { 0x02a0, 0x0005c000 },
210 };
211
212 static const struct reg_config dbsc_config4[] = {
213 { 0x0290, 0x00000010 },
214 { 0x02a0, 0xf00464db },
215 { 0x0290, 0x00000061 },
216 { 0x02a0, 0x0000006d },
217 { 0x0290, 0x00000001 },
218 { 0x02a0, 0x00000073 },
219 { 0x0020, 0x00000007 },
220 { 0x0024, 0x0f030a02 },
221 { 0x0030, 0x00000001 },
222 { 0x00b0, 0x00000000 },
223 { 0x0040, 0x00000009 },
224 { 0x0044, 0x00000007 },
225 { 0x0048, 0x00000000 },
226 { 0x0050, 0x00000009 },
227 { 0x0054, 0x000a0009 },
228 { 0x0058, 0x00000021 },
229 { 0x005c, 0x00000018 },
230 { 0x0060, 0x00000005 },
231 { 0x0064, 0x0000001b },
232 { 0x0068, 0x00000007 },
233 { 0x006c, 0x0000000a },
234 { 0x0070, 0x00000009 },
235 { 0x0074, 0x00000010 },
236 { 0x0078, 0x000000ae },
237 { 0x007c, 0x00140005 },
238 { 0x0080, 0x00050004 },
239 { 0x0084, 0x50213005 },
240 { 0x0088, 0x000c0000 },
241 { 0x008c, 0x00000200 },
242 { 0x0090, 0x00000040 },
243 { 0x0100, 0x00000001 },
244 { 0x00c0, 0x00020001 },
245 { 0x00c8, 0x20082008 },
246 { 0x0380, 0x00020003 },
247 { 0x0390, 0x0000001f },
248 };
249
250 static const struct reg_config dbsc_config5[] = {
251 { 0x0244, 0x00000011 },
252 { 0x0290, 0x00000003 },
253 { 0x02a0, 0x0300c4e1 },
254 { 0x0290, 0x00000023 },
255 { 0x02a0, 0x00fcb6d0 },
256 { 0x0290, 0x00000011 },
257 { 0x02a0, 0x1000040b },
258 { 0x0290, 0x00000012 },
259 { 0x02a0, 0x85589955 },
260 { 0x0290, 0x00000013 },
261 { 0x02a0, 0x1a852400 },
262 { 0x0290, 0x00000014 },
263 { 0x02a0, 0x300210b4 },
264 { 0x0290, 0x00000015 },
265 { 0x02a0, 0x00000b50 },
266 { 0x0290, 0x00000016 },
267 { 0x02a0, 0x00000006 },
268 { 0x0290, 0x00000017 },
269 { 0x02a0, 0x00000010 },
270 { 0x0290, 0x0000001a },
271 { 0x02a0, 0x910035c7 },
272 { 0x0290, 0x00000004 },
273 };
274
275 static const struct reg_config dbsc_config6[] = {
276 { 0x0290, 0x00000001 },
277 { 0x02a0, 0x00000181 },
278 { 0x0018, 0x11000000 },
279 { 0x0290, 0x00000004 },
280 };
281
282 static const struct reg_config dbsc_config7[] = {
283 { 0x0290, 0x00000001 },
284 { 0x02a0, 0x0000fe01 },
285 { 0x0304, 0x00000000 },
286 { 0x00f4, 0x01004c20 },
287 { 0x00f8, 0x014000aa },
288 { 0x00e0, 0x00000140 },
289 { 0x00e4, 0x00081450 },
290 { 0x00e8, 0x00010000 },
291 { 0x0290, 0x00000004 },
292 };
293
294 static const struct reg_config dbsc_config8[] = {
295 { 0x0014, 0x00000001 },
296 { 0x0010, 0x00000001 },
297 { 0x0280, 0x00000000 },
298 };
299
300 static const u32 dbsc3_0_base = DBSC3_0_BASE;
301 unsigned int i;
302
303 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
304 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
305
306 dbsc_wait(0x2a0);
307
308 for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
309 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
310
311 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
312 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
313
314 dbsc_wait(0x240);
315
316 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
317 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
318
319 dbsc_wait(0x2a0);
320
321 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
322 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
323
324 dbsc_wait(0x2a0);
325
326 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
327 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
328
329 dbsc_wait(0x2a0);
330
331 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
332 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
333
334 }
335
spl_init_qspi(void)336 static void spl_init_qspi(void)
337 {
338 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
339
340 static const u32 qspi_base = 0xe6b10000;
341
342 writeb(0x08, qspi_base + 0x00);
343 writeb(0x00, qspi_base + 0x01);
344 writeb(0x06, qspi_base + 0x02);
345 writeb(0x01, qspi_base + 0x0a);
346 writeb(0x00, qspi_base + 0x0b);
347 writeb(0x00, qspi_base + 0x0c);
348 writeb(0x00, qspi_base + 0x0d);
349 writeb(0x00, qspi_base + 0x0e);
350
351 writew(0xe080, qspi_base + 0x10);
352
353 writeb(0xc0, qspi_base + 0x18);
354 writeb(0x00, qspi_base + 0x18);
355 writeb(0x00, qspi_base + 0x08);
356 writeb(0x48, qspi_base + 0x00);
357 }
358
board_init_f(ulong dummy)359 void board_init_f(ulong dummy)
360 {
361 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
362 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
363
364 /* Set SD1 to the 97.5MHz */
365 writel(SD_97500KHZ, SD1CKCR);
366
367 spl_init_sys();
368 spl_init_pfc();
369 spl_init_gpio();
370 spl_init_lbsc();
371 spl_init_dbsc();
372 spl_init_qspi();
373 }
374
spl_board_init(void)375 void spl_board_init(void)
376 {
377 /* UART clocks enabled and gd valid - init serial console */
378 preloader_console_init();
379 }
380
board_boot_order(u32 * spl_boot_list)381 void board_boot_order(u32 *spl_boot_list)
382 {
383 const u32 jtag_magic = 0x1337c0de;
384 const u32 load_magic = 0xb33fc0de;
385
386 /*
387 * If JTAG probe sets special word at 0xe6300020, then it must
388 * put U-Boot into RAM and SPL will start it from RAM.
389 */
390 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
391 printf("JTAG boot detected!\n");
392
393 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
394 ;
395
396 spl_boot_list[0] = BOOT_DEVICE_RAM;
397 spl_boot_list[1] = BOOT_DEVICE_NONE;
398
399 return;
400 }
401
402 /* Boot from SPI NOR with YMODEM UART fallback. */
403 spl_boot_list[0] = BOOT_DEVICE_SPI;
404 spl_boot_list[1] = BOOT_DEVICE_UART;
405 spl_boot_list[2] = BOOT_DEVICE_NONE;
406 }
407
reset_cpu(ulong addr)408 void reset_cpu(ulong addr)
409 {
410 }
411