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Searched refs:Region (Results 1 – 25 of 62) sorted by relevance

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/openbmc/intel-ipmi-oem/
H A Dipmi-allowlist.conf152 0x2c:0x20:0xff7f //<Group Extension>:<Get MDR Data Region Status>
153 0x2c:0x21:0x7f7f //<Group Extension>:<Get MDR Region Update Complete>
154 0x2c:0x22:0xff7f //<Group Extension>:<Read MDR Region>
155 0x2c:0x23:0x7f7f //<Group Extension>:<Write MDR Region>
156 0x2c:0x24:0x7f7f //<Group Extension>:<Get MDR Region Lock>
317 0x3e:0x02:0xff7f //<Intel Managed Data Region>:<BMC Data Region Update Event Message>
318 0x3e:0x20:0x7f7f //<Intel Managed Data Region>:<BMC Region Status>
319 0x3e:0x21:0x7f7f //<Intel Managed Data Region>:<BMC Region Update Complete>
320 0x3e:0x22:0xff7f //<Intel Managed Data Region>:<MDR Event>
321 0x3e:0x23:0xff7f //<Intel Managed Data Region>:<BMC Region Read>
[all …]
/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.txt1 FPGA Region Device Tree Binding
9 - FPGA Region
39 Partial Reconfiguration Region (PRR)
108 When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
117 When the overlay is removed, the child nodes will be removed and the FPGA Region
121 FPGA Region
125 Region brings together the elements needed to program on a running system and
136 An FPGA Region that exists in the live Device Tree reflects the current state.
138 Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
143 The base FPGA Region in the device tree represents the FPGA and supports full
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.lsch3_218 - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
19 - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff,
20 - Region 3 is at address 0x60_0000_0000 to the top of memory,
/openbmc/linux/Documentation/PCI/endpoint/
H A Dpci-vntb-function.rst46 1) Config Region
53 Config Region:
108 BAR0 Config Region
121 BAR0 Config Region + Scratchpad
H A Dpci-ntb-function.rst51 1) Config Region
58 Config Region:
61 Config Region is a construct that is specific to NTB implemented using NTB
63 exchange information with each other using this region. Config Region has
70 The format of Config Region is given below. All the fields here are 32 bits.
239 BAR0 Config Region
261 BAR0 Config Region + Self Scratchpad
271 Modeling Config/Scratchpad Region:
/openbmc/qemu/docs/specs/
H A Dstandard-vga.rst27 PCI Region 0
31 PCI Region 1
34 PCI Region 2
37 PCI ROM Region
H A Dpci-serial.rst20 PCI Region 0:
33 PCI Region 0:
/openbmc/u-boot/arch/x86/include/asm/arch-tangier/acpi/
H A Dsouthcluster.asl22 /* IO Region 0 */
29 /* IO Region 1 */
33 /* GPIO Low Memory Region */
39 /* PSH Memory Region 0 */
45 /* PSH Memory Region 1 */
51 /* SST Memory Region */
57 /* PCI Memory Region */
/openbmc/u-boot/tools/binman/etype/
H A Dintel_descriptor.py20 class Region: class
59 self._regions.append(Region(self.data, frba, i))
/openbmc/linux/Documentation/driver-api/fpga/
H A Dintro.rst43 FPGA Region
49 The FPGA Region framework (fpga-region.c) associates managers and
53 The Device Tree FPGA Region support (of-fpga-region.c) handles
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/acpi/
H A Dsouthcluster.asl23 /* IO Region 0 */
30 /* IO Region 1 */
118 /* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
124 /* High PCI Memory Region */
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
10 Region 1 has registers for functionality common to all queues.
/openbmc/linux/drivers/fpga/
H A DKconfig134 tristate "FPGA Region"
137 FPGA Region common code. An FPGA Region controls an FPGA Manager
142 tristate "FPGA Region Device Tree Overlay Support"
188 tristate "FPGA DFL FME Region Driver"
191 Say Y to enable FPGA Region driver for FPGA Management Engine.
/openbmc/u-boot/arch/x86/include/asm/arch-quark/acpi/
H A Dsouthcluster.asl20 /* IO Region 0 */
27 /* IO Region 1 */
115 /* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
/openbmc/linux/drivers/cxl/
H A DKconfig109 bool "CXL: Region Support"
127 bool "CXL: Region Cache Management Bypass (TEST)"
130 CXL Region management and security operations potentially invalidate
132 invalidate the affected cachelines. The CXL Region driver attempts
/openbmc/linux/Documentation/networking/devlink/
H A Diosm.rst59 each having one secure bin file and at least one Loadmap/Region file. For flashing
91 b) Flashing the Loadmap/Region file
123 Region commands
H A Ddevlink-region.rst4 Devlink Region
13 Region snapshots are collected by the driver, and can be accessed via read
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-d4xx.rst67 - Left border of the AE Region of Interest (all ROI values are in pixels
70 - Right border of the AE Region of Interest
72 - Top border of the AE Region of Interest
74 - Bottom border of the AE Region of Interest
/openbmc/linux/arch/arm/mm/
H A Dproc-arm740.S97 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
101 mov r0, #0x02 @ Region 1 write bufferred
H A Dproc-arm940.S308 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
313 mov r0, #0x02 @ Region 1 write bufferred
/openbmc/linux/samples/vfio-mdev/
H A DREADME.rst67 Region 0: I/O ports at c150 [size=8]
68 Region 1: I/O ports at c158 [size=8]
/openbmc/qemu/hw/vfio/
H A Dtrace-events101 …ame, uint64_t iova, uint64_t offset_within_region, uintptr_t page_size) "Region \"%s\" iova=0x%"PR…
102 …map(const char *name, uint64_t iova, uint64_t size, uint64_t page_size) "Region \"%s\" 0x%"PRIx64"…
111 … *name, int index, unsigned long offset, unsigned long size, int fault) "Region %s mmaps[%d], [0x%…
112 vfio_region_mmap(const char *name, unsigned long offset, unsigned long end) "Region %s [0x%lx - 0x%…
115 vfio_region_mmaps_set_enabled(const char *name, bool enabled) "Region %s mmaps enabled: %d"
116 vfio_region_unmap(const char *name, unsigned long offset, unsigned long end) "Region %s unmap [0x%l…
/openbmc/u-boot/board/freescale/ls2080ardb/
H A DREADME71 During boot i.e. IFC Region #1:-
75 After relocate to DDR i.e. IFC Region #2:-
/openbmc/linux/Documentation/driver-api/nvdimm/
H A Dnvdimm.rst30 LIBNVDIMM/LIBNDCTL: Region
33 Why Not Encode the Region Type into the Region Name?
34 How Do I Determine the Major Type of a Region?
71 NVDIMM Control Region Structure defined in ACPI 6 Section 5.2.25.5.
380 LIBNVDIMM/LIBNDCTL: Region
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME115 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K
116 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K

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