1*d6fdec21SPriyanka Jain# 2*d6fdec21SPriyanka Jain# Copyright 2018 NXP 3*d6fdec21SPriyanka Jain# 4*d6fdec21SPriyanka Jain# SPDX-License-Identifier: GPL-2.0+ 5*d6fdec21SPriyanka Jain# 6*d6fdec21SPriyanka Jain 7*d6fdec21SPriyanka JainNXP LayerScape with Chassis Generation 3.2 8*d6fdec21SPriyanka Jain 9*d6fdec21SPriyanka JainThis architecture supports NXP ARMv8 SoCs with Chassis generation 3.2 10*d6fdec21SPriyanka Jainfor example LX2160A. 11*d6fdec21SPriyanka Jain 12*d6fdec21SPriyanka JainThis architecture is enhancement over Chassis Generation 3 with 13*d6fdec21SPriyanka Jainfew differences mentioned below 14*d6fdec21SPriyanka Jain 15*d6fdec21SPriyanka Jain1)DDR Layout 16*d6fdec21SPriyanka Jain============ 17*d6fdec21SPriyanka JainEntire DDR region splits into three regions. 18*d6fdec21SPriyanka Jain - Region 1 is at address 0x8000_0000 to 0xffff_ffff. 19*d6fdec21SPriyanka Jain - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff, 20*d6fdec21SPriyanka Jain - Region 3 is at address 0x60_0000_0000 to the top of memory, 21*d6fdec21SPriyanka Jain for example 140GB, 0x63_7fff_ffff. 22*d6fdec21SPriyanka Jain 23*d6fdec21SPriyanka JainAll DDR memory is marked as cache-enabled. 24*d6fdec21SPriyanka Jain 25*d6fdec21SPriyanka Jain2)IFC is removed 26*d6fdec21SPriyanka Jain 27*d6fdec21SPriyanka Jain3)Number of I2C controllers increased to 8 28