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Searched refs:RCC (Results 1 – 17 of 17) sorted by relevance

/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
35 The secondary index is the bit number within the RCC register bank, starting
36 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
42 drivers of the RCC IP, macros are available to generate the index in
84 The index is the bit number within the RCC registers bank, starting from RCC
H A Dst,stm32mp1.txt5 for RCC IP and on fixed clocks.
8 RCC CLOCK = st,stm32mp1-rcc-clk
11 The RCC IP is both a reset and a clock controller but this documentation only
27 with value equals to RCC clock specifier as defined in
34 with DIV coding defined in RCC associated register RCC_xxxDIVR
61 with DIV value as defined in RCC spec:
204 in device tree clk-hsi is the clock after HSIDIV (ck_hsi in RCC doc)
H A Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
137 The index is the bit number within the RCC registers bank, starting from RCC
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
42 The secondary index is the bit number within the RCC register bank, starting
43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
49 drivers of the RCC IP, macros are available to generate the index in
127 The index is the bit number within the RCC registers bank, starting from RCC
H A Dst,stm32mp1-rcc.yaml13 The RCC IP is both a reset and a clock controller.
14 RCC makes also power management (resume/supend and wakeup interrupt).
33 The index is the bit number within the RCC registers bank, starting from RCC
H A Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
59 The index is the bit number within the RCC registers bank, starting from RCC
/openbmc/qemu/tests/qtest/
H A Dcmsdk-apb-watchdog-test.c36 #define RCC 0x60 macro
90 rcc = readl(SSYS_BASE + RCC); in test_clock_change()
93 writel(SSYS_BASE + RCC, rcc); in test_clock_change()
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
H A Dst,stm32mp1-rcc.txt4 The RCC IP is both a reset and a clock controller.
/openbmc/u-boot/doc/device-tree-bindings/reset/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
/openbmc/u-boot/drivers/clk/
H A DKconfig54 This clock driver adds support for RCC clock management
94 bool "Enable RCC clock driver for STM32MP1"
98 Enable the STM32 clock (RCC) driver. Enable support for
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml87 set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
93 select RCC clock instead of ETH_REF_CLK.
/openbmc/qemu/docs/system/arm/
H A Dstm32.rst54 * Reset and Clock Controller (RCC)
/openbmc/u-boot/drivers/misc/
H A DKconfig203 bool "Enable RCC driver for the STM32 SoC's family"
206 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dst,stm32-rproc.yaml49 Reference to the system configuration which holds the RCC trust zone mode
/openbmc/linux/drivers/reset/
H A DKconfig228 - RCC reset controller in STM32 MCUs
/openbmc/qemu/hw/net/
H A Dpcnet.c294 GET_FIELD((R)->msg_length, RMDM, RCC), \