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Searched refs:PLL (Results 1 – 25 of 36) sorted by relevance

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/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32h7-rcc.txt29 Please see PLL section below.
65 STM32H7 PLL
68 The VCO of STM32 PLL could be reprensented like this:
79 When the PLL is configured in integer mode:
82 When the PLL is configured in fractional mode:
107 - st,pllrge: PLL input frequency range
108 - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz
109 - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz
110 - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz
111 - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz
H A Dst,stm32mp1.txt52 PLL children node for PLL1 to PLL4 : (see ref manual for details)
58 - cfg: The parameters for PLL configuration in this order:
76 (optional, PLL is in integer mode when absent)
/openbmc/u-boot/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
23 This option is used to enable the AT91 UTMI PLL clock
25 output of 480 MHz UTMI PLL, The souce clock of the UTMI
26 PLL is the main clock, so the main clock must select the
35 the device tree, configure the USBS bit (PLLA or UTMI PLL)
/openbmc/u-boot/doc/device-tree-bindings/phy/
H A Dphy-stm32-usbphyc.txt6 PLL configuration.
9 |_ PLL
25 - clocks: phandle + clock specifier for the PLL phy clock
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
31 - assigned-clock-parents: the PLL phy clock parent
/openbmc/u-boot/arch/arm/mach-davinci/
H A DKconfig67 comment "DA850 PLL Initialization Parameters"
76 int "PLLC0 PLL Post-Divider"
79 Value written to PLLC0 PLL Post-Divider Control Register
124 hex "PLLC1 PLL Post-Divider"
127 Value written to PLLC1 PLL Post-Divider Control Register
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c27 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
44 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
46 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
48 PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
50 PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
52 PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
54 PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
56 PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
58 PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
60 PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
[all …]
H A Dclk-mt7629.c31 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
48 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
50 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
52 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
54 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
56 PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
58 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
/openbmc/u-boot/doc/imx/common/
H A Dimx5.txt9 1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
12 The PLL's in the i.MX51 processor can go out of lock due to a metastable
14 This workaround implements an undocumented feature in the PLL (dither
/openbmc/u-boot/doc/
H A DREADME.Heterogeneous-SoCs63 Following are the defines for PLL's index that provide the Clocking to
66 CONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock
67 CONFIG_SYS_ULB_CLK - Define PLL index for ULB clock
68 CONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock
H A DREADME.m68k112 CONFIG_SYS_MFD -- defines the PLL Multiplication Factor Divider
114 CONFIG_SYS_RFD -- defines the PLL Reduce Frequency Devider
/openbmc/u-boot/cmd/aspeed/
H A DKconfig17 bool "ASPEED PLL test"
/openbmc/u-boot/board/freescale/mpc832xemds/
H A DREADME28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
29 SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
32 SW7[1-8]= 1000_0011 (QE PLL setting)
/openbmc/u-boot/board/freescale/mpc837xemds/
H A DREADME27 SW4[1-8]= 0000_0110 (core PLL setting)
28 SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S192 .word 0x00005B80 @ PLL
210 .word 0x000071C1 @ PLL
229 .word 0x00005B80 @ PLL
251 .word 0x000071C1 @ PLL
686 ldr r2, =0xC48066C0 @ load PLL parameter for 24Mhz CLKIN (330)
688 ldr r2, =0x93002400 @ load PLL parameter for 24Mhz CLKIN (396)
694 ldr r2, =0x930023E0 @ load PLL parameter for 24Mhz CLKIN (384)
696 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (372)
698 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (360)
708 ldr r2, =0xC4806680 @ load PLL parameter for 25Mhz CLKIN (331)
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dqts-filter.sh107 * Altera SoCFPGA Clock and PLL configuration
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A DKconfig442 This number is the reference clock frequency of core PLL.
443 For most platforms, the core PLL and Platform PLL have the same
455 Platform PLL, in another word:
/openbmc/u-boot/board/lego/ev3/
H A DREADME13 only and it takes care of low level configuration (PLL and DDR), we don't use
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A DKconfig74 PLL, Low-Power, and Reset Control Register (15-30)
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos_mipi_dsi.txt29 samsung,dsim-config-pll-stable-time: the PLL Timer for stability
/openbmc/qemu/hw/misc/
H A Dtrace-events129 msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
208 …r(uint32_t pll_id, uint32_t old_multiplier, uint32_t new_multiplier) "RCC: PLL %u: vco_multiplier …
209 stm32l4x5_rcc_pll_channel_enable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u ena…
210 stm32l4x5_rcc_pll_channel_disable(uint32_t pll_id, uint32_t channel_id) "RCC: PLL %u, channel %u di…
211 …id, uint32_t channel_id, uint32_t old_divider, uint32_t new_divider) "RCC: PLL %u, channel %u: div…
212 …channel_id, uint64_t vco_freq, uint64_t old_freq, uint64_t new_freq) "RCC: PLL %d channel %d updat…
/openbmc/u-boot/arch/arm/mach-mvebu/
H A DKconfig46 # Armada PLL frequency (used for NAND clock generation)
/openbmc/u-boot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg119 ; the system PLL and the peripheral's clocks are changed together.
/openbmc/u-boot/arch/arm/dts/
H A Dstih407-clock.dtsi37 * A9 PLL.
H A Dstih410-clock.dtsi39 * A9 PLL.
/openbmc/u-boot/drivers/power/
H A DKconfig182 On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC,
194 On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should

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