Home
last modified time | relevance | path

Searched refs:PHY_CTRL (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/phy/broadcom/
H A Dphy-bcm-sr-usb.c21 PHY_CTRL, enumerator
29 [PHY_CTRL] = 0x14,
34 [PHY_CTRL] = 0x10,
39 [PHY_CTRL] = 0xc,
134 rd_data = readl(regs + offset[PHY_CTRL]); in bcm_usb_ss_phy_init()
137 writel(rd_data, regs + offset[PHY_CTRL]); in bcm_usb_ss_phy_init()
183 bcm_usb_reg32_clrbits(regs + offset[PHY_CTRL], in bcm_usb_phy_reset()
185 bcm_usb_reg32_setbits(regs + offset[PHY_CTRL], in bcm_usb_phy_reset()
/openbmc/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-lvds-phy.c21 #define PHY_CTRL 0x0 macro
72 PHY_CTRL, CTRL_INIT_MASK, CTRL_INIT_VAL); in mixel_lvds_phy_init()
117 regmap_update_bits(priv->regmap, PHY_CTRL, M_MASK | NB, val); in mixel_lvds_phy_power_on()
127 regmap_write(priv->regmap, PHY_CTRL + REG_SET, val); in mixel_lvds_phy_power_on()
154 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()
157 regmap_write(priv->regmap, PHY_CTRL + REG_CLR, in mixel_lvds_phy_power_off()
287 regmap_write(priv->regmap, PHY_CTRL, CTRL_RESET_VAL); in mixel_lvds_phy_reset()
405 regmap_write(priv->regmap, PHY_CTRL + REG_SET, PD); in mixel_lvds_phy_runtime_suspend()
417 regmap_update_bits(priv->regmap, PHY_CTRL, in mixel_lvds_phy_runtime_resume()
H A Dphy-fsl-imx8-mipi-dphy.c25 #define PHY_CTRL 0x00 macro
395 regmap_write(priv->lvds_regmap, PHY_CTRL, in mixel_dphy_configure_lvds_phy()
545 regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, LVDS_EN); in mixel_dphy_power_on_lvds_phy()
602 regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, 0); in mixel_dphy_power_off()
/openbmc/linux/drivers/phy/renesas/
H A Dphy-rcar-gen3-pcie.c16 #define PHY_CTRL 0x4000 /* R8A77980 only */ macro
48 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, PHY_CTRL_PHY_PWDN, 0); in r8a77980_phy_pcie_power_on()
56 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, 0, PHY_CTRL_PHY_PWDN); in r8a77980_phy_pcie_power_off()
/openbmc/u-boot/board/keymile/km_arm/
H A Dkm_arm.c378 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
382 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
386 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
390 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
396 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
/openbmc/u-boot/include/
H A Dmv88e6352.h15 #define PHY_CTRL 0x00 macro
/openbmc/linux/drivers/net/ethernet/intel/e1000/
H A De1000_ethtool.c1169 e1000_write_phy_reg(hw, PHY_CTRL, 0x8100); in e1000_nonintegrated_phy_loopback()
1181 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_nonintegrated_phy_loopback()
1183 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); in e1000_nonintegrated_phy_loopback()
1189 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_nonintegrated_phy_loopback()
1217 e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); in e1000_integrated_phy_loopback()
1219 e1000_write_phy_reg(hw, PHY_CTRL, 0x8140); in e1000_integrated_phy_loopback()
1225 e1000_write_phy_reg(hw, PHY_CTRL, 0x4140); in e1000_integrated_phy_loopback()
1295 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_set_phy_loopback()
1297 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); in e1000_set_phy_loopback()
1347 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_loopback_cleanup()
[all …]
H A De1000_main.c423 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); in e1000_power_up_phy()
425 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); in e1000_power_up_phy()
460 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); in e1000_power_down_phy()
462 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); in e1000_power_down_phy()
4702 !e1000_read_phy_reg(hw, PHY_CTRL, in e1000_smartspeed()
4706 e1000_write_phy_reg(hw, PHY_CTRL, in e1000_smartspeed()
4717 !e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl)) { in e1000_smartspeed()
4720 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl); in e1000_smartspeed()
4791 case PHY_CTRL: in e1000_mii_ioctl()
4826 case PHY_CTRL: in e1000_mii_ioctl()
H A De1000_hw.c1340 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_copper_link_autoneg()
1345 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_copper_link_autoneg()
1668 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); in e1000_phy_force_speed_duplex()
1755 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); in e1000_phy_force_speed_duplex()
1926 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_config_mac_to_phy()
3109 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_phy_reset()
3114 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_phy_reset()
H A De1000_hw.h2478 #define PHY_CTRL 0x00 /* Control Register */ macro
/openbmc/u-boot/board/keymile/km83xx/
H A Dkm83xx.c209 { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
213 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
/openbmc/linux/drivers/gpu/drm/loongson/
H A Dlsdc_output_7a2000.c92 LSDC_HDMI_REG(0, PHY_CTRL),
104 LSDC_HDMI_REG(1, PHY_CTRL),
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.c2406 mac_reg = er32(PHY_CTRL); in e1000_oem_bits_config_ich8lan()
3033 phy_ctrl = er32(PHY_CTRL); in e1000_set_d0_lplu_state_ich8lan()
3037 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3058 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3116 phy_ctrl = er32(PHY_CTRL); in e1000_set_d3_lplu_state_ich8lan()
3120 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
3157 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
5248 ew32(PHY_CTRL, phy_ctrl); in e1000_kmrn_lock_loss_workaround_ich8lan()
5302 reg = er32(PHY_CTRL); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5305 ew32(PHY_CTRL, reg); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
[all …]
H A Dphy.c2695 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) in e1000_access_phy_wakeup_reg_bm()
/openbmc/u-boot/drivers/net/
H A De1000.c2435 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d3_lplu_state()
2454 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2506 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2557 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d0_lplu_state()
2570 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
2618 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
3163 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_copper_link_autoneg()
3168 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_copper_link_autoneg()
4808 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_phy_reset()
4813 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_phy_reset()
H A De1000.h1876 #define PHY_CTRL 0x00 /* Control Register */ macro
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-pci-arasan.c44 #define PHY_CTRL 0x24 macro
/openbmc/linux/drivers/scsi/hisi_sas/
H A Dhisi_sas_v1_hw.c126 #define PHY_CTRL (PORT_BASE + 0x14) macro
566 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); in reset_hw_v1_hw()
569 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl); in reset_hw_v1_hw()
H A Dhisi_sas_v2_hw.c181 #define PHY_CTRL (PORT_BASE + 0x14) macro
1266 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694); in init_reg_v2_hw()
H A Dhisi_sas_v3_hw.c200 #define PHY_CTRL (PORT_BASE + 0x14) macro
2958 HISI_SAS_DEBUGFS_REG(PHY_CTRL),
/openbmc/linux/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c262 #define PHY_CTRL 0x2080 macro
1331 writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL); in cadence_nand_set_timings()
/openbmc/linux/drivers/media/i2c/ccs/
H A Dccs-core.c1538 return ccs_write(sensor, PHY_CTRL, val); in ccs_update_phy_ctrl()