1ec4ba01eSPiotr Sroka // SPDX-License-Identifier: GPL-2.0+
2ec4ba01eSPiotr Sroka /*
3ec4ba01eSPiotr Sroka * Cadence NAND flash controller driver
4ec4ba01eSPiotr Sroka *
5ec4ba01eSPiotr Sroka * Copyright (C) 2019 Cadence
6ec4ba01eSPiotr Sroka *
7ec4ba01eSPiotr Sroka * Author: Piotr Sroka <piotrs@cadence.com>
8ec4ba01eSPiotr Sroka */
9ec4ba01eSPiotr Sroka
10ec4ba01eSPiotr Sroka #include <linux/bitfield.h>
11ec4ba01eSPiotr Sroka #include <linux/clk.h>
12ec4ba01eSPiotr Sroka #include <linux/dma-mapping.h>
13ec4ba01eSPiotr Sroka #include <linux/dmaengine.h>
14ec4ba01eSPiotr Sroka #include <linux/interrupt.h>
15ec4ba01eSPiotr Sroka #include <linux/module.h>
16ec4ba01eSPiotr Sroka #include <linux/mtd/mtd.h>
17ec4ba01eSPiotr Sroka #include <linux/mtd/rawnand.h>
18ec4ba01eSPiotr Sroka #include <linux/of_device.h>
19ec4ba01eSPiotr Sroka #include <linux/iopoll.h>
207999096fSHerbert Xu #include <linux/slab.h>
21ec4ba01eSPiotr Sroka
22ec4ba01eSPiotr Sroka /*
23ec4ba01eSPiotr Sroka * HPNFC can work in 3 modes:
24ec4ba01eSPiotr Sroka * - PIO - can work in master or slave DMA
25ec4ba01eSPiotr Sroka * - CDMA - needs Master DMA for accessing command descriptors.
26ec4ba01eSPiotr Sroka * - Generic mode - can use only slave DMA.
27ec4ba01eSPiotr Sroka * CDMA and PIO modes can be used to execute only base commands.
28ec4ba01eSPiotr Sroka * Generic mode can be used to execute any command
29ec4ba01eSPiotr Sroka * on NAND flash memory. Driver uses CDMA mode for
30ec4ba01eSPiotr Sroka * block erasing, page reading, page programing.
31ec4ba01eSPiotr Sroka * Generic mode is used for executing rest of commands.
32ec4ba01eSPiotr Sroka */
33ec4ba01eSPiotr Sroka
34ec4ba01eSPiotr Sroka #define MAX_ADDRESS_CYC 6
35ec4ba01eSPiotr Sroka #define MAX_ERASE_ADDRESS_CYC 3
36ec4ba01eSPiotr Sroka #define MAX_DATA_SIZE 0xFFFC
37ec4ba01eSPiotr Sroka #define DMA_DATA_SIZE_ALIGN 8
38ec4ba01eSPiotr Sroka
39ec4ba01eSPiotr Sroka /* Register definition. */
40ec4ba01eSPiotr Sroka /*
41ec4ba01eSPiotr Sroka * Command register 0.
42ec4ba01eSPiotr Sroka * Writing data to this register will initiate a new transaction
43ec4ba01eSPiotr Sroka * of the NF controller.
44ec4ba01eSPiotr Sroka */
45ec4ba01eSPiotr Sroka #define CMD_REG0 0x0000
46ec4ba01eSPiotr Sroka /* Command type field mask. */
47ec4ba01eSPiotr Sroka #define CMD_REG0_CT GENMASK(31, 30)
48ec4ba01eSPiotr Sroka /* Command type CDMA. */
49ec4ba01eSPiotr Sroka #define CMD_REG0_CT_CDMA 0uL
50ec4ba01eSPiotr Sroka /* Command type generic. */
51ec4ba01eSPiotr Sroka #define CMD_REG0_CT_GEN 3uL
52ec4ba01eSPiotr Sroka /* Command thread number field mask. */
53ec4ba01eSPiotr Sroka #define CMD_REG0_TN GENMASK(27, 24)
54ec4ba01eSPiotr Sroka
55ec4ba01eSPiotr Sroka /* Command register 2. */
56ec4ba01eSPiotr Sroka #define CMD_REG2 0x0008
57ec4ba01eSPiotr Sroka /* Command register 3. */
58ec4ba01eSPiotr Sroka #define CMD_REG3 0x000C
59ec4ba01eSPiotr Sroka /* Pointer register to select which thread status will be selected. */
60ec4ba01eSPiotr Sroka #define CMD_STATUS_PTR 0x0010
61ec4ba01eSPiotr Sroka /* Command status register for selected thread. */
62ec4ba01eSPiotr Sroka #define CMD_STATUS 0x0014
63ec4ba01eSPiotr Sroka
64ec4ba01eSPiotr Sroka /* Interrupt status register. */
65ec4ba01eSPiotr Sroka #define INTR_STATUS 0x0110
66ec4ba01eSPiotr Sroka #define INTR_STATUS_SDMA_ERR BIT(22)
67ec4ba01eSPiotr Sroka #define INTR_STATUS_SDMA_TRIGG BIT(21)
68ec4ba01eSPiotr Sroka #define INTR_STATUS_UNSUPP_CMD BIT(19)
69ec4ba01eSPiotr Sroka #define INTR_STATUS_DDMA_TERR BIT(18)
70ec4ba01eSPiotr Sroka #define INTR_STATUS_CDMA_TERR BIT(17)
71ec4ba01eSPiotr Sroka #define INTR_STATUS_CDMA_IDL BIT(16)
72ec4ba01eSPiotr Sroka
73ec4ba01eSPiotr Sroka /* Interrupt enable register. */
74ec4ba01eSPiotr Sroka #define INTR_ENABLE 0x0114
75ec4ba01eSPiotr Sroka #define INTR_ENABLE_INTR_EN BIT(31)
76ec4ba01eSPiotr Sroka #define INTR_ENABLE_SDMA_ERR_EN BIT(22)
77ec4ba01eSPiotr Sroka #define INTR_ENABLE_SDMA_TRIGG_EN BIT(21)
78ec4ba01eSPiotr Sroka #define INTR_ENABLE_UNSUPP_CMD_EN BIT(19)
79ec4ba01eSPiotr Sroka #define INTR_ENABLE_DDMA_TERR_EN BIT(18)
80ec4ba01eSPiotr Sroka #define INTR_ENABLE_CDMA_TERR_EN BIT(17)
81ec4ba01eSPiotr Sroka #define INTR_ENABLE_CDMA_IDLE_EN BIT(16)
82ec4ba01eSPiotr Sroka
83ec4ba01eSPiotr Sroka /* Controller internal state. */
84ec4ba01eSPiotr Sroka #define CTRL_STATUS 0x0118
85ec4ba01eSPiotr Sroka #define CTRL_STATUS_INIT_COMP BIT(9)
86ec4ba01eSPiotr Sroka #define CTRL_STATUS_CTRL_BUSY BIT(8)
87ec4ba01eSPiotr Sroka
88ec4ba01eSPiotr Sroka /* Command Engine threads state. */
89ec4ba01eSPiotr Sroka #define TRD_STATUS 0x0120
90ec4ba01eSPiotr Sroka
91ec4ba01eSPiotr Sroka /* Command Engine interrupt thread error status. */
92ec4ba01eSPiotr Sroka #define TRD_ERR_INT_STATUS 0x0128
93ec4ba01eSPiotr Sroka /* Command Engine interrupt thread error enable. */
94ec4ba01eSPiotr Sroka #define TRD_ERR_INT_STATUS_EN 0x0130
95ec4ba01eSPiotr Sroka /* Command Engine interrupt thread complete status. */
96ec4ba01eSPiotr Sroka #define TRD_COMP_INT_STATUS 0x0138
97ec4ba01eSPiotr Sroka
98ec4ba01eSPiotr Sroka /*
99ec4ba01eSPiotr Sroka * Transfer config 0 register.
100ec4ba01eSPiotr Sroka * Configures data transfer parameters.
101ec4ba01eSPiotr Sroka */
102ec4ba01eSPiotr Sroka #define TRAN_CFG_0 0x0400
103ec4ba01eSPiotr Sroka /* Offset value from the beginning of the page. */
104ec4ba01eSPiotr Sroka #define TRAN_CFG_0_OFFSET GENMASK(31, 16)
105ec4ba01eSPiotr Sroka /* Numbers of sectors to transfer within singlNF device's page. */
106ec4ba01eSPiotr Sroka #define TRAN_CFG_0_SEC_CNT GENMASK(7, 0)
107ec4ba01eSPiotr Sroka
108ec4ba01eSPiotr Sroka /*
109ec4ba01eSPiotr Sroka * Transfer config 1 register.
110ec4ba01eSPiotr Sroka * Configures data transfer parameters.
111ec4ba01eSPiotr Sroka */
112ec4ba01eSPiotr Sroka #define TRAN_CFG_1 0x0404
113ec4ba01eSPiotr Sroka /* Size of last data sector. */
114ec4ba01eSPiotr Sroka #define TRAN_CFG_1_LAST_SEC_SIZE GENMASK(31, 16)
115ec4ba01eSPiotr Sroka /* Size of not-last data sector. */
116ec4ba01eSPiotr Sroka #define TRAN_CFG_1_SECTOR_SIZE GENMASK(15, 0)
117ec4ba01eSPiotr Sroka
118ec4ba01eSPiotr Sroka /* ECC engine configuration register 0. */
119ec4ba01eSPiotr Sroka #define ECC_CONFIG_0 0x0428
120ec4ba01eSPiotr Sroka /* Correction strength. */
121ec4ba01eSPiotr Sroka #define ECC_CONFIG_0_CORR_STR GENMASK(10, 8)
122ec4ba01eSPiotr Sroka /* Enable erased pages detection mechanism. */
123ec4ba01eSPiotr Sroka #define ECC_CONFIG_0_ERASE_DET_EN BIT(1)
124ec4ba01eSPiotr Sroka /* Enable controller ECC check bits generation and correction. */
125ec4ba01eSPiotr Sroka #define ECC_CONFIG_0_ECC_EN BIT(0)
126ec4ba01eSPiotr Sroka
127ec4ba01eSPiotr Sroka /* ECC engine configuration register 1. */
128ec4ba01eSPiotr Sroka #define ECC_CONFIG_1 0x042C
129ec4ba01eSPiotr Sroka
130ec4ba01eSPiotr Sroka /* Multiplane settings register. */
131ec4ba01eSPiotr Sroka #define MULTIPLANE_CFG 0x0434
132ec4ba01eSPiotr Sroka /* Cache operation settings. */
133ec4ba01eSPiotr Sroka #define CACHE_CFG 0x0438
134ec4ba01eSPiotr Sroka
135ec4ba01eSPiotr Sroka /* DMA settings register. */
136ec4ba01eSPiotr Sroka #define DMA_SETINGS 0x043C
137ec4ba01eSPiotr Sroka /* Enable SDMA error report on access unprepared slave DMA interface. */
138ec4ba01eSPiotr Sroka #define DMA_SETINGS_SDMA_ERR_RSP BIT(17)
139ec4ba01eSPiotr Sroka
140ec4ba01eSPiotr Sroka /* Transferred data block size for the slave DMA module. */
141ec4ba01eSPiotr Sroka #define SDMA_SIZE 0x0440
142ec4ba01eSPiotr Sroka
143ec4ba01eSPiotr Sroka /* Thread number associated with transferred data block
144ec4ba01eSPiotr Sroka * for the slave DMA module.
145ec4ba01eSPiotr Sroka */
146ec4ba01eSPiotr Sroka #define SDMA_TRD_NUM 0x0444
147ec4ba01eSPiotr Sroka /* Thread number mask. */
148ec4ba01eSPiotr Sroka #define SDMA_TRD_NUM_SDMA_TRD GENMASK(2, 0)
149ec4ba01eSPiotr Sroka
150ec4ba01eSPiotr Sroka #define CONTROL_DATA_CTRL 0x0494
151ec4ba01eSPiotr Sroka /* Thread number mask. */
152ec4ba01eSPiotr Sroka #define CONTROL_DATA_CTRL_SIZE GENMASK(15, 0)
153ec4ba01eSPiotr Sroka
154ec4ba01eSPiotr Sroka #define CTRL_VERSION 0x800
155ec4ba01eSPiotr Sroka #define CTRL_VERSION_REV GENMASK(7, 0)
156ec4ba01eSPiotr Sroka
157ec4ba01eSPiotr Sroka /* Available hardware features of the controller. */
158ec4ba01eSPiotr Sroka #define CTRL_FEATURES 0x804
159ec4ba01eSPiotr Sroka /* Support for NV-DDR2/3 work mode. */
160ec4ba01eSPiotr Sroka #define CTRL_FEATURES_NVDDR_2_3 BIT(28)
161ec4ba01eSPiotr Sroka /* Support for NV-DDR work mode. */
162ec4ba01eSPiotr Sroka #define CTRL_FEATURES_NVDDR BIT(27)
163ec4ba01eSPiotr Sroka /* Support for asynchronous work mode. */
164ec4ba01eSPiotr Sroka #define CTRL_FEATURES_ASYNC BIT(26)
165ec4ba01eSPiotr Sroka /* Support for asynchronous work mode. */
166ec4ba01eSPiotr Sroka #define CTRL_FEATURES_N_BANKS GENMASK(25, 24)
167ec4ba01eSPiotr Sroka /* Slave and Master DMA data width. */
168ec4ba01eSPiotr Sroka #define CTRL_FEATURES_DMA_DWITH64 BIT(21)
169ec4ba01eSPiotr Sroka /* Availability of Control Data feature.*/
170ec4ba01eSPiotr Sroka #define CTRL_FEATURES_CONTROL_DATA BIT(10)
171ec4ba01eSPiotr Sroka
172ec4ba01eSPiotr Sroka /* BCH Engine identification register 0 - correction strengths. */
173ec4ba01eSPiotr Sroka #define BCH_CFG_0 0x838
174ec4ba01eSPiotr Sroka #define BCH_CFG_0_CORR_CAP_0 GENMASK(7, 0)
175ec4ba01eSPiotr Sroka #define BCH_CFG_0_CORR_CAP_1 GENMASK(15, 8)
176ec4ba01eSPiotr Sroka #define BCH_CFG_0_CORR_CAP_2 GENMASK(23, 16)
177ec4ba01eSPiotr Sroka #define BCH_CFG_0_CORR_CAP_3 GENMASK(31, 24)
178ec4ba01eSPiotr Sroka
179ec4ba01eSPiotr Sroka /* BCH Engine identification register 1 - correction strengths. */
180ec4ba01eSPiotr Sroka #define BCH_CFG_1 0x83C
181ec4ba01eSPiotr Sroka #define BCH_CFG_1_CORR_CAP_4 GENMASK(7, 0)
182ec4ba01eSPiotr Sroka #define BCH_CFG_1_CORR_CAP_5 GENMASK(15, 8)
183ec4ba01eSPiotr Sroka #define BCH_CFG_1_CORR_CAP_6 GENMASK(23, 16)
184ec4ba01eSPiotr Sroka #define BCH_CFG_1_CORR_CAP_7 GENMASK(31, 24)
185ec4ba01eSPiotr Sroka
186ec4ba01eSPiotr Sroka /* BCH Engine identification register 2 - sector sizes. */
187ec4ba01eSPiotr Sroka #define BCH_CFG_2 0x840
188ec4ba01eSPiotr Sroka #define BCH_CFG_2_SECT_0 GENMASK(15, 0)
189ec4ba01eSPiotr Sroka #define BCH_CFG_2_SECT_1 GENMASK(31, 16)
190ec4ba01eSPiotr Sroka
191ec4ba01eSPiotr Sroka /* BCH Engine identification register 3. */
192ec4ba01eSPiotr Sroka #define BCH_CFG_3 0x844
193397deafcSPiotr Sroka #define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16)
194ec4ba01eSPiotr Sroka
195ec4ba01eSPiotr Sroka /* Ready/Busy# line status. */
196ec4ba01eSPiotr Sroka #define RBN_SETINGS 0x1004
197ec4ba01eSPiotr Sroka
198ec4ba01eSPiotr Sroka /* Common settings. */
199ec4ba01eSPiotr Sroka #define COMMON_SET 0x1008
200ec4ba01eSPiotr Sroka /* 16 bit device connected to the NAND Flash interface. */
201ec4ba01eSPiotr Sroka #define COMMON_SET_DEVICE_16BIT BIT(8)
202ec4ba01eSPiotr Sroka
203ec4ba01eSPiotr Sroka /* Skip_bytes registers. */
204ec4ba01eSPiotr Sroka #define SKIP_BYTES_CONF 0x100C
205ec4ba01eSPiotr Sroka #define SKIP_BYTES_MARKER_VALUE GENMASK(31, 16)
206ec4ba01eSPiotr Sroka #define SKIP_BYTES_NUM_OF_BYTES GENMASK(7, 0)
207ec4ba01eSPiotr Sroka
208ec4ba01eSPiotr Sroka #define SKIP_BYTES_OFFSET 0x1010
209ec4ba01eSPiotr Sroka #define SKIP_BYTES_OFFSET_VALUE GENMASK(23, 0)
210ec4ba01eSPiotr Sroka
211ec4ba01eSPiotr Sroka /* Timings configuration. */
212ec4ba01eSPiotr Sroka #define ASYNC_TOGGLE_TIMINGS 0x101c
213ec4ba01eSPiotr Sroka #define ASYNC_TOGGLE_TIMINGS_TRH GENMASK(28, 24)
214ec4ba01eSPiotr Sroka #define ASYNC_TOGGLE_TIMINGS_TRP GENMASK(20, 16)
215ec4ba01eSPiotr Sroka #define ASYNC_TOGGLE_TIMINGS_TWH GENMASK(12, 8)
216ec4ba01eSPiotr Sroka #define ASYNC_TOGGLE_TIMINGS_TWP GENMASK(4, 0)
217ec4ba01eSPiotr Sroka
218ec4ba01eSPiotr Sroka #define TIMINGS0 0x1024
219ec4ba01eSPiotr Sroka #define TIMINGS0_TADL GENMASK(31, 24)
220ec4ba01eSPiotr Sroka #define TIMINGS0_TCCS GENMASK(23, 16)
221ec4ba01eSPiotr Sroka #define TIMINGS0_TWHR GENMASK(15, 8)
222ec4ba01eSPiotr Sroka #define TIMINGS0_TRHW GENMASK(7, 0)
223ec4ba01eSPiotr Sroka
224ec4ba01eSPiotr Sroka #define TIMINGS1 0x1028
225ec4ba01eSPiotr Sroka #define TIMINGS1_TRHZ GENMASK(31, 24)
226ec4ba01eSPiotr Sroka #define TIMINGS1_TWB GENMASK(23, 16)
227ec4ba01eSPiotr Sroka #define TIMINGS1_TVDLY GENMASK(7, 0)
228ec4ba01eSPiotr Sroka
229ec4ba01eSPiotr Sroka #define TIMINGS2 0x102c
230ec4ba01eSPiotr Sroka #define TIMINGS2_TFEAT GENMASK(25, 16)
231ec4ba01eSPiotr Sroka #define TIMINGS2_CS_HOLD_TIME GENMASK(13, 8)
232ec4ba01eSPiotr Sroka #define TIMINGS2_CS_SETUP_TIME GENMASK(5, 0)
233ec4ba01eSPiotr Sroka
234ec4ba01eSPiotr Sroka /* Configuration of the resynchronization of slave DLL of PHY. */
235ec4ba01eSPiotr Sroka #define DLL_PHY_CTRL 0x1034
236ec4ba01eSPiotr Sroka #define DLL_PHY_CTRL_DLL_RST_N BIT(24)
237ec4ba01eSPiotr Sroka #define DLL_PHY_CTRL_EXTENDED_WR_MODE BIT(17)
238ec4ba01eSPiotr Sroka #define DLL_PHY_CTRL_EXTENDED_RD_MODE BIT(16)
239ec4ba01eSPiotr Sroka #define DLL_PHY_CTRL_RS_HIGH_WAIT_CNT GENMASK(11, 8)
240ec4ba01eSPiotr Sroka #define DLL_PHY_CTRL_RS_IDLE_CNT GENMASK(7, 0)
241ec4ba01eSPiotr Sroka
242ec4ba01eSPiotr Sroka /* Register controlling DQ related timing. */
243ec4ba01eSPiotr Sroka #define PHY_DQ_TIMING 0x2000
244ec4ba01eSPiotr Sroka /* Register controlling DSQ related timing. */
245ec4ba01eSPiotr Sroka #define PHY_DQS_TIMING 0x2004
246ec4ba01eSPiotr Sroka #define PHY_DQS_TIMING_DQS_SEL_OE_END GENMASK(3, 0)
247ec4ba01eSPiotr Sroka #define PHY_DQS_TIMING_PHONY_DQS_SEL BIT(16)
248ec4ba01eSPiotr Sroka #define PHY_DQS_TIMING_USE_PHONY_DQS BIT(20)
249ec4ba01eSPiotr Sroka
250ec4ba01eSPiotr Sroka /* Register controlling the gate and loopback control related timing. */
251ec4ba01eSPiotr Sroka #define PHY_GATE_LPBK_CTRL 0x2008
252ec4ba01eSPiotr Sroka #define PHY_GATE_LPBK_CTRL_RDS GENMASK(24, 19)
253ec4ba01eSPiotr Sroka
254ec4ba01eSPiotr Sroka /* Register holds the control for the master DLL logic. */
255ec4ba01eSPiotr Sroka #define PHY_DLL_MASTER_CTRL 0x200C
256ec4ba01eSPiotr Sroka #define PHY_DLL_MASTER_CTRL_BYPASS_MODE BIT(23)
257ec4ba01eSPiotr Sroka
258ec4ba01eSPiotr Sroka /* Register holds the control for the slave DLL logic. */
259ec4ba01eSPiotr Sroka #define PHY_DLL_SLAVE_CTRL 0x2010
260ec4ba01eSPiotr Sroka
261ec4ba01eSPiotr Sroka /* This register handles the global control settings for the PHY. */
262ec4ba01eSPiotr Sroka #define PHY_CTRL 0x2080
263ec4ba01eSPiotr Sroka #define PHY_CTRL_SDR_DQS BIT(14)
264ec4ba01eSPiotr Sroka #define PHY_CTRL_PHONY_DQS GENMASK(9, 4)
265ec4ba01eSPiotr Sroka
266ec4ba01eSPiotr Sroka /*
267ec4ba01eSPiotr Sroka * This register handles the global control settings
268ec4ba01eSPiotr Sroka * for the termination selects for reads.
269ec4ba01eSPiotr Sroka */
270ec4ba01eSPiotr Sroka #define PHY_TSEL 0x2084
271ec4ba01eSPiotr Sroka
272ec4ba01eSPiotr Sroka /* Generic command layout. */
273ec4ba01eSPiotr Sroka #define GCMD_LAY_CS GENMASK_ULL(11, 8)
274ec4ba01eSPiotr Sroka /*
275ec4ba01eSPiotr Sroka * This bit informs the minicotroller if it has to wait for tWB
276ec4ba01eSPiotr Sroka * after sending the last CMD/ADDR/DATA in the sequence.
277ec4ba01eSPiotr Sroka */
278ec4ba01eSPiotr Sroka #define GCMD_LAY_TWB BIT_ULL(6)
279ec4ba01eSPiotr Sroka /* Type of generic instruction. */
280ec4ba01eSPiotr Sroka #define GCMD_LAY_INSTR GENMASK_ULL(5, 0)
281ec4ba01eSPiotr Sroka
282ec4ba01eSPiotr Sroka /* Generic CMD sequence type. */
283ec4ba01eSPiotr Sroka #define GCMD_LAY_INSTR_CMD 0
284ec4ba01eSPiotr Sroka /* Generic ADDR sequence type. */
285ec4ba01eSPiotr Sroka #define GCMD_LAY_INSTR_ADDR 1
286ec4ba01eSPiotr Sroka /* Generic data transfer sequence type. */
287ec4ba01eSPiotr Sroka #define GCMD_LAY_INSTR_DATA 2
288ec4ba01eSPiotr Sroka
289ec4ba01eSPiotr Sroka /* Input part of generic command type of input is command. */
290ec4ba01eSPiotr Sroka #define GCMD_LAY_INPUT_CMD GENMASK_ULL(23, 16)
291ec4ba01eSPiotr Sroka
292ec4ba01eSPiotr Sroka /* Generic command address sequence - address fields. */
293ec4ba01eSPiotr Sroka #define GCMD_LAY_INPUT_ADDR GENMASK_ULL(63, 16)
294ec4ba01eSPiotr Sroka /* Generic command address sequence - address size. */
295ec4ba01eSPiotr Sroka #define GCMD_LAY_INPUT_ADDR_SIZE GENMASK_ULL(13, 11)
296ec4ba01eSPiotr Sroka
297ec4ba01eSPiotr Sroka /* Transfer direction field of generic command data sequence. */
298ec4ba01eSPiotr Sroka #define GCMD_DIR BIT_ULL(11)
299ec4ba01eSPiotr Sroka /* Read transfer direction of generic command data sequence. */
300ec4ba01eSPiotr Sroka #define GCMD_DIR_READ 0
301ec4ba01eSPiotr Sroka /* Write transfer direction of generic command data sequence. */
302ec4ba01eSPiotr Sroka #define GCMD_DIR_WRITE 1
303ec4ba01eSPiotr Sroka
304ec4ba01eSPiotr Sroka /* ECC enabled flag of generic command data sequence - ECC enabled. */
305ec4ba01eSPiotr Sroka #define GCMD_ECC_EN BIT_ULL(12)
306ec4ba01eSPiotr Sroka /* Generic command data sequence - sector size. */
307ec4ba01eSPiotr Sroka #define GCMD_SECT_SIZE GENMASK_ULL(31, 16)
308ec4ba01eSPiotr Sroka /* Generic command data sequence - sector count. */
309ec4ba01eSPiotr Sroka #define GCMD_SECT_CNT GENMASK_ULL(39, 32)
310ec4ba01eSPiotr Sroka /* Generic command data sequence - last sector size. */
311ec4ba01eSPiotr Sroka #define GCMD_LAST_SIZE GENMASK_ULL(55, 40)
312ec4ba01eSPiotr Sroka
313ec4ba01eSPiotr Sroka /* CDMA descriptor fields. */
314ec4ba01eSPiotr Sroka /* Erase command type of CDMA descriptor. */
315ec4ba01eSPiotr Sroka #define CDMA_CT_ERASE 0x1000
316ec4ba01eSPiotr Sroka /* Program page command type of CDMA descriptor. */
317ec4ba01eSPiotr Sroka #define CDMA_CT_WR 0x2100
318ec4ba01eSPiotr Sroka /* Read page command type of CDMA descriptor. */
319ec4ba01eSPiotr Sroka #define CDMA_CT_RD 0x2200
320ec4ba01eSPiotr Sroka
321ec4ba01eSPiotr Sroka /* Flash pointer memory shift. */
322ec4ba01eSPiotr Sroka #define CDMA_CFPTR_MEM_SHIFT 24
323ec4ba01eSPiotr Sroka /* Flash pointer memory mask. */
324ec4ba01eSPiotr Sroka #define CDMA_CFPTR_MEM GENMASK(26, 24)
325ec4ba01eSPiotr Sroka
326ec4ba01eSPiotr Sroka /*
327ec4ba01eSPiotr Sroka * Command DMA descriptor flags. If set causes issue interrupt after
328ec4ba01eSPiotr Sroka * the completion of descriptor processing.
329ec4ba01eSPiotr Sroka */
330ec4ba01eSPiotr Sroka #define CDMA_CF_INT BIT(8)
331ec4ba01eSPiotr Sroka /*
332ec4ba01eSPiotr Sroka * Command DMA descriptor flags - the next descriptor
333ec4ba01eSPiotr Sroka * address field is valid and descriptor processing should continue.
334ec4ba01eSPiotr Sroka */
335ec4ba01eSPiotr Sroka #define CDMA_CF_CONT BIT(9)
336ec4ba01eSPiotr Sroka /* DMA master flag of command DMA descriptor. */
337ec4ba01eSPiotr Sroka #define CDMA_CF_DMA_MASTER BIT(10)
338ec4ba01eSPiotr Sroka
339ec4ba01eSPiotr Sroka /* Operation complete status of command descriptor. */
340ec4ba01eSPiotr Sroka #define CDMA_CS_COMP BIT(15)
341ec4ba01eSPiotr Sroka /* Operation complete status of command descriptor. */
342ec4ba01eSPiotr Sroka /* Command descriptor status - operation fail. */
343ec4ba01eSPiotr Sroka #define CDMA_CS_FAIL BIT(14)
344ec4ba01eSPiotr Sroka /* Command descriptor status - page erased. */
345ec4ba01eSPiotr Sroka #define CDMA_CS_ERP BIT(11)
346ec4ba01eSPiotr Sroka /* Command descriptor status - timeout occurred. */
347ec4ba01eSPiotr Sroka #define CDMA_CS_TOUT BIT(10)
348ec4ba01eSPiotr Sroka /*
349ec4ba01eSPiotr Sroka * Maximum amount of correction applied to one ECC sector.
350ec4ba01eSPiotr Sroka * It is part of command descriptor status.
351ec4ba01eSPiotr Sroka */
352ec4ba01eSPiotr Sroka #define CDMA_CS_MAXERR GENMASK(9, 2)
353ec4ba01eSPiotr Sroka /* Command descriptor status - uncorrectable ECC error. */
354ec4ba01eSPiotr Sroka #define CDMA_CS_UNCE BIT(1)
355ec4ba01eSPiotr Sroka /* Command descriptor status - descriptor error. */
356ec4ba01eSPiotr Sroka #define CDMA_CS_ERR BIT(0)
357ec4ba01eSPiotr Sroka
358ec4ba01eSPiotr Sroka /* Status of operation - OK. */
359ec4ba01eSPiotr Sroka #define STAT_OK 0
360ec4ba01eSPiotr Sroka /* Status of operation - FAIL. */
361ec4ba01eSPiotr Sroka #define STAT_FAIL 2
362ec4ba01eSPiotr Sroka /* Status of operation - uncorrectable ECC error. */
363ec4ba01eSPiotr Sroka #define STAT_ECC_UNCORR 3
364ec4ba01eSPiotr Sroka /* Status of operation - page erased. */
365ec4ba01eSPiotr Sroka #define STAT_ERASED 5
366ec4ba01eSPiotr Sroka /* Status of operation - correctable ECC error. */
367ec4ba01eSPiotr Sroka #define STAT_ECC_CORR 6
368ec4ba01eSPiotr Sroka /* Status of operation - unsuspected state. */
369ec4ba01eSPiotr Sroka #define STAT_UNKNOWN 7
370ec4ba01eSPiotr Sroka /* Status of operation - operation is not completed yet. */
371ec4ba01eSPiotr Sroka #define STAT_BUSY 0xFF
372ec4ba01eSPiotr Sroka
373ec4ba01eSPiotr Sroka #define BCH_MAX_NUM_CORR_CAPS 8
374ec4ba01eSPiotr Sroka #define BCH_MAX_NUM_SECTOR_SIZES 2
375ec4ba01eSPiotr Sroka
376ec4ba01eSPiotr Sroka struct cadence_nand_timings {
377ec4ba01eSPiotr Sroka u32 async_toggle_timings;
378ec4ba01eSPiotr Sroka u32 timings0;
379ec4ba01eSPiotr Sroka u32 timings1;
380ec4ba01eSPiotr Sroka u32 timings2;
381ec4ba01eSPiotr Sroka u32 dll_phy_ctrl;
382ec4ba01eSPiotr Sroka u32 phy_ctrl;
383ec4ba01eSPiotr Sroka u32 phy_dqs_timing;
384ec4ba01eSPiotr Sroka u32 phy_gate_lpbk_ctrl;
385ec4ba01eSPiotr Sroka };
386ec4ba01eSPiotr Sroka
387ec4ba01eSPiotr Sroka /* Command DMA descriptor. */
388ec4ba01eSPiotr Sroka struct cadence_nand_cdma_desc {
389ec4ba01eSPiotr Sroka /* Next descriptor address. */
390ec4ba01eSPiotr Sroka u64 next_pointer;
391ec4ba01eSPiotr Sroka
392ec4ba01eSPiotr Sroka /* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */
393ec4ba01eSPiotr Sroka u32 flash_pointer;
394ec4ba01eSPiotr Sroka /*field appears in HPNFC version 13*/
395ec4ba01eSPiotr Sroka u16 bank;
396ec4ba01eSPiotr Sroka u16 rsvd0;
397ec4ba01eSPiotr Sroka
398ec4ba01eSPiotr Sroka /* Operation the controller needs to perform. */
399ec4ba01eSPiotr Sroka u16 command_type;
400ec4ba01eSPiotr Sroka u16 rsvd1;
401ec4ba01eSPiotr Sroka /* Flags for operation of this command. */
402ec4ba01eSPiotr Sroka u16 command_flags;
403ec4ba01eSPiotr Sroka u16 rsvd2;
404ec4ba01eSPiotr Sroka
405ec4ba01eSPiotr Sroka /* System/host memory address required for data DMA commands. */
406ec4ba01eSPiotr Sroka u64 memory_pointer;
407ec4ba01eSPiotr Sroka
408ec4ba01eSPiotr Sroka /* Status of operation. */
409ec4ba01eSPiotr Sroka u32 status;
410ec4ba01eSPiotr Sroka u32 rsvd3;
411ec4ba01eSPiotr Sroka
412ec4ba01eSPiotr Sroka /* Address pointer to sync buffer location. */
413ec4ba01eSPiotr Sroka u64 sync_flag_pointer;
414ec4ba01eSPiotr Sroka
415ec4ba01eSPiotr Sroka /* Controls the buffer sync mechanism. */
416ec4ba01eSPiotr Sroka u32 sync_arguments;
417ec4ba01eSPiotr Sroka u32 rsvd4;
418ec4ba01eSPiotr Sroka
419ec4ba01eSPiotr Sroka /* Control data pointer. */
420ec4ba01eSPiotr Sroka u64 ctrl_data_ptr;
421ec4ba01eSPiotr Sroka };
422ec4ba01eSPiotr Sroka
423ec4ba01eSPiotr Sroka /* Interrupt status. */
424ec4ba01eSPiotr Sroka struct cadence_nand_irq_status {
425ec4ba01eSPiotr Sroka /* Thread operation complete status. */
426ec4ba01eSPiotr Sroka u32 trd_status;
427ec4ba01eSPiotr Sroka /* Thread operation error. */
428ec4ba01eSPiotr Sroka u32 trd_error;
429ec4ba01eSPiotr Sroka /* Controller status. */
430ec4ba01eSPiotr Sroka u32 status;
431ec4ba01eSPiotr Sroka };
432ec4ba01eSPiotr Sroka
433ec4ba01eSPiotr Sroka /* Cadence NAND flash controller capabilities get from driver data. */
434ec4ba01eSPiotr Sroka struct cadence_nand_dt_devdata {
435ec4ba01eSPiotr Sroka /* Skew value of the output signals of the NAND Flash interface. */
436ec4ba01eSPiotr Sroka u32 if_skew;
437ec4ba01eSPiotr Sroka /* It informs if slave DMA interface is connected to DMA engine. */
438ec4ba01eSPiotr Sroka unsigned int has_dma:1;
439ec4ba01eSPiotr Sroka };
440ec4ba01eSPiotr Sroka
441ec4ba01eSPiotr Sroka /* Cadence NAND flash controller capabilities read from registers. */
442ec4ba01eSPiotr Sroka struct cdns_nand_caps {
443ec4ba01eSPiotr Sroka /* Maximum number of banks supported by hardware. */
444ec4ba01eSPiotr Sroka u8 max_banks;
445ec4ba01eSPiotr Sroka /* Slave and Master DMA data width in bytes (4 or 8). */
446ec4ba01eSPiotr Sroka u8 data_dma_width;
447ec4ba01eSPiotr Sroka /* Control Data feature supported. */
448ec4ba01eSPiotr Sroka bool data_control_supp;
449ec4ba01eSPiotr Sroka /* Is PHY type DLL. */
450ec4ba01eSPiotr Sroka bool is_phy_type_dll;
451ec4ba01eSPiotr Sroka };
452ec4ba01eSPiotr Sroka
453ec4ba01eSPiotr Sroka struct cdns_nand_ctrl {
454ec4ba01eSPiotr Sroka struct device *dev;
455ec4ba01eSPiotr Sroka struct nand_controller controller;
456ec4ba01eSPiotr Sroka struct cadence_nand_cdma_desc *cdma_desc;
457ec4ba01eSPiotr Sroka /* IP capability. */
458ec4ba01eSPiotr Sroka const struct cadence_nand_dt_devdata *caps1;
459ec4ba01eSPiotr Sroka struct cdns_nand_caps caps2;
460ec4ba01eSPiotr Sroka u8 ctrl_rev;
461ec4ba01eSPiotr Sroka dma_addr_t dma_cdma_desc;
462ec4ba01eSPiotr Sroka u8 *buf;
463ec4ba01eSPiotr Sroka u32 buf_size;
464ec4ba01eSPiotr Sroka u8 curr_corr_str_idx;
465ec4ba01eSPiotr Sroka
466ec4ba01eSPiotr Sroka /* Register interface. */
467ec4ba01eSPiotr Sroka void __iomem *reg;
468ec4ba01eSPiotr Sroka
469ec4ba01eSPiotr Sroka struct {
470ec4ba01eSPiotr Sroka void __iomem *virt;
471ec4ba01eSPiotr Sroka dma_addr_t dma;
472ec4ba01eSPiotr Sroka } io;
473ec4ba01eSPiotr Sroka
474ec4ba01eSPiotr Sroka int irq;
475ec4ba01eSPiotr Sroka /* Interrupts that have happened. */
476ec4ba01eSPiotr Sroka struct cadence_nand_irq_status irq_status;
477ec4ba01eSPiotr Sroka /* Interrupts we are waiting for. */
478ec4ba01eSPiotr Sroka struct cadence_nand_irq_status irq_mask;
479ec4ba01eSPiotr Sroka struct completion complete;
480ec4ba01eSPiotr Sroka /* Protect irq_mask and irq_status. */
481ec4ba01eSPiotr Sroka spinlock_t irq_lock;
482ec4ba01eSPiotr Sroka
483ec4ba01eSPiotr Sroka int ecc_strengths[BCH_MAX_NUM_CORR_CAPS];
484ec4ba01eSPiotr Sroka struct nand_ecc_step_info ecc_stepinfos[BCH_MAX_NUM_SECTOR_SIZES];
485ec4ba01eSPiotr Sroka struct nand_ecc_caps ecc_caps;
486ec4ba01eSPiotr Sroka
487ec4ba01eSPiotr Sroka int curr_trans_type;
488ec4ba01eSPiotr Sroka
489ec4ba01eSPiotr Sroka struct dma_chan *dmac;
490ec4ba01eSPiotr Sroka
491ec4ba01eSPiotr Sroka u32 nf_clk_rate;
492ec4ba01eSPiotr Sroka /*
493ec4ba01eSPiotr Sroka * Estimated Board delay. The value includes the total
494ec4ba01eSPiotr Sroka * round trip delay for the signals and is used for deciding on values
495ec4ba01eSPiotr Sroka * associated with data read capture.
496ec4ba01eSPiotr Sroka */
497ec4ba01eSPiotr Sroka u32 board_delay;
498ec4ba01eSPiotr Sroka
499ec4ba01eSPiotr Sroka struct nand_chip *selected_chip;
500ec4ba01eSPiotr Sroka
501ec4ba01eSPiotr Sroka unsigned long assigned_cs;
502ec4ba01eSPiotr Sroka struct list_head chips;
503397deafcSPiotr Sroka u8 bch_metadata_size;
504ec4ba01eSPiotr Sroka };
505ec4ba01eSPiotr Sroka
506ec4ba01eSPiotr Sroka struct cdns_nand_chip {
507ec4ba01eSPiotr Sroka struct cadence_nand_timings timings;
508ec4ba01eSPiotr Sroka struct nand_chip chip;
509ec4ba01eSPiotr Sroka u8 nsels;
510ec4ba01eSPiotr Sroka struct list_head node;
511ec4ba01eSPiotr Sroka
512ec4ba01eSPiotr Sroka /*
513ec4ba01eSPiotr Sroka * part of oob area of NAND flash memory page.
514ec4ba01eSPiotr Sroka * This part is available for user to read or write.
515ec4ba01eSPiotr Sroka */
516ec4ba01eSPiotr Sroka u32 avail_oob_size;
517ec4ba01eSPiotr Sroka
518ec4ba01eSPiotr Sroka /* Sector size. There are few sectors per mtd->writesize */
519ec4ba01eSPiotr Sroka u32 sector_size;
520ec4ba01eSPiotr Sroka u32 sector_count;
521ec4ba01eSPiotr Sroka
522ec4ba01eSPiotr Sroka /* Offset of BBM. */
523ec4ba01eSPiotr Sroka u8 bbm_offs;
524ec4ba01eSPiotr Sroka /* Number of bytes reserved for BBM. */
525ec4ba01eSPiotr Sroka u8 bbm_len;
526ec4ba01eSPiotr Sroka /* ECC strength index. */
527ec4ba01eSPiotr Sroka u8 corr_str_idx;
528ec4ba01eSPiotr Sroka
529ec4ba01eSPiotr Sroka u8 cs[];
530ec4ba01eSPiotr Sroka };
531ec4ba01eSPiotr Sroka
532ec4ba01eSPiotr Sroka struct ecc_info {
533ec4ba01eSPiotr Sroka int (*calc_ecc_bytes)(int step_size, int strength);
534ec4ba01eSPiotr Sroka int max_step_size;
535ec4ba01eSPiotr Sroka };
536ec4ba01eSPiotr Sroka
537ec4ba01eSPiotr Sroka static inline struct
to_cdns_nand_chip(struct nand_chip * chip)538ec4ba01eSPiotr Sroka cdns_nand_chip *to_cdns_nand_chip(struct nand_chip *chip)
539ec4ba01eSPiotr Sroka {
540ec4ba01eSPiotr Sroka return container_of(chip, struct cdns_nand_chip, chip);
541ec4ba01eSPiotr Sroka }
542ec4ba01eSPiotr Sroka
543ec4ba01eSPiotr Sroka static inline struct
to_cdns_nand_ctrl(struct nand_controller * controller)544ec4ba01eSPiotr Sroka cdns_nand_ctrl *to_cdns_nand_ctrl(struct nand_controller *controller)
545ec4ba01eSPiotr Sroka {
546ec4ba01eSPiotr Sroka return container_of(controller, struct cdns_nand_ctrl, controller);
547ec4ba01eSPiotr Sroka }
548ec4ba01eSPiotr Sroka
549ec4ba01eSPiotr Sroka static bool
cadence_nand_dma_buf_ok(struct cdns_nand_ctrl * cdns_ctrl,const void * buf,u32 buf_len)550ec4ba01eSPiotr Sroka cadence_nand_dma_buf_ok(struct cdns_nand_ctrl *cdns_ctrl, const void *buf,
551ec4ba01eSPiotr Sroka u32 buf_len)
552ec4ba01eSPiotr Sroka {
553ec4ba01eSPiotr Sroka u8 data_dma_width = cdns_ctrl->caps2.data_dma_width;
554ec4ba01eSPiotr Sroka
555ec4ba01eSPiotr Sroka return buf && virt_addr_valid(buf) &&
556ec4ba01eSPiotr Sroka likely(IS_ALIGNED((uintptr_t)buf, data_dma_width)) &&
557ec4ba01eSPiotr Sroka likely(IS_ALIGNED(buf_len, DMA_DATA_SIZE_ALIGN));
558ec4ba01eSPiotr Sroka }
559ec4ba01eSPiotr Sroka
cadence_nand_wait_for_value(struct cdns_nand_ctrl * cdns_ctrl,u32 reg_offset,u32 timeout_us,u32 mask,bool is_clear)560ec4ba01eSPiotr Sroka static int cadence_nand_wait_for_value(struct cdns_nand_ctrl *cdns_ctrl,
561ec4ba01eSPiotr Sroka u32 reg_offset, u32 timeout_us,
562ec4ba01eSPiotr Sroka u32 mask, bool is_clear)
563ec4ba01eSPiotr Sroka {
564ec4ba01eSPiotr Sroka u32 val;
565ec4ba01eSPiotr Sroka int ret;
566ec4ba01eSPiotr Sroka
567ec4ba01eSPiotr Sroka ret = readl_relaxed_poll_timeout(cdns_ctrl->reg + reg_offset,
568ec4ba01eSPiotr Sroka val, !(val & mask) == is_clear,
569ec4ba01eSPiotr Sroka 10, timeout_us);
570ec4ba01eSPiotr Sroka
571ec4ba01eSPiotr Sroka if (ret < 0) {
572ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
573ec4ba01eSPiotr Sroka "Timeout while waiting for reg %x with mask %x is clear %d\n",
574ec4ba01eSPiotr Sroka reg_offset, mask, is_clear);
575ec4ba01eSPiotr Sroka }
576ec4ba01eSPiotr Sroka
577ec4ba01eSPiotr Sroka return ret;
578ec4ba01eSPiotr Sroka }
579ec4ba01eSPiotr Sroka
cadence_nand_set_ecc_enable(struct cdns_nand_ctrl * cdns_ctrl,bool enable)580ec4ba01eSPiotr Sroka static int cadence_nand_set_ecc_enable(struct cdns_nand_ctrl *cdns_ctrl,
581ec4ba01eSPiotr Sroka bool enable)
582ec4ba01eSPiotr Sroka {
583ec4ba01eSPiotr Sroka u32 reg;
584ec4ba01eSPiotr Sroka
585ec4ba01eSPiotr Sroka if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
586ec4ba01eSPiotr Sroka 1000000,
587ec4ba01eSPiotr Sroka CTRL_STATUS_CTRL_BUSY, true))
588ec4ba01eSPiotr Sroka return -ETIMEDOUT;
589ec4ba01eSPiotr Sroka
590ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0);
591ec4ba01eSPiotr Sroka
592ec4ba01eSPiotr Sroka if (enable)
593ec4ba01eSPiotr Sroka reg |= ECC_CONFIG_0_ECC_EN;
594ec4ba01eSPiotr Sroka else
595ec4ba01eSPiotr Sroka reg &= ~ECC_CONFIG_0_ECC_EN;
596ec4ba01eSPiotr Sroka
597ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
598ec4ba01eSPiotr Sroka
599ec4ba01eSPiotr Sroka return 0;
600ec4ba01eSPiotr Sroka }
601ec4ba01eSPiotr Sroka
cadence_nand_set_ecc_strength(struct cdns_nand_ctrl * cdns_ctrl,u8 corr_str_idx)602ec4ba01eSPiotr Sroka static void cadence_nand_set_ecc_strength(struct cdns_nand_ctrl *cdns_ctrl,
603ec4ba01eSPiotr Sroka u8 corr_str_idx)
604ec4ba01eSPiotr Sroka {
605ec4ba01eSPiotr Sroka u32 reg;
606ec4ba01eSPiotr Sroka
607ec4ba01eSPiotr Sroka if (cdns_ctrl->curr_corr_str_idx == corr_str_idx)
608ec4ba01eSPiotr Sroka return;
609ec4ba01eSPiotr Sroka
610ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0);
611ec4ba01eSPiotr Sroka reg &= ~ECC_CONFIG_0_CORR_STR;
612ec4ba01eSPiotr Sroka reg |= FIELD_PREP(ECC_CONFIG_0_CORR_STR, corr_str_idx);
613ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
614ec4ba01eSPiotr Sroka
615ec4ba01eSPiotr Sroka cdns_ctrl->curr_corr_str_idx = corr_str_idx;
616ec4ba01eSPiotr Sroka }
617ec4ba01eSPiotr Sroka
cadence_nand_get_ecc_strength_idx(struct cdns_nand_ctrl * cdns_ctrl,u8 strength)618ec4ba01eSPiotr Sroka static int cadence_nand_get_ecc_strength_idx(struct cdns_nand_ctrl *cdns_ctrl,
619ec4ba01eSPiotr Sroka u8 strength)
620ec4ba01eSPiotr Sroka {
621ec4ba01eSPiotr Sroka int i, corr_str_idx = -1;
622ec4ba01eSPiotr Sroka
623ec4ba01eSPiotr Sroka for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) {
624ec4ba01eSPiotr Sroka if (cdns_ctrl->ecc_strengths[i] == strength) {
625ec4ba01eSPiotr Sroka corr_str_idx = i;
626ec4ba01eSPiotr Sroka break;
627ec4ba01eSPiotr Sroka }
628ec4ba01eSPiotr Sroka }
629ec4ba01eSPiotr Sroka
630ec4ba01eSPiotr Sroka return corr_str_idx;
631ec4ba01eSPiotr Sroka }
632ec4ba01eSPiotr Sroka
cadence_nand_set_skip_marker_val(struct cdns_nand_ctrl * cdns_ctrl,u16 marker_value)633ec4ba01eSPiotr Sroka static int cadence_nand_set_skip_marker_val(struct cdns_nand_ctrl *cdns_ctrl,
634ec4ba01eSPiotr Sroka u16 marker_value)
635ec4ba01eSPiotr Sroka {
636ec4ba01eSPiotr Sroka u32 reg;
637ec4ba01eSPiotr Sroka
638ec4ba01eSPiotr Sroka if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
639ec4ba01eSPiotr Sroka 1000000,
640ec4ba01eSPiotr Sroka CTRL_STATUS_CTRL_BUSY, true))
641ec4ba01eSPiotr Sroka return -ETIMEDOUT;
642ec4ba01eSPiotr Sroka
643ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + SKIP_BYTES_CONF);
644ec4ba01eSPiotr Sroka reg &= ~SKIP_BYTES_MARKER_VALUE;
645ec4ba01eSPiotr Sroka reg |= FIELD_PREP(SKIP_BYTES_MARKER_VALUE,
646ec4ba01eSPiotr Sroka marker_value);
647ec4ba01eSPiotr Sroka
648ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF);
649ec4ba01eSPiotr Sroka
650ec4ba01eSPiotr Sroka return 0;
651ec4ba01eSPiotr Sroka }
652ec4ba01eSPiotr Sroka
cadence_nand_set_skip_bytes_conf(struct cdns_nand_ctrl * cdns_ctrl,u8 num_of_bytes,u32 offset_value,int enable)653ec4ba01eSPiotr Sroka static int cadence_nand_set_skip_bytes_conf(struct cdns_nand_ctrl *cdns_ctrl,
654ec4ba01eSPiotr Sroka u8 num_of_bytes,
655ec4ba01eSPiotr Sroka u32 offset_value,
656ec4ba01eSPiotr Sroka int enable)
657ec4ba01eSPiotr Sroka {
658ec4ba01eSPiotr Sroka u32 reg, skip_bytes_offset;
659ec4ba01eSPiotr Sroka
660ec4ba01eSPiotr Sroka if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
661ec4ba01eSPiotr Sroka 1000000,
662ec4ba01eSPiotr Sroka CTRL_STATUS_CTRL_BUSY, true))
663ec4ba01eSPiotr Sroka return -ETIMEDOUT;
664ec4ba01eSPiotr Sroka
665ec4ba01eSPiotr Sroka if (!enable) {
666ec4ba01eSPiotr Sroka num_of_bytes = 0;
667ec4ba01eSPiotr Sroka offset_value = 0;
668ec4ba01eSPiotr Sroka }
669ec4ba01eSPiotr Sroka
670ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + SKIP_BYTES_CONF);
671ec4ba01eSPiotr Sroka reg &= ~SKIP_BYTES_NUM_OF_BYTES;
672ec4ba01eSPiotr Sroka reg |= FIELD_PREP(SKIP_BYTES_NUM_OF_BYTES,
673ec4ba01eSPiotr Sroka num_of_bytes);
674ec4ba01eSPiotr Sroka skip_bytes_offset = FIELD_PREP(SKIP_BYTES_OFFSET_VALUE,
675ec4ba01eSPiotr Sroka offset_value);
676ec4ba01eSPiotr Sroka
677ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF);
678ec4ba01eSPiotr Sroka writel_relaxed(skip_bytes_offset, cdns_ctrl->reg + SKIP_BYTES_OFFSET);
679ec4ba01eSPiotr Sroka
680ec4ba01eSPiotr Sroka return 0;
681ec4ba01eSPiotr Sroka }
682ec4ba01eSPiotr Sroka
683ec4ba01eSPiotr Sroka /* Functions enables/disables hardware detection of erased data */
cadence_nand_set_erase_detection(struct cdns_nand_ctrl * cdns_ctrl,bool enable,u8 bitflips_threshold)684ec4ba01eSPiotr Sroka static void cadence_nand_set_erase_detection(struct cdns_nand_ctrl *cdns_ctrl,
685ec4ba01eSPiotr Sroka bool enable,
686ec4ba01eSPiotr Sroka u8 bitflips_threshold)
687ec4ba01eSPiotr Sroka {
688ec4ba01eSPiotr Sroka u32 reg;
689ec4ba01eSPiotr Sroka
690ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0);
691ec4ba01eSPiotr Sroka
692ec4ba01eSPiotr Sroka if (enable)
693ec4ba01eSPiotr Sroka reg |= ECC_CONFIG_0_ERASE_DET_EN;
694ec4ba01eSPiotr Sroka else
695ec4ba01eSPiotr Sroka reg &= ~ECC_CONFIG_0_ERASE_DET_EN;
696ec4ba01eSPiotr Sroka
697ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
698ec4ba01eSPiotr Sroka writel_relaxed(bitflips_threshold, cdns_ctrl->reg + ECC_CONFIG_1);
699ec4ba01eSPiotr Sroka }
700ec4ba01eSPiotr Sroka
cadence_nand_set_access_width16(struct cdns_nand_ctrl * cdns_ctrl,bool bit_bus16)701ec4ba01eSPiotr Sroka static int cadence_nand_set_access_width16(struct cdns_nand_ctrl *cdns_ctrl,
702ec4ba01eSPiotr Sroka bool bit_bus16)
703ec4ba01eSPiotr Sroka {
704ec4ba01eSPiotr Sroka u32 reg;
705ec4ba01eSPiotr Sroka
706ec4ba01eSPiotr Sroka if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
707ec4ba01eSPiotr Sroka 1000000,
708ec4ba01eSPiotr Sroka CTRL_STATUS_CTRL_BUSY, true))
709ec4ba01eSPiotr Sroka return -ETIMEDOUT;
710ec4ba01eSPiotr Sroka
711ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + COMMON_SET);
712ec4ba01eSPiotr Sroka
713ec4ba01eSPiotr Sroka if (!bit_bus16)
714ec4ba01eSPiotr Sroka reg &= ~COMMON_SET_DEVICE_16BIT;
715ec4ba01eSPiotr Sroka else
716ec4ba01eSPiotr Sroka reg |= COMMON_SET_DEVICE_16BIT;
717ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + COMMON_SET);
718ec4ba01eSPiotr Sroka
719ec4ba01eSPiotr Sroka return 0;
720ec4ba01eSPiotr Sroka }
721ec4ba01eSPiotr Sroka
722ec4ba01eSPiotr Sroka static void
cadence_nand_clear_interrupt(struct cdns_nand_ctrl * cdns_ctrl,struct cadence_nand_irq_status * irq_status)723ec4ba01eSPiotr Sroka cadence_nand_clear_interrupt(struct cdns_nand_ctrl *cdns_ctrl,
724ec4ba01eSPiotr Sroka struct cadence_nand_irq_status *irq_status)
725ec4ba01eSPiotr Sroka {
726ec4ba01eSPiotr Sroka writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS);
727ec4ba01eSPiotr Sroka writel_relaxed(irq_status->trd_status,
728ec4ba01eSPiotr Sroka cdns_ctrl->reg + TRD_COMP_INT_STATUS);
729ec4ba01eSPiotr Sroka writel_relaxed(irq_status->trd_error,
730ec4ba01eSPiotr Sroka cdns_ctrl->reg + TRD_ERR_INT_STATUS);
731ec4ba01eSPiotr Sroka }
732ec4ba01eSPiotr Sroka
733ec4ba01eSPiotr Sroka static void
cadence_nand_read_int_status(struct cdns_nand_ctrl * cdns_ctrl,struct cadence_nand_irq_status * irq_status)734ec4ba01eSPiotr Sroka cadence_nand_read_int_status(struct cdns_nand_ctrl *cdns_ctrl,
735ec4ba01eSPiotr Sroka struct cadence_nand_irq_status *irq_status)
736ec4ba01eSPiotr Sroka {
737ec4ba01eSPiotr Sroka irq_status->status = readl_relaxed(cdns_ctrl->reg + INTR_STATUS);
738ec4ba01eSPiotr Sroka irq_status->trd_status = readl_relaxed(cdns_ctrl->reg
739ec4ba01eSPiotr Sroka + TRD_COMP_INT_STATUS);
740ec4ba01eSPiotr Sroka irq_status->trd_error = readl_relaxed(cdns_ctrl->reg
741ec4ba01eSPiotr Sroka + TRD_ERR_INT_STATUS);
742ec4ba01eSPiotr Sroka }
743ec4ba01eSPiotr Sroka
irq_detected(struct cdns_nand_ctrl * cdns_ctrl,struct cadence_nand_irq_status * irq_status)744ec4ba01eSPiotr Sroka static u32 irq_detected(struct cdns_nand_ctrl *cdns_ctrl,
745ec4ba01eSPiotr Sroka struct cadence_nand_irq_status *irq_status)
746ec4ba01eSPiotr Sroka {
747ec4ba01eSPiotr Sroka cadence_nand_read_int_status(cdns_ctrl, irq_status);
748ec4ba01eSPiotr Sroka
749ec4ba01eSPiotr Sroka return irq_status->status || irq_status->trd_status ||
750ec4ba01eSPiotr Sroka irq_status->trd_error;
751ec4ba01eSPiotr Sroka }
752ec4ba01eSPiotr Sroka
cadence_nand_reset_irq(struct cdns_nand_ctrl * cdns_ctrl)753ec4ba01eSPiotr Sroka static void cadence_nand_reset_irq(struct cdns_nand_ctrl *cdns_ctrl)
754ec4ba01eSPiotr Sroka {
755ec4ba01eSPiotr Sroka unsigned long flags;
756ec4ba01eSPiotr Sroka
757ec4ba01eSPiotr Sroka spin_lock_irqsave(&cdns_ctrl->irq_lock, flags);
758ec4ba01eSPiotr Sroka memset(&cdns_ctrl->irq_status, 0, sizeof(cdns_ctrl->irq_status));
759ec4ba01eSPiotr Sroka memset(&cdns_ctrl->irq_mask, 0, sizeof(cdns_ctrl->irq_mask));
760ec4ba01eSPiotr Sroka spin_unlock_irqrestore(&cdns_ctrl->irq_lock, flags);
761ec4ba01eSPiotr Sroka }
762ec4ba01eSPiotr Sroka
763ec4ba01eSPiotr Sroka /*
764ec4ba01eSPiotr Sroka * This is the interrupt service routine. It handles all interrupts
765ec4ba01eSPiotr Sroka * sent to this device.
766ec4ba01eSPiotr Sroka */
cadence_nand_isr(int irq,void * dev_id)767ec4ba01eSPiotr Sroka static irqreturn_t cadence_nand_isr(int irq, void *dev_id)
768ec4ba01eSPiotr Sroka {
769ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = dev_id;
770ec4ba01eSPiotr Sroka struct cadence_nand_irq_status irq_status;
771ec4ba01eSPiotr Sroka irqreturn_t result = IRQ_NONE;
772ec4ba01eSPiotr Sroka
773ec4ba01eSPiotr Sroka spin_lock(&cdns_ctrl->irq_lock);
774ec4ba01eSPiotr Sroka
775ec4ba01eSPiotr Sroka if (irq_detected(cdns_ctrl, &irq_status)) {
776ec4ba01eSPiotr Sroka /* Handle interrupt. */
777ec4ba01eSPiotr Sroka /* First acknowledge it. */
778ec4ba01eSPiotr Sroka cadence_nand_clear_interrupt(cdns_ctrl, &irq_status);
779ec4ba01eSPiotr Sroka /* Status in the device context for someone to read. */
780ec4ba01eSPiotr Sroka cdns_ctrl->irq_status.status |= irq_status.status;
781ec4ba01eSPiotr Sroka cdns_ctrl->irq_status.trd_status |= irq_status.trd_status;
782ec4ba01eSPiotr Sroka cdns_ctrl->irq_status.trd_error |= irq_status.trd_error;
783ec4ba01eSPiotr Sroka /* Notify anyone who cares that it happened. */
784ec4ba01eSPiotr Sroka complete(&cdns_ctrl->complete);
785ec4ba01eSPiotr Sroka /* Tell the OS that we've handled this. */
786ec4ba01eSPiotr Sroka result = IRQ_HANDLED;
787ec4ba01eSPiotr Sroka }
788ec4ba01eSPiotr Sroka spin_unlock(&cdns_ctrl->irq_lock);
789ec4ba01eSPiotr Sroka
790ec4ba01eSPiotr Sroka return result;
791ec4ba01eSPiotr Sroka }
792ec4ba01eSPiotr Sroka
cadence_nand_set_irq_mask(struct cdns_nand_ctrl * cdns_ctrl,struct cadence_nand_irq_status * irq_mask)793ec4ba01eSPiotr Sroka static void cadence_nand_set_irq_mask(struct cdns_nand_ctrl *cdns_ctrl,
794ec4ba01eSPiotr Sroka struct cadence_nand_irq_status *irq_mask)
795ec4ba01eSPiotr Sroka {
796ec4ba01eSPiotr Sroka writel_relaxed(INTR_ENABLE_INTR_EN | irq_mask->status,
797ec4ba01eSPiotr Sroka cdns_ctrl->reg + INTR_ENABLE);
798ec4ba01eSPiotr Sroka
799ec4ba01eSPiotr Sroka writel_relaxed(irq_mask->trd_error,
800ec4ba01eSPiotr Sroka cdns_ctrl->reg + TRD_ERR_INT_STATUS_EN);
801ec4ba01eSPiotr Sroka }
802ec4ba01eSPiotr Sroka
803ec4ba01eSPiotr Sroka static void
cadence_nand_wait_for_irq(struct cdns_nand_ctrl * cdns_ctrl,struct cadence_nand_irq_status * irq_mask,struct cadence_nand_irq_status * irq_status)804ec4ba01eSPiotr Sroka cadence_nand_wait_for_irq(struct cdns_nand_ctrl *cdns_ctrl,
805ec4ba01eSPiotr Sroka struct cadence_nand_irq_status *irq_mask,
806ec4ba01eSPiotr Sroka struct cadence_nand_irq_status *irq_status)
807ec4ba01eSPiotr Sroka {
808ec4ba01eSPiotr Sroka unsigned long timeout = msecs_to_jiffies(10000);
809ec4ba01eSPiotr Sroka unsigned long time_left;
810ec4ba01eSPiotr Sroka
811ec4ba01eSPiotr Sroka time_left = wait_for_completion_timeout(&cdns_ctrl->complete,
812ec4ba01eSPiotr Sroka timeout);
813ec4ba01eSPiotr Sroka
814ec4ba01eSPiotr Sroka *irq_status = cdns_ctrl->irq_status;
815ec4ba01eSPiotr Sroka if (time_left == 0) {
816ec4ba01eSPiotr Sroka /* Timeout error. */
817ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "timeout occurred:\n");
818ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "\tstatus = 0x%x, mask = 0x%x\n",
819ec4ba01eSPiotr Sroka irq_status->status, irq_mask->status);
820ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
821ec4ba01eSPiotr Sroka "\ttrd_status = 0x%x, trd_status mask = 0x%x\n",
822ec4ba01eSPiotr Sroka irq_status->trd_status, irq_mask->trd_status);
823ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
824ec4ba01eSPiotr Sroka "\t trd_error = 0x%x, trd_error mask = 0x%x\n",
825ec4ba01eSPiotr Sroka irq_status->trd_error, irq_mask->trd_error);
826ec4ba01eSPiotr Sroka }
827ec4ba01eSPiotr Sroka }
828ec4ba01eSPiotr Sroka
829ec4ba01eSPiotr Sroka /* Execute generic command on NAND controller. */
cadence_nand_generic_cmd_send(struct cdns_nand_ctrl * cdns_ctrl,u8 chip_nr,u64 mini_ctrl_cmd)830ec4ba01eSPiotr Sroka static int cadence_nand_generic_cmd_send(struct cdns_nand_ctrl *cdns_ctrl,
831ec4ba01eSPiotr Sroka u8 chip_nr,
832ec4ba01eSPiotr Sroka u64 mini_ctrl_cmd)
833ec4ba01eSPiotr Sroka {
834ec4ba01eSPiotr Sroka u32 mini_ctrl_cmd_l, mini_ctrl_cmd_h, reg;
835ec4ba01eSPiotr Sroka
836ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_CS, chip_nr);
837ec4ba01eSPiotr Sroka mini_ctrl_cmd_l = mini_ctrl_cmd & 0xFFFFFFFF;
838ec4ba01eSPiotr Sroka mini_ctrl_cmd_h = mini_ctrl_cmd >> 32;
839ec4ba01eSPiotr Sroka
840ec4ba01eSPiotr Sroka if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
841ec4ba01eSPiotr Sroka 1000000,
842ec4ba01eSPiotr Sroka CTRL_STATUS_CTRL_BUSY, true))
843ec4ba01eSPiotr Sroka return -ETIMEDOUT;
844ec4ba01eSPiotr Sroka
845ec4ba01eSPiotr Sroka cadence_nand_reset_irq(cdns_ctrl);
846ec4ba01eSPiotr Sroka
847ec4ba01eSPiotr Sroka writel_relaxed(mini_ctrl_cmd_l, cdns_ctrl->reg + CMD_REG2);
848ec4ba01eSPiotr Sroka writel_relaxed(mini_ctrl_cmd_h, cdns_ctrl->reg + CMD_REG3);
849ec4ba01eSPiotr Sroka
850ec4ba01eSPiotr Sroka /* Select generic command. */
851ec4ba01eSPiotr Sroka reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_GEN);
852ec4ba01eSPiotr Sroka /* Thread number. */
853ec4ba01eSPiotr Sroka reg |= FIELD_PREP(CMD_REG0_TN, 0);
854ec4ba01eSPiotr Sroka
855ec4ba01eSPiotr Sroka /* Issue command. */
856ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0);
857ec4ba01eSPiotr Sroka
858ec4ba01eSPiotr Sroka return 0;
859ec4ba01eSPiotr Sroka }
860ec4ba01eSPiotr Sroka
861ec4ba01eSPiotr Sroka /* Wait for data on slave DMA interface. */
cadence_nand_wait_on_sdma(struct cdns_nand_ctrl * cdns_ctrl,u8 * out_sdma_trd,u32 * out_sdma_size)862ec4ba01eSPiotr Sroka static int cadence_nand_wait_on_sdma(struct cdns_nand_ctrl *cdns_ctrl,
863ec4ba01eSPiotr Sroka u8 *out_sdma_trd,
864ec4ba01eSPiotr Sroka u32 *out_sdma_size)
865ec4ba01eSPiotr Sroka {
866ec4ba01eSPiotr Sroka struct cadence_nand_irq_status irq_mask, irq_status;
867ec4ba01eSPiotr Sroka
868ec4ba01eSPiotr Sroka irq_mask.trd_status = 0;
869ec4ba01eSPiotr Sroka irq_mask.trd_error = 0;
870ec4ba01eSPiotr Sroka irq_mask.status = INTR_STATUS_SDMA_TRIGG
871ec4ba01eSPiotr Sroka | INTR_STATUS_SDMA_ERR
872ec4ba01eSPiotr Sroka | INTR_STATUS_UNSUPP_CMD;
873ec4ba01eSPiotr Sroka
874ec4ba01eSPiotr Sroka cadence_nand_set_irq_mask(cdns_ctrl, &irq_mask);
875ec4ba01eSPiotr Sroka cadence_nand_wait_for_irq(cdns_ctrl, &irq_mask, &irq_status);
876ec4ba01eSPiotr Sroka if (irq_status.status == 0) {
877ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Timeout while waiting for SDMA\n");
878ec4ba01eSPiotr Sroka return -ETIMEDOUT;
879ec4ba01eSPiotr Sroka }
880ec4ba01eSPiotr Sroka
881ec4ba01eSPiotr Sroka if (irq_status.status & INTR_STATUS_SDMA_TRIGG) {
882ec4ba01eSPiotr Sroka *out_sdma_size = readl_relaxed(cdns_ctrl->reg + SDMA_SIZE);
883ec4ba01eSPiotr Sroka *out_sdma_trd = readl_relaxed(cdns_ctrl->reg + SDMA_TRD_NUM);
884ec4ba01eSPiotr Sroka *out_sdma_trd =
885ec4ba01eSPiotr Sroka FIELD_GET(SDMA_TRD_NUM_SDMA_TRD, *out_sdma_trd);
886ec4ba01eSPiotr Sroka } else {
887ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "SDMA error - irq_status %x\n",
888ec4ba01eSPiotr Sroka irq_status.status);
889ec4ba01eSPiotr Sroka return -EIO;
890ec4ba01eSPiotr Sroka }
891ec4ba01eSPiotr Sroka
892ec4ba01eSPiotr Sroka return 0;
893ec4ba01eSPiotr Sroka }
894ec4ba01eSPiotr Sroka
cadence_nand_get_caps(struct cdns_nand_ctrl * cdns_ctrl)895ec4ba01eSPiotr Sroka static void cadence_nand_get_caps(struct cdns_nand_ctrl *cdns_ctrl)
896ec4ba01eSPiotr Sroka {
897ec4ba01eSPiotr Sroka u32 reg;
898ec4ba01eSPiotr Sroka
899ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + CTRL_FEATURES);
900ec4ba01eSPiotr Sroka
901ec4ba01eSPiotr Sroka cdns_ctrl->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg);
902ec4ba01eSPiotr Sroka
903ec4ba01eSPiotr Sroka if (FIELD_GET(CTRL_FEATURES_DMA_DWITH64, reg))
904ec4ba01eSPiotr Sroka cdns_ctrl->caps2.data_dma_width = 8;
905ec4ba01eSPiotr Sroka else
906ec4ba01eSPiotr Sroka cdns_ctrl->caps2.data_dma_width = 4;
907ec4ba01eSPiotr Sroka
908ec4ba01eSPiotr Sroka if (reg & CTRL_FEATURES_CONTROL_DATA)
909ec4ba01eSPiotr Sroka cdns_ctrl->caps2.data_control_supp = true;
910ec4ba01eSPiotr Sroka
911ec4ba01eSPiotr Sroka if (reg & (CTRL_FEATURES_NVDDR_2_3
912ec4ba01eSPiotr Sroka | CTRL_FEATURES_NVDDR))
913ec4ba01eSPiotr Sroka cdns_ctrl->caps2.is_phy_type_dll = true;
914ec4ba01eSPiotr Sroka }
915ec4ba01eSPiotr Sroka
916ec4ba01eSPiotr Sroka /* Prepare CDMA descriptor. */
917ec4ba01eSPiotr Sroka static void
cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl * cdns_ctrl,char nf_mem,u32 flash_ptr,dma_addr_t mem_ptr,dma_addr_t ctrl_data_ptr,u16 ctype)918ec4ba01eSPiotr Sroka cadence_nand_cdma_desc_prepare(struct cdns_nand_ctrl *cdns_ctrl,
9194aa906f1SVasyl Gomonovych char nf_mem, u32 flash_ptr, dma_addr_t mem_ptr,
9204aa906f1SVasyl Gomonovych dma_addr_t ctrl_data_ptr, u16 ctype)
921ec4ba01eSPiotr Sroka {
922ec4ba01eSPiotr Sroka struct cadence_nand_cdma_desc *cdma_desc = cdns_ctrl->cdma_desc;
923ec4ba01eSPiotr Sroka
924ec4ba01eSPiotr Sroka memset(cdma_desc, 0, sizeof(struct cadence_nand_cdma_desc));
925ec4ba01eSPiotr Sroka
926ec4ba01eSPiotr Sroka /* Set fields for one descriptor. */
927ec4ba01eSPiotr Sroka cdma_desc->flash_pointer = flash_ptr;
928ec4ba01eSPiotr Sroka if (cdns_ctrl->ctrl_rev >= 13)
929ec4ba01eSPiotr Sroka cdma_desc->bank = nf_mem;
930ec4ba01eSPiotr Sroka else
931ec4ba01eSPiotr Sroka cdma_desc->flash_pointer |= (nf_mem << CDMA_CFPTR_MEM_SHIFT);
932ec4ba01eSPiotr Sroka
933ec4ba01eSPiotr Sroka cdma_desc->command_flags |= CDMA_CF_DMA_MASTER;
934ec4ba01eSPiotr Sroka cdma_desc->command_flags |= CDMA_CF_INT;
935ec4ba01eSPiotr Sroka
9364aa906f1SVasyl Gomonovych cdma_desc->memory_pointer = mem_ptr;
937ec4ba01eSPiotr Sroka cdma_desc->status = 0;
938ec4ba01eSPiotr Sroka cdma_desc->sync_flag_pointer = 0;
939ec4ba01eSPiotr Sroka cdma_desc->sync_arguments = 0;
940ec4ba01eSPiotr Sroka
941ec4ba01eSPiotr Sroka cdma_desc->command_type = ctype;
9424aa906f1SVasyl Gomonovych cdma_desc->ctrl_data_ptr = ctrl_data_ptr;
943ec4ba01eSPiotr Sroka }
944ec4ba01eSPiotr Sroka
cadence_nand_check_desc_error(struct cdns_nand_ctrl * cdns_ctrl,u32 desc_status)945ec4ba01eSPiotr Sroka static u8 cadence_nand_check_desc_error(struct cdns_nand_ctrl *cdns_ctrl,
946ec4ba01eSPiotr Sroka u32 desc_status)
947ec4ba01eSPiotr Sroka {
948ec4ba01eSPiotr Sroka if (desc_status & CDMA_CS_ERP)
949ec4ba01eSPiotr Sroka return STAT_ERASED;
950ec4ba01eSPiotr Sroka
951ec4ba01eSPiotr Sroka if (desc_status & CDMA_CS_UNCE)
952ec4ba01eSPiotr Sroka return STAT_ECC_UNCORR;
953ec4ba01eSPiotr Sroka
954ec4ba01eSPiotr Sroka if (desc_status & CDMA_CS_ERR) {
955ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, ":CDMA desc error flag detected.\n");
956ec4ba01eSPiotr Sroka return STAT_FAIL;
957ec4ba01eSPiotr Sroka }
958ec4ba01eSPiotr Sroka
959ec4ba01eSPiotr Sroka if (FIELD_GET(CDMA_CS_MAXERR, desc_status))
960ec4ba01eSPiotr Sroka return STAT_ECC_CORR;
961ec4ba01eSPiotr Sroka
962ec4ba01eSPiotr Sroka return STAT_FAIL;
963ec4ba01eSPiotr Sroka }
964ec4ba01eSPiotr Sroka
cadence_nand_cdma_finish(struct cdns_nand_ctrl * cdns_ctrl)965ec4ba01eSPiotr Sroka static int cadence_nand_cdma_finish(struct cdns_nand_ctrl *cdns_ctrl)
966ec4ba01eSPiotr Sroka {
967ec4ba01eSPiotr Sroka struct cadence_nand_cdma_desc *desc_ptr = cdns_ctrl->cdma_desc;
968ec4ba01eSPiotr Sroka u8 status = STAT_BUSY;
969ec4ba01eSPiotr Sroka
970ec4ba01eSPiotr Sroka if (desc_ptr->status & CDMA_CS_FAIL) {
971ec4ba01eSPiotr Sroka status = cadence_nand_check_desc_error(cdns_ctrl,
972ec4ba01eSPiotr Sroka desc_ptr->status);
973ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, ":CDMA error %x\n", desc_ptr->status);
974ec4ba01eSPiotr Sroka } else if (desc_ptr->status & CDMA_CS_COMP) {
975ec4ba01eSPiotr Sroka /* Descriptor finished with no errors. */
976ec4ba01eSPiotr Sroka if (desc_ptr->command_flags & CDMA_CF_CONT) {
977ec4ba01eSPiotr Sroka dev_info(cdns_ctrl->dev, "DMA unsupported flag is set");
978ec4ba01eSPiotr Sroka status = STAT_UNKNOWN;
979ec4ba01eSPiotr Sroka } else {
980ec4ba01eSPiotr Sroka /* Last descriptor. */
981ec4ba01eSPiotr Sroka status = STAT_OK;
982ec4ba01eSPiotr Sroka }
983ec4ba01eSPiotr Sroka }
984ec4ba01eSPiotr Sroka
985ec4ba01eSPiotr Sroka return status;
986ec4ba01eSPiotr Sroka }
987ec4ba01eSPiotr Sroka
cadence_nand_cdma_send(struct cdns_nand_ctrl * cdns_ctrl,u8 thread)988ec4ba01eSPiotr Sroka static int cadence_nand_cdma_send(struct cdns_nand_ctrl *cdns_ctrl,
989ec4ba01eSPiotr Sroka u8 thread)
990ec4ba01eSPiotr Sroka {
991ec4ba01eSPiotr Sroka u32 reg;
992ec4ba01eSPiotr Sroka int status;
993ec4ba01eSPiotr Sroka
994ec4ba01eSPiotr Sroka /* Wait for thread ready. */
995ec4ba01eSPiotr Sroka status = cadence_nand_wait_for_value(cdns_ctrl, TRD_STATUS,
996ec4ba01eSPiotr Sroka 1000000,
997ec4ba01eSPiotr Sroka BIT(thread), true);
998ec4ba01eSPiotr Sroka if (status)
999ec4ba01eSPiotr Sroka return status;
1000ec4ba01eSPiotr Sroka
1001ec4ba01eSPiotr Sroka cadence_nand_reset_irq(cdns_ctrl);
10020d7d6c81SPiotr Sroka reinit_completion(&cdns_ctrl->complete);
1003ec4ba01eSPiotr Sroka
1004ec4ba01eSPiotr Sroka writel_relaxed((u32)cdns_ctrl->dma_cdma_desc,
1005ec4ba01eSPiotr Sroka cdns_ctrl->reg + CMD_REG2);
1006ec4ba01eSPiotr Sroka writel_relaxed(0, cdns_ctrl->reg + CMD_REG3);
1007ec4ba01eSPiotr Sroka
1008ec4ba01eSPiotr Sroka /* Select CDMA mode. */
1009ec4ba01eSPiotr Sroka reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_CDMA);
1010ec4ba01eSPiotr Sroka /* Thread number. */
1011ec4ba01eSPiotr Sroka reg |= FIELD_PREP(CMD_REG0_TN, thread);
1012ec4ba01eSPiotr Sroka /* Issue command. */
1013ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0);
1014ec4ba01eSPiotr Sroka
1015ec4ba01eSPiotr Sroka return 0;
1016ec4ba01eSPiotr Sroka }
1017ec4ba01eSPiotr Sroka
1018ec4ba01eSPiotr Sroka /* Send SDMA command and wait for finish. */
1019ec4ba01eSPiotr Sroka static u32
cadence_nand_cdma_send_and_wait(struct cdns_nand_ctrl * cdns_ctrl,u8 thread)1020ec4ba01eSPiotr Sroka cadence_nand_cdma_send_and_wait(struct cdns_nand_ctrl *cdns_ctrl,
1021ec4ba01eSPiotr Sroka u8 thread)
1022ec4ba01eSPiotr Sroka {
1023ec4ba01eSPiotr Sroka struct cadence_nand_irq_status irq_mask, irq_status = {0};
1024ec4ba01eSPiotr Sroka int status;
1025ec4ba01eSPiotr Sroka
1026ec4ba01eSPiotr Sroka irq_mask.trd_status = BIT(thread);
1027ec4ba01eSPiotr Sroka irq_mask.trd_error = BIT(thread);
1028ec4ba01eSPiotr Sroka irq_mask.status = INTR_STATUS_CDMA_TERR;
1029ec4ba01eSPiotr Sroka
1030ec4ba01eSPiotr Sroka cadence_nand_set_irq_mask(cdns_ctrl, &irq_mask);
1031ec4ba01eSPiotr Sroka
1032ec4ba01eSPiotr Sroka status = cadence_nand_cdma_send(cdns_ctrl, thread);
1033ec4ba01eSPiotr Sroka if (status)
1034ec4ba01eSPiotr Sroka return status;
1035ec4ba01eSPiotr Sroka
1036ec4ba01eSPiotr Sroka cadence_nand_wait_for_irq(cdns_ctrl, &irq_mask, &irq_status);
1037ec4ba01eSPiotr Sroka
1038ec4ba01eSPiotr Sroka if (irq_status.status == 0 && irq_status.trd_status == 0 &&
1039ec4ba01eSPiotr Sroka irq_status.trd_error == 0) {
1040ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "CDMA command timeout\n");
1041ec4ba01eSPiotr Sroka return -ETIMEDOUT;
1042ec4ba01eSPiotr Sroka }
1043ec4ba01eSPiotr Sroka if (irq_status.status & irq_mask.status) {
1044ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "CDMA command failed\n");
1045ec4ba01eSPiotr Sroka return -EIO;
1046ec4ba01eSPiotr Sroka }
1047ec4ba01eSPiotr Sroka
1048ec4ba01eSPiotr Sroka return 0;
1049ec4ba01eSPiotr Sroka }
1050ec4ba01eSPiotr Sroka
1051ec4ba01eSPiotr Sroka /*
1052ec4ba01eSPiotr Sroka * ECC size depends on configured ECC strength and on maximum supported
1053ec4ba01eSPiotr Sroka * ECC step size.
1054ec4ba01eSPiotr Sroka */
cadence_nand_calc_ecc_bytes(int max_step_size,int strength)1055ec4ba01eSPiotr Sroka static int cadence_nand_calc_ecc_bytes(int max_step_size, int strength)
1056ec4ba01eSPiotr Sroka {
1057ec4ba01eSPiotr Sroka int nbytes = DIV_ROUND_UP(fls(8 * max_step_size) * strength, 8);
1058ec4ba01eSPiotr Sroka
1059ec4ba01eSPiotr Sroka return ALIGN(nbytes, 2);
1060ec4ba01eSPiotr Sroka }
1061ec4ba01eSPiotr Sroka
1062ec4ba01eSPiotr Sroka #define CADENCE_NAND_CALC_ECC_BYTES(max_step_size) \
1063ec4ba01eSPiotr Sroka static int \
1064ec4ba01eSPiotr Sroka cadence_nand_calc_ecc_bytes_##max_step_size(int step_size, \
1065ec4ba01eSPiotr Sroka int strength)\
1066ec4ba01eSPiotr Sroka {\
1067ec4ba01eSPiotr Sroka return cadence_nand_calc_ecc_bytes(max_step_size, strength);\
1068ec4ba01eSPiotr Sroka }
1069ec4ba01eSPiotr Sroka
1070ec4ba01eSPiotr Sroka CADENCE_NAND_CALC_ECC_BYTES(256)
1071ec4ba01eSPiotr Sroka CADENCE_NAND_CALC_ECC_BYTES(512)
1072ec4ba01eSPiotr Sroka CADENCE_NAND_CALC_ECC_BYTES(1024)
1073ec4ba01eSPiotr Sroka CADENCE_NAND_CALC_ECC_BYTES(2048)
1074ec4ba01eSPiotr Sroka CADENCE_NAND_CALC_ECC_BYTES(4096)
1075ec4ba01eSPiotr Sroka
1076ec4ba01eSPiotr Sroka /* Function reads BCH capabilities. */
cadence_nand_read_bch_caps(struct cdns_nand_ctrl * cdns_ctrl)1077ec4ba01eSPiotr Sroka static int cadence_nand_read_bch_caps(struct cdns_nand_ctrl *cdns_ctrl)
1078ec4ba01eSPiotr Sroka {
1079ec4ba01eSPiotr Sroka struct nand_ecc_caps *ecc_caps = &cdns_ctrl->ecc_caps;
1080ec4ba01eSPiotr Sroka int max_step_size = 0, nstrengths, i;
1081ec4ba01eSPiotr Sroka u32 reg;
1082ec4ba01eSPiotr Sroka
1083397deafcSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_3);
1084397deafcSPiotr Sroka cdns_ctrl->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg);
1085397deafcSPiotr Sroka if (cdns_ctrl->bch_metadata_size < 4) {
1086397deafcSPiotr Sroka dev_err(cdns_ctrl->dev,
1087397deafcSPiotr Sroka "Driver needs at least 4 bytes of BCH meta data\n");
1088397deafcSPiotr Sroka return -EIO;
1089397deafcSPiotr Sroka }
1090397deafcSPiotr Sroka
1091ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_0);
1092ec4ba01eSPiotr Sroka cdns_ctrl->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg);
1093ec4ba01eSPiotr Sroka cdns_ctrl->ecc_strengths[1] = FIELD_GET(BCH_CFG_0_CORR_CAP_1, reg);
1094ec4ba01eSPiotr Sroka cdns_ctrl->ecc_strengths[2] = FIELD_GET(BCH_CFG_0_CORR_CAP_2, reg);
1095ec4ba01eSPiotr Sroka cdns_ctrl->ecc_strengths[3] = FIELD_GET(BCH_CFG_0_CORR_CAP_3, reg);
1096ec4ba01eSPiotr Sroka
1097ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_1);
1098ec4ba01eSPiotr Sroka cdns_ctrl->ecc_strengths[4] = FIELD_GET(BCH_CFG_1_CORR_CAP_4, reg);
1099ec4ba01eSPiotr Sroka cdns_ctrl->ecc_strengths[5] = FIELD_GET(BCH_CFG_1_CORR_CAP_5, reg);
1100ec4ba01eSPiotr Sroka cdns_ctrl->ecc_strengths[6] = FIELD_GET(BCH_CFG_1_CORR_CAP_6, reg);
1101ec4ba01eSPiotr Sroka cdns_ctrl->ecc_strengths[7] = FIELD_GET(BCH_CFG_1_CORR_CAP_7, reg);
1102ec4ba01eSPiotr Sroka
1103ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_2);
1104ec4ba01eSPiotr Sroka cdns_ctrl->ecc_stepinfos[0].stepsize =
1105ec4ba01eSPiotr Sroka FIELD_GET(BCH_CFG_2_SECT_0, reg);
1106ec4ba01eSPiotr Sroka
1107ec4ba01eSPiotr Sroka cdns_ctrl->ecc_stepinfos[1].stepsize =
1108ec4ba01eSPiotr Sroka FIELD_GET(BCH_CFG_2_SECT_1, reg);
1109ec4ba01eSPiotr Sroka
1110ec4ba01eSPiotr Sroka nstrengths = 0;
1111ec4ba01eSPiotr Sroka for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) {
1112ec4ba01eSPiotr Sroka if (cdns_ctrl->ecc_strengths[i] != 0)
1113ec4ba01eSPiotr Sroka nstrengths++;
1114ec4ba01eSPiotr Sroka }
1115ec4ba01eSPiotr Sroka
1116ec4ba01eSPiotr Sroka ecc_caps->nstepinfos = 0;
1117ec4ba01eSPiotr Sroka for (i = 0; i < BCH_MAX_NUM_SECTOR_SIZES; i++) {
1118ec4ba01eSPiotr Sroka /* ECC strengths are common for all step infos. */
1119ec4ba01eSPiotr Sroka cdns_ctrl->ecc_stepinfos[i].nstrengths = nstrengths;
1120ec4ba01eSPiotr Sroka cdns_ctrl->ecc_stepinfos[i].strengths =
1121ec4ba01eSPiotr Sroka cdns_ctrl->ecc_strengths;
1122ec4ba01eSPiotr Sroka
1123ec4ba01eSPiotr Sroka if (cdns_ctrl->ecc_stepinfos[i].stepsize != 0)
1124ec4ba01eSPiotr Sroka ecc_caps->nstepinfos++;
1125ec4ba01eSPiotr Sroka
1126ec4ba01eSPiotr Sroka if (cdns_ctrl->ecc_stepinfos[i].stepsize > max_step_size)
1127ec4ba01eSPiotr Sroka max_step_size = cdns_ctrl->ecc_stepinfos[i].stepsize;
1128ec4ba01eSPiotr Sroka }
1129ec4ba01eSPiotr Sroka ecc_caps->stepinfos = &cdns_ctrl->ecc_stepinfos[0];
1130ec4ba01eSPiotr Sroka
1131ec4ba01eSPiotr Sroka switch (max_step_size) {
1132ec4ba01eSPiotr Sroka case 256:
1133ec4ba01eSPiotr Sroka ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_256;
1134ec4ba01eSPiotr Sroka break;
1135ec4ba01eSPiotr Sroka case 512:
1136ec4ba01eSPiotr Sroka ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_512;
1137ec4ba01eSPiotr Sroka break;
1138ec4ba01eSPiotr Sroka case 1024:
1139ec4ba01eSPiotr Sroka ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_1024;
1140ec4ba01eSPiotr Sroka break;
1141ec4ba01eSPiotr Sroka case 2048:
1142ec4ba01eSPiotr Sroka ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_2048;
1143ec4ba01eSPiotr Sroka break;
1144ec4ba01eSPiotr Sroka case 4096:
1145ec4ba01eSPiotr Sroka ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_4096;
1146ec4ba01eSPiotr Sroka break;
1147ec4ba01eSPiotr Sroka default:
1148ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
1149ec4ba01eSPiotr Sroka "Unsupported sector size(ecc step size) %d\n",
1150ec4ba01eSPiotr Sroka max_step_size);
1151ec4ba01eSPiotr Sroka return -EIO;
1152ec4ba01eSPiotr Sroka }
1153ec4ba01eSPiotr Sroka
1154ec4ba01eSPiotr Sroka return 0;
1155ec4ba01eSPiotr Sroka }
1156ec4ba01eSPiotr Sroka
1157ec4ba01eSPiotr Sroka /* Hardware initialization. */
cadence_nand_hw_init(struct cdns_nand_ctrl * cdns_ctrl)1158ec4ba01eSPiotr Sroka static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl)
1159ec4ba01eSPiotr Sroka {
1160ec4ba01eSPiotr Sroka int status;
1161ec4ba01eSPiotr Sroka u32 reg;
1162ec4ba01eSPiotr Sroka
1163ec4ba01eSPiotr Sroka status = cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
1164ec4ba01eSPiotr Sroka 1000000,
1165ec4ba01eSPiotr Sroka CTRL_STATUS_INIT_COMP, false);
1166ec4ba01eSPiotr Sroka if (status)
1167ec4ba01eSPiotr Sroka return status;
1168ec4ba01eSPiotr Sroka
1169ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + CTRL_VERSION);
1170ec4ba01eSPiotr Sroka cdns_ctrl->ctrl_rev = FIELD_GET(CTRL_VERSION_REV, reg);
1171ec4ba01eSPiotr Sroka
1172ec4ba01eSPiotr Sroka dev_info(cdns_ctrl->dev,
1173ec4ba01eSPiotr Sroka "%s: cadence nand controller version reg %x\n",
1174ec4ba01eSPiotr Sroka __func__, reg);
1175ec4ba01eSPiotr Sroka
1176ec4ba01eSPiotr Sroka /* Disable cache and multiplane. */
1177ec4ba01eSPiotr Sroka writel_relaxed(0, cdns_ctrl->reg + MULTIPLANE_CFG);
1178ec4ba01eSPiotr Sroka writel_relaxed(0, cdns_ctrl->reg + CACHE_CFG);
1179ec4ba01eSPiotr Sroka
1180ec4ba01eSPiotr Sroka /* Clear all interrupts. */
1181ec4ba01eSPiotr Sroka writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS);
1182ec4ba01eSPiotr Sroka
1183ec4ba01eSPiotr Sroka cadence_nand_get_caps(cdns_ctrl);
1184397deafcSPiotr Sroka if (cadence_nand_read_bch_caps(cdns_ctrl))
1185397deafcSPiotr Sroka return -EIO;
1186ec4ba01eSPiotr Sroka
11877c3fc998SValentin Korenblit #ifndef CONFIG_64BIT
11887c3fc998SValentin Korenblit if (cdns_ctrl->caps2.data_dma_width == 8) {
11897c3fc998SValentin Korenblit dev_err(cdns_ctrl->dev,
11907c3fc998SValentin Korenblit "cannot access 64-bit dma on !64-bit architectures");
11917c3fc998SValentin Korenblit return -EIO;
11927c3fc998SValentin Korenblit }
11937c3fc998SValentin Korenblit #endif
11947c3fc998SValentin Korenblit
1195ec4ba01eSPiotr Sroka /*
1196ec4ba01eSPiotr Sroka * Set IO width access to 8.
1197ec4ba01eSPiotr Sroka * It is because during SW device discovering width access
1198ec4ba01eSPiotr Sroka * is expected to be 8.
1199ec4ba01eSPiotr Sroka */
1200ec4ba01eSPiotr Sroka status = cadence_nand_set_access_width16(cdns_ctrl, false);
1201ec4ba01eSPiotr Sroka
1202ec4ba01eSPiotr Sroka return status;
1203ec4ba01eSPiotr Sroka }
1204ec4ba01eSPiotr Sroka
1205ec4ba01eSPiotr Sroka #define TT_MAIN_OOB_AREAS 2
1206ec4ba01eSPiotr Sroka #define TT_RAW_PAGE 3
1207ec4ba01eSPiotr Sroka #define TT_BBM 4
1208ec4ba01eSPiotr Sroka #define TT_MAIN_OOB_AREA_EXT 5
1209ec4ba01eSPiotr Sroka
1210ec4ba01eSPiotr Sroka /* Prepare size of data to transfer. */
1211ec4ba01eSPiotr Sroka static void
cadence_nand_prepare_data_size(struct nand_chip * chip,int transfer_type)1212ec4ba01eSPiotr Sroka cadence_nand_prepare_data_size(struct nand_chip *chip,
1213ec4ba01eSPiotr Sroka int transfer_type)
1214ec4ba01eSPiotr Sroka {
1215ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1216ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
1217ec4ba01eSPiotr Sroka struct mtd_info *mtd = nand_to_mtd(chip);
1218ec4ba01eSPiotr Sroka u32 sec_size = 0, offset = 0, sec_cnt = 1;
1219ec4ba01eSPiotr Sroka u32 last_sec_size = cdns_chip->sector_size;
1220ec4ba01eSPiotr Sroka u32 data_ctrl_size = 0;
1221ec4ba01eSPiotr Sroka u32 reg = 0;
1222ec4ba01eSPiotr Sroka
1223ec4ba01eSPiotr Sroka if (cdns_ctrl->curr_trans_type == transfer_type)
1224ec4ba01eSPiotr Sroka return;
1225ec4ba01eSPiotr Sroka
1226ec4ba01eSPiotr Sroka switch (transfer_type) {
1227ec4ba01eSPiotr Sroka case TT_MAIN_OOB_AREA_EXT:
1228ec4ba01eSPiotr Sroka sec_cnt = cdns_chip->sector_count;
1229ec4ba01eSPiotr Sroka sec_size = cdns_chip->sector_size;
1230ec4ba01eSPiotr Sroka data_ctrl_size = cdns_chip->avail_oob_size;
1231ec4ba01eSPiotr Sroka break;
1232ec4ba01eSPiotr Sroka case TT_MAIN_OOB_AREAS:
1233ec4ba01eSPiotr Sroka sec_cnt = cdns_chip->sector_count;
1234ec4ba01eSPiotr Sroka last_sec_size = cdns_chip->sector_size
1235ec4ba01eSPiotr Sroka + cdns_chip->avail_oob_size;
1236ec4ba01eSPiotr Sroka sec_size = cdns_chip->sector_size;
1237ec4ba01eSPiotr Sroka break;
1238ec4ba01eSPiotr Sroka case TT_RAW_PAGE:
1239ec4ba01eSPiotr Sroka last_sec_size = mtd->writesize + mtd->oobsize;
1240ec4ba01eSPiotr Sroka break;
1241ec4ba01eSPiotr Sroka case TT_BBM:
1242ec4ba01eSPiotr Sroka offset = mtd->writesize + cdns_chip->bbm_offs;
1243ec4ba01eSPiotr Sroka last_sec_size = 8;
1244ec4ba01eSPiotr Sroka break;
1245ec4ba01eSPiotr Sroka }
1246ec4ba01eSPiotr Sroka
1247ec4ba01eSPiotr Sroka reg = 0;
1248ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TRAN_CFG_0_OFFSET, offset);
1249ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TRAN_CFG_0_SEC_CNT, sec_cnt);
1250ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_0);
1251ec4ba01eSPiotr Sroka
1252ec4ba01eSPiotr Sroka reg = 0;
1253ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TRAN_CFG_1_LAST_SEC_SIZE, last_sec_size);
1254ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TRAN_CFG_1_SECTOR_SIZE, sec_size);
1255ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_1);
1256ec4ba01eSPiotr Sroka
1257ec4ba01eSPiotr Sroka if (cdns_ctrl->caps2.data_control_supp) {
1258ec4ba01eSPiotr Sroka reg = readl_relaxed(cdns_ctrl->reg + CONTROL_DATA_CTRL);
1259ec4ba01eSPiotr Sroka reg &= ~CONTROL_DATA_CTRL_SIZE;
1260ec4ba01eSPiotr Sroka reg |= FIELD_PREP(CONTROL_DATA_CTRL_SIZE, data_ctrl_size);
1261ec4ba01eSPiotr Sroka writel_relaxed(reg, cdns_ctrl->reg + CONTROL_DATA_CTRL);
1262ec4ba01eSPiotr Sroka }
1263ec4ba01eSPiotr Sroka
1264ec4ba01eSPiotr Sroka cdns_ctrl->curr_trans_type = transfer_type;
1265ec4ba01eSPiotr Sroka }
1266ec4ba01eSPiotr Sroka
1267ec4ba01eSPiotr Sroka static int
cadence_nand_cdma_transfer(struct cdns_nand_ctrl * cdns_ctrl,u8 chip_nr,int page,void * buf,void * ctrl_dat,u32 buf_size,u32 ctrl_dat_size,enum dma_data_direction dir,bool with_ecc)1268ec4ba01eSPiotr Sroka cadence_nand_cdma_transfer(struct cdns_nand_ctrl *cdns_ctrl, u8 chip_nr,
1269ec4ba01eSPiotr Sroka int page, void *buf, void *ctrl_dat, u32 buf_size,
1270ec4ba01eSPiotr Sroka u32 ctrl_dat_size, enum dma_data_direction dir,
1271ec4ba01eSPiotr Sroka bool with_ecc)
1272ec4ba01eSPiotr Sroka {
1273ec4ba01eSPiotr Sroka dma_addr_t dma_buf, dma_ctrl_dat = 0;
1274ec4ba01eSPiotr Sroka u8 thread_nr = chip_nr;
1275ec4ba01eSPiotr Sroka int status;
1276ec4ba01eSPiotr Sroka u16 ctype;
1277ec4ba01eSPiotr Sroka
1278ec4ba01eSPiotr Sroka if (dir == DMA_FROM_DEVICE)
1279ec4ba01eSPiotr Sroka ctype = CDMA_CT_RD;
1280ec4ba01eSPiotr Sroka else
1281ec4ba01eSPiotr Sroka ctype = CDMA_CT_WR;
1282ec4ba01eSPiotr Sroka
1283ec4ba01eSPiotr Sroka cadence_nand_set_ecc_enable(cdns_ctrl, with_ecc);
1284ec4ba01eSPiotr Sroka
1285ec4ba01eSPiotr Sroka dma_buf = dma_map_single(cdns_ctrl->dev, buf, buf_size, dir);
1286ec4ba01eSPiotr Sroka if (dma_mapping_error(cdns_ctrl->dev, dma_buf)) {
1287ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n");
1288ec4ba01eSPiotr Sroka return -EIO;
1289ec4ba01eSPiotr Sroka }
1290ec4ba01eSPiotr Sroka
1291ec4ba01eSPiotr Sroka if (ctrl_dat && ctrl_dat_size) {
1292ec4ba01eSPiotr Sroka dma_ctrl_dat = dma_map_single(cdns_ctrl->dev, ctrl_dat,
1293ec4ba01eSPiotr Sroka ctrl_dat_size, dir);
1294ec4ba01eSPiotr Sroka if (dma_mapping_error(cdns_ctrl->dev, dma_ctrl_dat)) {
1295ec4ba01eSPiotr Sroka dma_unmap_single(cdns_ctrl->dev, dma_buf,
1296ec4ba01eSPiotr Sroka buf_size, dir);
1297ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n");
1298ec4ba01eSPiotr Sroka return -EIO;
1299ec4ba01eSPiotr Sroka }
1300ec4ba01eSPiotr Sroka }
1301ec4ba01eSPiotr Sroka
1302ec4ba01eSPiotr Sroka cadence_nand_cdma_desc_prepare(cdns_ctrl, chip_nr, page,
13034aa906f1SVasyl Gomonovych dma_buf, dma_ctrl_dat, ctype);
1304ec4ba01eSPiotr Sroka
1305ec4ba01eSPiotr Sroka status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
1306ec4ba01eSPiotr Sroka
1307ec4ba01eSPiotr Sroka dma_unmap_single(cdns_ctrl->dev, dma_buf,
1308ec4ba01eSPiotr Sroka buf_size, dir);
1309ec4ba01eSPiotr Sroka
1310ec4ba01eSPiotr Sroka if (ctrl_dat && ctrl_dat_size)
1311ec4ba01eSPiotr Sroka dma_unmap_single(cdns_ctrl->dev, dma_ctrl_dat,
1312ec4ba01eSPiotr Sroka ctrl_dat_size, dir);
1313ec4ba01eSPiotr Sroka if (status)
1314ec4ba01eSPiotr Sroka return status;
1315ec4ba01eSPiotr Sroka
1316ec4ba01eSPiotr Sroka return cadence_nand_cdma_finish(cdns_ctrl);
1317ec4ba01eSPiotr Sroka }
1318ec4ba01eSPiotr Sroka
cadence_nand_set_timings(struct cdns_nand_ctrl * cdns_ctrl,struct cadence_nand_timings * t)1319ec4ba01eSPiotr Sroka static void cadence_nand_set_timings(struct cdns_nand_ctrl *cdns_ctrl,
1320ec4ba01eSPiotr Sroka struct cadence_nand_timings *t)
1321ec4ba01eSPiotr Sroka {
1322ec4ba01eSPiotr Sroka writel_relaxed(t->async_toggle_timings,
1323ec4ba01eSPiotr Sroka cdns_ctrl->reg + ASYNC_TOGGLE_TIMINGS);
1324ec4ba01eSPiotr Sroka writel_relaxed(t->timings0, cdns_ctrl->reg + TIMINGS0);
1325ec4ba01eSPiotr Sroka writel_relaxed(t->timings1, cdns_ctrl->reg + TIMINGS1);
1326ec4ba01eSPiotr Sroka writel_relaxed(t->timings2, cdns_ctrl->reg + TIMINGS2);
1327ec4ba01eSPiotr Sroka
1328ec4ba01eSPiotr Sroka if (cdns_ctrl->caps2.is_phy_type_dll)
1329ec4ba01eSPiotr Sroka writel_relaxed(t->dll_phy_ctrl, cdns_ctrl->reg + DLL_PHY_CTRL);
1330ec4ba01eSPiotr Sroka
1331ec4ba01eSPiotr Sroka writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL);
1332ec4ba01eSPiotr Sroka
1333ec4ba01eSPiotr Sroka if (cdns_ctrl->caps2.is_phy_type_dll) {
1334ec4ba01eSPiotr Sroka writel_relaxed(0, cdns_ctrl->reg + PHY_TSEL);
1335ec4ba01eSPiotr Sroka writel_relaxed(2, cdns_ctrl->reg + PHY_DQ_TIMING);
1336ec4ba01eSPiotr Sroka writel_relaxed(t->phy_dqs_timing,
1337ec4ba01eSPiotr Sroka cdns_ctrl->reg + PHY_DQS_TIMING);
1338ec4ba01eSPiotr Sroka writel_relaxed(t->phy_gate_lpbk_ctrl,
1339ec4ba01eSPiotr Sroka cdns_ctrl->reg + PHY_GATE_LPBK_CTRL);
1340ec4ba01eSPiotr Sroka writel_relaxed(PHY_DLL_MASTER_CTRL_BYPASS_MODE,
1341ec4ba01eSPiotr Sroka cdns_ctrl->reg + PHY_DLL_MASTER_CTRL);
1342ec4ba01eSPiotr Sroka writel_relaxed(0, cdns_ctrl->reg + PHY_DLL_SLAVE_CTRL);
1343ec4ba01eSPiotr Sroka }
1344ec4ba01eSPiotr Sroka }
1345ec4ba01eSPiotr Sroka
cadence_nand_select_target(struct nand_chip * chip)1346ec4ba01eSPiotr Sroka static int cadence_nand_select_target(struct nand_chip *chip)
1347ec4ba01eSPiotr Sroka {
1348ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1349ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
1350ec4ba01eSPiotr Sroka
1351ec4ba01eSPiotr Sroka if (chip == cdns_ctrl->selected_chip)
1352ec4ba01eSPiotr Sroka return 0;
1353ec4ba01eSPiotr Sroka
1354ec4ba01eSPiotr Sroka if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
1355ec4ba01eSPiotr Sroka 1000000,
1356ec4ba01eSPiotr Sroka CTRL_STATUS_CTRL_BUSY, true))
1357ec4ba01eSPiotr Sroka return -ETIMEDOUT;
1358ec4ba01eSPiotr Sroka
1359ec4ba01eSPiotr Sroka cadence_nand_set_timings(cdns_ctrl, &cdns_chip->timings);
1360ec4ba01eSPiotr Sroka
1361ec4ba01eSPiotr Sroka cadence_nand_set_ecc_strength(cdns_ctrl,
1362ec4ba01eSPiotr Sroka cdns_chip->corr_str_idx);
1363ec4ba01eSPiotr Sroka
1364ec4ba01eSPiotr Sroka cadence_nand_set_erase_detection(cdns_ctrl, true,
1365ec4ba01eSPiotr Sroka chip->ecc.strength);
1366ec4ba01eSPiotr Sroka
1367ec4ba01eSPiotr Sroka cdns_ctrl->curr_trans_type = -1;
1368ec4ba01eSPiotr Sroka cdns_ctrl->selected_chip = chip;
1369ec4ba01eSPiotr Sroka
1370ec4ba01eSPiotr Sroka return 0;
1371ec4ba01eSPiotr Sroka }
1372ec4ba01eSPiotr Sroka
cadence_nand_erase(struct nand_chip * chip,u32 page)1373ec4ba01eSPiotr Sroka static int cadence_nand_erase(struct nand_chip *chip, u32 page)
1374ec4ba01eSPiotr Sroka {
1375ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1376ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
1377ec4ba01eSPiotr Sroka int status;
1378ec4ba01eSPiotr Sroka u8 thread_nr = cdns_chip->cs[chip->cur_cs];
1379ec4ba01eSPiotr Sroka
1380ec4ba01eSPiotr Sroka cadence_nand_cdma_desc_prepare(cdns_ctrl,
1381ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
13824aa906f1SVasyl Gomonovych page, 0, 0,
1383ec4ba01eSPiotr Sroka CDMA_CT_ERASE);
1384ec4ba01eSPiotr Sroka status = cadence_nand_cdma_send_and_wait(cdns_ctrl, thread_nr);
1385ec4ba01eSPiotr Sroka if (status) {
1386ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "erase operation failed\n");
1387ec4ba01eSPiotr Sroka return -EIO;
1388ec4ba01eSPiotr Sroka }
1389ec4ba01eSPiotr Sroka
1390ec4ba01eSPiotr Sroka status = cadence_nand_cdma_finish(cdns_ctrl);
1391ec4ba01eSPiotr Sroka if (status)
1392ec4ba01eSPiotr Sroka return status;
1393ec4ba01eSPiotr Sroka
1394ec4ba01eSPiotr Sroka return 0;
1395ec4ba01eSPiotr Sroka }
1396ec4ba01eSPiotr Sroka
cadence_nand_read_bbm(struct nand_chip * chip,int page,u8 * buf)1397ec4ba01eSPiotr Sroka static int cadence_nand_read_bbm(struct nand_chip *chip, int page, u8 *buf)
1398ec4ba01eSPiotr Sroka {
1399ec4ba01eSPiotr Sroka int status;
1400ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1401ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
1402ec4ba01eSPiotr Sroka struct mtd_info *mtd = nand_to_mtd(chip);
1403ec4ba01eSPiotr Sroka
1404ec4ba01eSPiotr Sroka cadence_nand_prepare_data_size(chip, TT_BBM);
1405ec4ba01eSPiotr Sroka
1406ec4ba01eSPiotr Sroka cadence_nand_set_skip_bytes_conf(cdns_ctrl, 0, 0, 0);
1407ec4ba01eSPiotr Sroka
1408ec4ba01eSPiotr Sroka /*
1409ec4ba01eSPiotr Sroka * Read only bad block marker from offset
1410ec4ba01eSPiotr Sroka * defined by a memory manufacturer.
1411ec4ba01eSPiotr Sroka */
1412ec4ba01eSPiotr Sroka status = cadence_nand_cdma_transfer(cdns_ctrl,
1413ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
1414ec4ba01eSPiotr Sroka page, cdns_ctrl->buf, NULL,
1415ec4ba01eSPiotr Sroka mtd->oobsize,
1416ec4ba01eSPiotr Sroka 0, DMA_FROM_DEVICE, false);
1417ec4ba01eSPiotr Sroka if (status) {
1418ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "read BBM failed\n");
1419ec4ba01eSPiotr Sroka return -EIO;
1420ec4ba01eSPiotr Sroka }
1421ec4ba01eSPiotr Sroka
1422ec4ba01eSPiotr Sroka memcpy(buf + cdns_chip->bbm_offs, cdns_ctrl->buf, cdns_chip->bbm_len);
1423ec4ba01eSPiotr Sroka
1424ec4ba01eSPiotr Sroka return 0;
1425ec4ba01eSPiotr Sroka }
1426ec4ba01eSPiotr Sroka
cadence_nand_write_page(struct nand_chip * chip,const u8 * buf,int oob_required,int page)1427ec4ba01eSPiotr Sroka static int cadence_nand_write_page(struct nand_chip *chip,
1428ec4ba01eSPiotr Sroka const u8 *buf, int oob_required,
1429ec4ba01eSPiotr Sroka int page)
1430ec4ba01eSPiotr Sroka {
1431ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1432ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
1433ec4ba01eSPiotr Sroka struct mtd_info *mtd = nand_to_mtd(chip);
1434ec4ba01eSPiotr Sroka int status;
1435ec4ba01eSPiotr Sroka u16 marker_val = 0xFFFF;
1436ec4ba01eSPiotr Sroka
1437ec4ba01eSPiotr Sroka status = cadence_nand_select_target(chip);
1438ec4ba01eSPiotr Sroka if (status)
1439ec4ba01eSPiotr Sroka return status;
1440ec4ba01eSPiotr Sroka
1441ec4ba01eSPiotr Sroka cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len,
1442ec4ba01eSPiotr Sroka mtd->writesize
1443ec4ba01eSPiotr Sroka + cdns_chip->bbm_offs,
1444ec4ba01eSPiotr Sroka 1);
1445ec4ba01eSPiotr Sroka
1446ec4ba01eSPiotr Sroka if (oob_required) {
1447ec4ba01eSPiotr Sroka marker_val = *(u16 *)(chip->oob_poi
1448ec4ba01eSPiotr Sroka + cdns_chip->bbm_offs);
1449ec4ba01eSPiotr Sroka } else {
1450ec4ba01eSPiotr Sroka /* Set oob data to 0xFF. */
1451ec4ba01eSPiotr Sroka memset(cdns_ctrl->buf + mtd->writesize, 0xFF,
1452ec4ba01eSPiotr Sroka cdns_chip->avail_oob_size);
1453ec4ba01eSPiotr Sroka }
1454ec4ba01eSPiotr Sroka
1455ec4ba01eSPiotr Sroka cadence_nand_set_skip_marker_val(cdns_ctrl, marker_val);
1456ec4ba01eSPiotr Sroka
1457ec4ba01eSPiotr Sroka cadence_nand_prepare_data_size(chip, TT_MAIN_OOB_AREA_EXT);
1458ec4ba01eSPiotr Sroka
1459ec4ba01eSPiotr Sroka if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, mtd->writesize) &&
1460ec4ba01eSPiotr Sroka cdns_ctrl->caps2.data_control_supp) {
1461ec4ba01eSPiotr Sroka u8 *oob;
1462ec4ba01eSPiotr Sroka
1463ec4ba01eSPiotr Sroka if (oob_required)
1464ec4ba01eSPiotr Sroka oob = chip->oob_poi;
1465ec4ba01eSPiotr Sroka else
1466ec4ba01eSPiotr Sroka oob = cdns_ctrl->buf + mtd->writesize;
1467ec4ba01eSPiotr Sroka
1468ec4ba01eSPiotr Sroka status = cadence_nand_cdma_transfer(cdns_ctrl,
1469ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
1470ec4ba01eSPiotr Sroka page, (void *)buf, oob,
1471ec4ba01eSPiotr Sroka mtd->writesize,
1472ec4ba01eSPiotr Sroka cdns_chip->avail_oob_size,
1473ec4ba01eSPiotr Sroka DMA_TO_DEVICE, true);
1474ec4ba01eSPiotr Sroka if (status) {
1475ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "write page failed\n");
1476ec4ba01eSPiotr Sroka return -EIO;
1477ec4ba01eSPiotr Sroka }
1478ec4ba01eSPiotr Sroka
1479ec4ba01eSPiotr Sroka return 0;
1480ec4ba01eSPiotr Sroka }
1481ec4ba01eSPiotr Sroka
1482ec4ba01eSPiotr Sroka if (oob_required) {
1483ec4ba01eSPiotr Sroka /* Transfer the data to the oob area. */
1484ec4ba01eSPiotr Sroka memcpy(cdns_ctrl->buf + mtd->writesize, chip->oob_poi,
1485ec4ba01eSPiotr Sroka cdns_chip->avail_oob_size);
1486ec4ba01eSPiotr Sroka }
1487ec4ba01eSPiotr Sroka
1488ec4ba01eSPiotr Sroka memcpy(cdns_ctrl->buf, buf, mtd->writesize);
1489ec4ba01eSPiotr Sroka
1490ec4ba01eSPiotr Sroka cadence_nand_prepare_data_size(chip, TT_MAIN_OOB_AREAS);
1491ec4ba01eSPiotr Sroka
1492ec4ba01eSPiotr Sroka return cadence_nand_cdma_transfer(cdns_ctrl,
1493ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
1494ec4ba01eSPiotr Sroka page, cdns_ctrl->buf, NULL,
1495ec4ba01eSPiotr Sroka mtd->writesize
1496ec4ba01eSPiotr Sroka + cdns_chip->avail_oob_size,
1497ec4ba01eSPiotr Sroka 0, DMA_TO_DEVICE, true);
1498ec4ba01eSPiotr Sroka }
1499ec4ba01eSPiotr Sroka
cadence_nand_write_oob(struct nand_chip * chip,int page)1500ec4ba01eSPiotr Sroka static int cadence_nand_write_oob(struct nand_chip *chip, int page)
1501ec4ba01eSPiotr Sroka {
1502ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1503ec4ba01eSPiotr Sroka struct mtd_info *mtd = nand_to_mtd(chip);
1504ec4ba01eSPiotr Sroka
1505ec4ba01eSPiotr Sroka memset(cdns_ctrl->buf, 0xFF, mtd->writesize);
1506ec4ba01eSPiotr Sroka
1507ec4ba01eSPiotr Sroka return cadence_nand_write_page(chip, cdns_ctrl->buf, 1, page);
1508ec4ba01eSPiotr Sroka }
1509ec4ba01eSPiotr Sroka
cadence_nand_write_page_raw(struct nand_chip * chip,const u8 * buf,int oob_required,int page)1510ec4ba01eSPiotr Sroka static int cadence_nand_write_page_raw(struct nand_chip *chip,
1511ec4ba01eSPiotr Sroka const u8 *buf, int oob_required,
1512ec4ba01eSPiotr Sroka int page)
1513ec4ba01eSPiotr Sroka {
1514ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1515ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
1516ec4ba01eSPiotr Sroka struct mtd_info *mtd = nand_to_mtd(chip);
1517ec4ba01eSPiotr Sroka int writesize = mtd->writesize;
1518ec4ba01eSPiotr Sroka int oobsize = mtd->oobsize;
1519ec4ba01eSPiotr Sroka int ecc_steps = chip->ecc.steps;
1520ec4ba01eSPiotr Sroka int ecc_size = chip->ecc.size;
1521ec4ba01eSPiotr Sroka int ecc_bytes = chip->ecc.bytes;
1522ec4ba01eSPiotr Sroka void *tmp_buf = cdns_ctrl->buf;
1523ec4ba01eSPiotr Sroka int oob_skip = cdns_chip->bbm_len;
1524ec4ba01eSPiotr Sroka size_t size = writesize + oobsize;
1525ec4ba01eSPiotr Sroka int i, pos, len;
1526ec4ba01eSPiotr Sroka int status = 0;
1527ec4ba01eSPiotr Sroka
1528ec4ba01eSPiotr Sroka status = cadence_nand_select_target(chip);
1529ec4ba01eSPiotr Sroka if (status)
1530ec4ba01eSPiotr Sroka return status;
1531ec4ba01eSPiotr Sroka
1532ec4ba01eSPiotr Sroka /*
1533ec4ba01eSPiotr Sroka * Fill the buffer with 0xff first except the full page transfer.
1534ec4ba01eSPiotr Sroka * This simplifies the logic.
1535ec4ba01eSPiotr Sroka */
1536ec4ba01eSPiotr Sroka if (!buf || !oob_required)
1537ec4ba01eSPiotr Sroka memset(tmp_buf, 0xff, size);
1538ec4ba01eSPiotr Sroka
1539ec4ba01eSPiotr Sroka cadence_nand_set_skip_bytes_conf(cdns_ctrl, 0, 0, 0);
1540ec4ba01eSPiotr Sroka
1541ec4ba01eSPiotr Sroka /* Arrange the buffer for syndrome payload/ecc layout. */
1542ec4ba01eSPiotr Sroka if (buf) {
1543ec4ba01eSPiotr Sroka for (i = 0; i < ecc_steps; i++) {
1544ec4ba01eSPiotr Sroka pos = i * (ecc_size + ecc_bytes);
1545ec4ba01eSPiotr Sroka len = ecc_size;
1546ec4ba01eSPiotr Sroka
1547ec4ba01eSPiotr Sroka if (pos >= writesize)
1548ec4ba01eSPiotr Sroka pos += oob_skip;
1549ec4ba01eSPiotr Sroka else if (pos + len > writesize)
1550ec4ba01eSPiotr Sroka len = writesize - pos;
1551ec4ba01eSPiotr Sroka
1552ec4ba01eSPiotr Sroka memcpy(tmp_buf + pos, buf, len);
1553ec4ba01eSPiotr Sroka buf += len;
1554ec4ba01eSPiotr Sroka if (len < ecc_size) {
1555ec4ba01eSPiotr Sroka len = ecc_size - len;
1556ec4ba01eSPiotr Sroka memcpy(tmp_buf + writesize + oob_skip, buf,
1557ec4ba01eSPiotr Sroka len);
1558ec4ba01eSPiotr Sroka buf += len;
1559ec4ba01eSPiotr Sroka }
1560ec4ba01eSPiotr Sroka }
1561ec4ba01eSPiotr Sroka }
1562ec4ba01eSPiotr Sroka
1563ec4ba01eSPiotr Sroka if (oob_required) {
1564ec4ba01eSPiotr Sroka const u8 *oob = chip->oob_poi;
1565ec4ba01eSPiotr Sroka u32 oob_data_offset = (cdns_chip->sector_count - 1) *
1566ec4ba01eSPiotr Sroka (cdns_chip->sector_size + chip->ecc.bytes)
1567ec4ba01eSPiotr Sroka + cdns_chip->sector_size + oob_skip;
1568ec4ba01eSPiotr Sroka
1569ec4ba01eSPiotr Sroka /* BBM at the beginning of the OOB area. */
1570ec4ba01eSPiotr Sroka memcpy(tmp_buf + writesize, oob, oob_skip);
1571ec4ba01eSPiotr Sroka
1572ec4ba01eSPiotr Sroka /* OOB free. */
1573ec4ba01eSPiotr Sroka memcpy(tmp_buf + oob_data_offset, oob,
1574ec4ba01eSPiotr Sroka cdns_chip->avail_oob_size);
1575ec4ba01eSPiotr Sroka oob += cdns_chip->avail_oob_size;
1576ec4ba01eSPiotr Sroka
1577ec4ba01eSPiotr Sroka /* OOB ECC. */
1578ec4ba01eSPiotr Sroka for (i = 0; i < ecc_steps; i++) {
1579ec4ba01eSPiotr Sroka pos = ecc_size + i * (ecc_size + ecc_bytes);
1580ec4ba01eSPiotr Sroka if (i == (ecc_steps - 1))
1581ec4ba01eSPiotr Sroka pos += cdns_chip->avail_oob_size;
1582ec4ba01eSPiotr Sroka
1583ec4ba01eSPiotr Sroka len = ecc_bytes;
1584ec4ba01eSPiotr Sroka
1585ec4ba01eSPiotr Sroka if (pos >= writesize)
1586ec4ba01eSPiotr Sroka pos += oob_skip;
1587ec4ba01eSPiotr Sroka else if (pos + len > writesize)
1588ec4ba01eSPiotr Sroka len = writesize - pos;
1589ec4ba01eSPiotr Sroka
1590ec4ba01eSPiotr Sroka memcpy(tmp_buf + pos, oob, len);
1591ec4ba01eSPiotr Sroka oob += len;
1592ec4ba01eSPiotr Sroka if (len < ecc_bytes) {
1593ec4ba01eSPiotr Sroka len = ecc_bytes - len;
1594ec4ba01eSPiotr Sroka memcpy(tmp_buf + writesize + oob_skip, oob,
1595ec4ba01eSPiotr Sroka len);
1596ec4ba01eSPiotr Sroka oob += len;
1597ec4ba01eSPiotr Sroka }
1598ec4ba01eSPiotr Sroka }
1599ec4ba01eSPiotr Sroka }
1600ec4ba01eSPiotr Sroka
1601ec4ba01eSPiotr Sroka cadence_nand_prepare_data_size(chip, TT_RAW_PAGE);
1602ec4ba01eSPiotr Sroka
1603ec4ba01eSPiotr Sroka return cadence_nand_cdma_transfer(cdns_ctrl,
1604ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
1605ec4ba01eSPiotr Sroka page, cdns_ctrl->buf, NULL,
1606ec4ba01eSPiotr Sroka mtd->writesize +
1607ec4ba01eSPiotr Sroka mtd->oobsize,
1608ec4ba01eSPiotr Sroka 0, DMA_TO_DEVICE, false);
1609ec4ba01eSPiotr Sroka }
1610ec4ba01eSPiotr Sroka
cadence_nand_write_oob_raw(struct nand_chip * chip,int page)1611ec4ba01eSPiotr Sroka static int cadence_nand_write_oob_raw(struct nand_chip *chip,
1612ec4ba01eSPiotr Sroka int page)
1613ec4ba01eSPiotr Sroka {
1614ec4ba01eSPiotr Sroka return cadence_nand_write_page_raw(chip, NULL, true, page);
1615ec4ba01eSPiotr Sroka }
1616ec4ba01eSPiotr Sroka
cadence_nand_read_page(struct nand_chip * chip,u8 * buf,int oob_required,int page)1617ec4ba01eSPiotr Sroka static int cadence_nand_read_page(struct nand_chip *chip,
1618ec4ba01eSPiotr Sroka u8 *buf, int oob_required, int page)
1619ec4ba01eSPiotr Sroka {
1620ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1621ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
1622ec4ba01eSPiotr Sroka struct mtd_info *mtd = nand_to_mtd(chip);
1623ec4ba01eSPiotr Sroka int status = 0;
1624ec4ba01eSPiotr Sroka int ecc_err_count = 0;
1625ec4ba01eSPiotr Sroka
1626ec4ba01eSPiotr Sroka status = cadence_nand_select_target(chip);
1627ec4ba01eSPiotr Sroka if (status)
1628ec4ba01eSPiotr Sroka return status;
1629ec4ba01eSPiotr Sroka
1630ec4ba01eSPiotr Sroka cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len,
1631ec4ba01eSPiotr Sroka mtd->writesize
1632ec4ba01eSPiotr Sroka + cdns_chip->bbm_offs, 1);
1633ec4ba01eSPiotr Sroka
1634ec4ba01eSPiotr Sroka /*
1635ec4ba01eSPiotr Sroka * If data buffer can be accessed by DMA and data_control feature
1636ec4ba01eSPiotr Sroka * is supported then transfer data and oob directly.
1637ec4ba01eSPiotr Sroka */
1638ec4ba01eSPiotr Sroka if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, mtd->writesize) &&
1639ec4ba01eSPiotr Sroka cdns_ctrl->caps2.data_control_supp) {
1640ec4ba01eSPiotr Sroka u8 *oob;
1641ec4ba01eSPiotr Sroka
1642ec4ba01eSPiotr Sroka if (oob_required)
1643ec4ba01eSPiotr Sroka oob = chip->oob_poi;
1644ec4ba01eSPiotr Sroka else
1645ec4ba01eSPiotr Sroka oob = cdns_ctrl->buf + mtd->writesize;
1646ec4ba01eSPiotr Sroka
1647ec4ba01eSPiotr Sroka cadence_nand_prepare_data_size(chip, TT_MAIN_OOB_AREA_EXT);
1648ec4ba01eSPiotr Sroka status = cadence_nand_cdma_transfer(cdns_ctrl,
1649ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
1650ec4ba01eSPiotr Sroka page, buf, oob,
1651ec4ba01eSPiotr Sroka mtd->writesize,
1652ec4ba01eSPiotr Sroka cdns_chip->avail_oob_size,
1653ec4ba01eSPiotr Sroka DMA_FROM_DEVICE, true);
1654ec4ba01eSPiotr Sroka /* Otherwise use bounce buffer. */
1655ec4ba01eSPiotr Sroka } else {
1656ec4ba01eSPiotr Sroka cadence_nand_prepare_data_size(chip, TT_MAIN_OOB_AREAS);
1657ec4ba01eSPiotr Sroka status = cadence_nand_cdma_transfer(cdns_ctrl,
1658ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
1659ec4ba01eSPiotr Sroka page, cdns_ctrl->buf,
1660ec4ba01eSPiotr Sroka NULL, mtd->writesize
1661ec4ba01eSPiotr Sroka + cdns_chip->avail_oob_size,
1662ec4ba01eSPiotr Sroka 0, DMA_FROM_DEVICE, true);
1663ec4ba01eSPiotr Sroka
1664ec4ba01eSPiotr Sroka memcpy(buf, cdns_ctrl->buf, mtd->writesize);
1665ec4ba01eSPiotr Sroka if (oob_required)
1666ec4ba01eSPiotr Sroka memcpy(chip->oob_poi,
1667ec4ba01eSPiotr Sroka cdns_ctrl->buf + mtd->writesize,
1668ec4ba01eSPiotr Sroka mtd->oobsize);
1669ec4ba01eSPiotr Sroka }
1670ec4ba01eSPiotr Sroka
1671ec4ba01eSPiotr Sroka switch (status) {
1672ec4ba01eSPiotr Sroka case STAT_ECC_UNCORR:
1673ec4ba01eSPiotr Sroka mtd->ecc_stats.failed++;
1674ec4ba01eSPiotr Sroka ecc_err_count++;
1675ec4ba01eSPiotr Sroka break;
1676ec4ba01eSPiotr Sroka case STAT_ECC_CORR:
1677ec4ba01eSPiotr Sroka ecc_err_count = FIELD_GET(CDMA_CS_MAXERR,
1678ec4ba01eSPiotr Sroka cdns_ctrl->cdma_desc->status);
1679ec4ba01eSPiotr Sroka mtd->ecc_stats.corrected += ecc_err_count;
1680ec4ba01eSPiotr Sroka break;
1681ec4ba01eSPiotr Sroka case STAT_ERASED:
1682ec4ba01eSPiotr Sroka case STAT_OK:
1683ec4ba01eSPiotr Sroka break;
1684ec4ba01eSPiotr Sroka default:
1685ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "read page failed\n");
1686ec4ba01eSPiotr Sroka return -EIO;
1687ec4ba01eSPiotr Sroka }
1688ec4ba01eSPiotr Sroka
1689ec4ba01eSPiotr Sroka if (oob_required)
1690ec4ba01eSPiotr Sroka if (cadence_nand_read_bbm(chip, page, chip->oob_poi))
1691ec4ba01eSPiotr Sroka return -EIO;
1692ec4ba01eSPiotr Sroka
1693ec4ba01eSPiotr Sroka return ecc_err_count;
1694ec4ba01eSPiotr Sroka }
1695ec4ba01eSPiotr Sroka
1696ec4ba01eSPiotr Sroka /* Reads OOB data from the device. */
cadence_nand_read_oob(struct nand_chip * chip,int page)1697ec4ba01eSPiotr Sroka static int cadence_nand_read_oob(struct nand_chip *chip, int page)
1698ec4ba01eSPiotr Sroka {
1699ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1700ec4ba01eSPiotr Sroka
1701ec4ba01eSPiotr Sroka return cadence_nand_read_page(chip, cdns_ctrl->buf, 1, page);
1702ec4ba01eSPiotr Sroka }
1703ec4ba01eSPiotr Sroka
cadence_nand_read_page_raw(struct nand_chip * chip,u8 * buf,int oob_required,int page)1704ec4ba01eSPiotr Sroka static int cadence_nand_read_page_raw(struct nand_chip *chip,
1705ec4ba01eSPiotr Sroka u8 *buf, int oob_required, int page)
1706ec4ba01eSPiotr Sroka {
1707ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
1708ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
1709ec4ba01eSPiotr Sroka struct mtd_info *mtd = nand_to_mtd(chip);
1710ec4ba01eSPiotr Sroka int oob_skip = cdns_chip->bbm_len;
1711ec4ba01eSPiotr Sroka int writesize = mtd->writesize;
1712ec4ba01eSPiotr Sroka int ecc_steps = chip->ecc.steps;
1713ec4ba01eSPiotr Sroka int ecc_size = chip->ecc.size;
1714ec4ba01eSPiotr Sroka int ecc_bytes = chip->ecc.bytes;
1715ec4ba01eSPiotr Sroka void *tmp_buf = cdns_ctrl->buf;
1716ec4ba01eSPiotr Sroka int i, pos, len;
1717ec4ba01eSPiotr Sroka int status = 0;
1718ec4ba01eSPiotr Sroka
1719ec4ba01eSPiotr Sroka status = cadence_nand_select_target(chip);
1720ec4ba01eSPiotr Sroka if (status)
1721ec4ba01eSPiotr Sroka return status;
1722ec4ba01eSPiotr Sroka
1723ec4ba01eSPiotr Sroka cadence_nand_set_skip_bytes_conf(cdns_ctrl, 0, 0, 0);
1724ec4ba01eSPiotr Sroka
1725ec4ba01eSPiotr Sroka cadence_nand_prepare_data_size(chip, TT_RAW_PAGE);
1726ec4ba01eSPiotr Sroka status = cadence_nand_cdma_transfer(cdns_ctrl,
1727ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
1728ec4ba01eSPiotr Sroka page, cdns_ctrl->buf, NULL,
1729ec4ba01eSPiotr Sroka mtd->writesize
1730ec4ba01eSPiotr Sroka + mtd->oobsize,
1731ec4ba01eSPiotr Sroka 0, DMA_FROM_DEVICE, false);
1732ec4ba01eSPiotr Sroka
1733ec4ba01eSPiotr Sroka switch (status) {
1734ec4ba01eSPiotr Sroka case STAT_ERASED:
1735ec4ba01eSPiotr Sroka case STAT_OK:
1736ec4ba01eSPiotr Sroka break;
1737ec4ba01eSPiotr Sroka default:
1738ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "read raw page failed\n");
1739ec4ba01eSPiotr Sroka return -EIO;
1740ec4ba01eSPiotr Sroka }
1741ec4ba01eSPiotr Sroka
1742ec4ba01eSPiotr Sroka /* Arrange the buffer for syndrome payload/ecc layout. */
1743ec4ba01eSPiotr Sroka if (buf) {
1744ec4ba01eSPiotr Sroka for (i = 0; i < ecc_steps; i++) {
1745ec4ba01eSPiotr Sroka pos = i * (ecc_size + ecc_bytes);
1746ec4ba01eSPiotr Sroka len = ecc_size;
1747ec4ba01eSPiotr Sroka
1748ec4ba01eSPiotr Sroka if (pos >= writesize)
1749ec4ba01eSPiotr Sroka pos += oob_skip;
1750ec4ba01eSPiotr Sroka else if (pos + len > writesize)
1751ec4ba01eSPiotr Sroka len = writesize - pos;
1752ec4ba01eSPiotr Sroka
1753ec4ba01eSPiotr Sroka memcpy(buf, tmp_buf + pos, len);
1754ec4ba01eSPiotr Sroka buf += len;
1755ec4ba01eSPiotr Sroka if (len < ecc_size) {
1756ec4ba01eSPiotr Sroka len = ecc_size - len;
1757ec4ba01eSPiotr Sroka memcpy(buf, tmp_buf + writesize + oob_skip,
1758ec4ba01eSPiotr Sroka len);
1759ec4ba01eSPiotr Sroka buf += len;
1760ec4ba01eSPiotr Sroka }
1761ec4ba01eSPiotr Sroka }
1762ec4ba01eSPiotr Sroka }
1763ec4ba01eSPiotr Sroka
1764ec4ba01eSPiotr Sroka if (oob_required) {
1765ec4ba01eSPiotr Sroka u8 *oob = chip->oob_poi;
1766ec4ba01eSPiotr Sroka u32 oob_data_offset = (cdns_chip->sector_count - 1) *
1767ec4ba01eSPiotr Sroka (cdns_chip->sector_size + chip->ecc.bytes)
1768ec4ba01eSPiotr Sroka + cdns_chip->sector_size + oob_skip;
1769ec4ba01eSPiotr Sroka
1770ec4ba01eSPiotr Sroka /* OOB free. */
1771ec4ba01eSPiotr Sroka memcpy(oob, tmp_buf + oob_data_offset,
1772ec4ba01eSPiotr Sroka cdns_chip->avail_oob_size);
1773ec4ba01eSPiotr Sroka
1774ec4ba01eSPiotr Sroka /* BBM at the beginning of the OOB area. */
1775ec4ba01eSPiotr Sroka memcpy(oob, tmp_buf + writesize, oob_skip);
1776ec4ba01eSPiotr Sroka
1777ec4ba01eSPiotr Sroka oob += cdns_chip->avail_oob_size;
1778ec4ba01eSPiotr Sroka
1779ec4ba01eSPiotr Sroka /* OOB ECC */
1780ec4ba01eSPiotr Sroka for (i = 0; i < ecc_steps; i++) {
1781ec4ba01eSPiotr Sroka pos = ecc_size + i * (ecc_size + ecc_bytes);
1782ec4ba01eSPiotr Sroka len = ecc_bytes;
1783ec4ba01eSPiotr Sroka
1784ec4ba01eSPiotr Sroka if (i == (ecc_steps - 1))
1785ec4ba01eSPiotr Sroka pos += cdns_chip->avail_oob_size;
1786ec4ba01eSPiotr Sroka
1787ec4ba01eSPiotr Sroka if (pos >= writesize)
1788ec4ba01eSPiotr Sroka pos += oob_skip;
1789ec4ba01eSPiotr Sroka else if (pos + len > writesize)
1790ec4ba01eSPiotr Sroka len = writesize - pos;
1791ec4ba01eSPiotr Sroka
1792ec4ba01eSPiotr Sroka memcpy(oob, tmp_buf + pos, len);
1793ec4ba01eSPiotr Sroka oob += len;
1794ec4ba01eSPiotr Sroka if (len < ecc_bytes) {
1795ec4ba01eSPiotr Sroka len = ecc_bytes - len;
1796ec4ba01eSPiotr Sroka memcpy(oob, tmp_buf + writesize + oob_skip,
1797ec4ba01eSPiotr Sroka len);
1798ec4ba01eSPiotr Sroka oob += len;
1799ec4ba01eSPiotr Sroka }
1800ec4ba01eSPiotr Sroka }
1801ec4ba01eSPiotr Sroka }
1802ec4ba01eSPiotr Sroka
1803ec4ba01eSPiotr Sroka return 0;
1804ec4ba01eSPiotr Sroka }
1805ec4ba01eSPiotr Sroka
cadence_nand_read_oob_raw(struct nand_chip * chip,int page)1806ec4ba01eSPiotr Sroka static int cadence_nand_read_oob_raw(struct nand_chip *chip,
1807ec4ba01eSPiotr Sroka int page)
1808ec4ba01eSPiotr Sroka {
1809ec4ba01eSPiotr Sroka return cadence_nand_read_page_raw(chip, NULL, true, page);
1810ec4ba01eSPiotr Sroka }
1811ec4ba01eSPiotr Sroka
cadence_nand_slave_dma_transfer_finished(void * data)1812ec4ba01eSPiotr Sroka static void cadence_nand_slave_dma_transfer_finished(void *data)
1813ec4ba01eSPiotr Sroka {
1814ec4ba01eSPiotr Sroka struct completion *finished = data;
1815ec4ba01eSPiotr Sroka
1816ec4ba01eSPiotr Sroka complete(finished);
1817ec4ba01eSPiotr Sroka }
1818ec4ba01eSPiotr Sroka
cadence_nand_slave_dma_transfer(struct cdns_nand_ctrl * cdns_ctrl,void * buf,dma_addr_t dev_dma,size_t len,enum dma_data_direction dir)1819ec4ba01eSPiotr Sroka static int cadence_nand_slave_dma_transfer(struct cdns_nand_ctrl *cdns_ctrl,
1820ec4ba01eSPiotr Sroka void *buf,
1821ec4ba01eSPiotr Sroka dma_addr_t dev_dma, size_t len,
1822ec4ba01eSPiotr Sroka enum dma_data_direction dir)
1823ec4ba01eSPiotr Sroka {
1824ec4ba01eSPiotr Sroka DECLARE_COMPLETION_ONSTACK(finished);
1825ec4ba01eSPiotr Sroka struct dma_chan *chan;
1826ec4ba01eSPiotr Sroka struct dma_device *dma_dev;
1827ec4ba01eSPiotr Sroka dma_addr_t src_dma, dst_dma, buf_dma;
1828ec4ba01eSPiotr Sroka struct dma_async_tx_descriptor *tx;
1829ec4ba01eSPiotr Sroka dma_cookie_t cookie;
1830ec4ba01eSPiotr Sroka
1831ec4ba01eSPiotr Sroka chan = cdns_ctrl->dmac;
1832ec4ba01eSPiotr Sroka dma_dev = chan->device;
1833ec4ba01eSPiotr Sroka
1834ec4ba01eSPiotr Sroka buf_dma = dma_map_single(dma_dev->dev, buf, len, dir);
1835ec4ba01eSPiotr Sroka if (dma_mapping_error(dma_dev->dev, buf_dma)) {
1836ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n");
1837ec4ba01eSPiotr Sroka goto err;
1838ec4ba01eSPiotr Sroka }
1839ec4ba01eSPiotr Sroka
1840ec4ba01eSPiotr Sroka if (dir == DMA_FROM_DEVICE) {
1841ec4ba01eSPiotr Sroka src_dma = cdns_ctrl->io.dma;
1842ec4ba01eSPiotr Sroka dst_dma = buf_dma;
1843ec4ba01eSPiotr Sroka } else {
1844ec4ba01eSPiotr Sroka src_dma = buf_dma;
1845ec4ba01eSPiotr Sroka dst_dma = cdns_ctrl->io.dma;
1846ec4ba01eSPiotr Sroka }
1847ec4ba01eSPiotr Sroka
1848ec4ba01eSPiotr Sroka tx = dmaengine_prep_dma_memcpy(cdns_ctrl->dmac, dst_dma, src_dma, len,
1849ec4ba01eSPiotr Sroka DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1850ec4ba01eSPiotr Sroka if (!tx) {
1851ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Failed to prepare DMA memcpy\n");
1852ec4ba01eSPiotr Sroka goto err_unmap;
1853ec4ba01eSPiotr Sroka }
1854ec4ba01eSPiotr Sroka
1855ec4ba01eSPiotr Sroka tx->callback = cadence_nand_slave_dma_transfer_finished;
1856ec4ba01eSPiotr Sroka tx->callback_param = &finished;
1857ec4ba01eSPiotr Sroka
1858ec4ba01eSPiotr Sroka cookie = dmaengine_submit(tx);
1859ec4ba01eSPiotr Sroka if (dma_submit_error(cookie)) {
1860ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Failed to do DMA tx_submit\n");
1861ec4ba01eSPiotr Sroka goto err_unmap;
1862ec4ba01eSPiotr Sroka }
1863ec4ba01eSPiotr Sroka
1864ec4ba01eSPiotr Sroka dma_async_issue_pending(cdns_ctrl->dmac);
1865ec4ba01eSPiotr Sroka wait_for_completion(&finished);
1866ec4ba01eSPiotr Sroka
1867ec4ba01eSPiotr Sroka dma_unmap_single(cdns_ctrl->dev, buf_dma, len, dir);
1868ec4ba01eSPiotr Sroka
1869ec4ba01eSPiotr Sroka return 0;
1870ec4ba01eSPiotr Sroka
1871ec4ba01eSPiotr Sroka err_unmap:
1872ec4ba01eSPiotr Sroka dma_unmap_single(cdns_ctrl->dev, buf_dma, len, dir);
1873ec4ba01eSPiotr Sroka
1874ec4ba01eSPiotr Sroka err:
1875ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "Fall back to CPU I/O\n");
1876ec4ba01eSPiotr Sroka
1877ec4ba01eSPiotr Sroka return -EIO;
1878ec4ba01eSPiotr Sroka }
1879ec4ba01eSPiotr Sroka
cadence_nand_read_buf(struct cdns_nand_ctrl * cdns_ctrl,u8 * buf,int len)1880ec4ba01eSPiotr Sroka static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl,
1881ec4ba01eSPiotr Sroka u8 *buf, int len)
1882ec4ba01eSPiotr Sroka {
1883ec4ba01eSPiotr Sroka u8 thread_nr = 0;
1884ec4ba01eSPiotr Sroka u32 sdma_size;
1885ec4ba01eSPiotr Sroka int status;
1886ec4ba01eSPiotr Sroka
1887ec4ba01eSPiotr Sroka /* Wait until slave DMA interface is ready to data transfer. */
1888ec4ba01eSPiotr Sroka status = cadence_nand_wait_on_sdma(cdns_ctrl, &thread_nr, &sdma_size);
1889ec4ba01eSPiotr Sroka if (status)
1890ec4ba01eSPiotr Sroka return status;
1891ec4ba01eSPiotr Sroka
1892ec4ba01eSPiotr Sroka if (!cdns_ctrl->caps1->has_dma) {
18937c3fc998SValentin Korenblit u8 data_dma_width = cdns_ctrl->caps2.data_dma_width;
18947c3fc998SValentin Korenblit
18957c3fc998SValentin Korenblit int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3;
1896ec4ba01eSPiotr Sroka
1897ec4ba01eSPiotr Sroka /* read alingment data */
18987c3fc998SValentin Korenblit if (data_dma_width == 4)
1899ec4ba01eSPiotr Sroka ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words);
19007c3fc998SValentin Korenblit #ifdef CONFIG_64BIT
19017c3fc998SValentin Korenblit else
19027c3fc998SValentin Korenblit readsq(cdns_ctrl->io.virt, buf, len_in_words);
19037c3fc998SValentin Korenblit #endif
19047c3fc998SValentin Korenblit
1905ec4ba01eSPiotr Sroka if (sdma_size > len) {
19067c3fc998SValentin Korenblit int read_bytes = (data_dma_width == 4) ?
19077c3fc998SValentin Korenblit len_in_words << 2 : len_in_words << 3;
19087c3fc998SValentin Korenblit
1909ec4ba01eSPiotr Sroka /* read rest data from slave DMA interface if any */
19107c3fc998SValentin Korenblit if (data_dma_width == 4)
19117c3fc998SValentin Korenblit ioread32_rep(cdns_ctrl->io.virt,
19127c3fc998SValentin Korenblit cdns_ctrl->buf,
1913ec4ba01eSPiotr Sroka sdma_size / 4 - len_in_words);
19147c3fc998SValentin Korenblit #ifdef CONFIG_64BIT
19157c3fc998SValentin Korenblit else
19167c3fc998SValentin Korenblit readsq(cdns_ctrl->io.virt, cdns_ctrl->buf,
19177c3fc998SValentin Korenblit sdma_size / 8 - len_in_words);
19187c3fc998SValentin Korenblit #endif
19197c3fc998SValentin Korenblit
1920ec4ba01eSPiotr Sroka /* copy rest of data */
19217c3fc998SValentin Korenblit memcpy(buf + read_bytes, cdns_ctrl->buf,
19227c3fc998SValentin Korenblit len - read_bytes);
1923ec4ba01eSPiotr Sroka }
1924ec4ba01eSPiotr Sroka return 0;
1925ec4ba01eSPiotr Sroka }
1926ec4ba01eSPiotr Sroka
1927777260a5SPiotr Sroka if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, len)) {
1928ec4ba01eSPiotr Sroka status = cadence_nand_slave_dma_transfer(cdns_ctrl, buf,
1929ec4ba01eSPiotr Sroka cdns_ctrl->io.dma,
1930ec4ba01eSPiotr Sroka len, DMA_FROM_DEVICE);
1931ec4ba01eSPiotr Sroka if (status == 0)
1932ec4ba01eSPiotr Sroka return 0;
1933ec4ba01eSPiotr Sroka
1934ec4ba01eSPiotr Sroka dev_warn(cdns_ctrl->dev,
1935ec4ba01eSPiotr Sroka "Slave DMA transfer failed. Try again using bounce buffer.");
1936ec4ba01eSPiotr Sroka }
1937ec4ba01eSPiotr Sroka
1938ec4ba01eSPiotr Sroka /* If DMA transfer is not possible or failed then use bounce buffer. */
1939ec4ba01eSPiotr Sroka status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf,
1940ec4ba01eSPiotr Sroka cdns_ctrl->io.dma,
1941ec4ba01eSPiotr Sroka sdma_size, DMA_FROM_DEVICE);
1942ec4ba01eSPiotr Sroka
1943ec4ba01eSPiotr Sroka if (status) {
1944ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Slave DMA transfer failed");
1945ec4ba01eSPiotr Sroka return status;
1946ec4ba01eSPiotr Sroka }
1947ec4ba01eSPiotr Sroka
1948ec4ba01eSPiotr Sroka memcpy(buf, cdns_ctrl->buf, len);
1949ec4ba01eSPiotr Sroka
1950ec4ba01eSPiotr Sroka return 0;
1951ec4ba01eSPiotr Sroka }
1952ec4ba01eSPiotr Sroka
cadence_nand_write_buf(struct cdns_nand_ctrl * cdns_ctrl,const u8 * buf,int len)1953ec4ba01eSPiotr Sroka static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl,
1954ec4ba01eSPiotr Sroka const u8 *buf, int len)
1955ec4ba01eSPiotr Sroka {
1956ec4ba01eSPiotr Sroka u8 thread_nr = 0;
1957ec4ba01eSPiotr Sroka u32 sdma_size;
1958ec4ba01eSPiotr Sroka int status;
1959ec4ba01eSPiotr Sroka
1960ec4ba01eSPiotr Sroka /* Wait until slave DMA interface is ready to data transfer. */
1961ec4ba01eSPiotr Sroka status = cadence_nand_wait_on_sdma(cdns_ctrl, &thread_nr, &sdma_size);
1962ec4ba01eSPiotr Sroka if (status)
1963ec4ba01eSPiotr Sroka return status;
1964ec4ba01eSPiotr Sroka
1965ec4ba01eSPiotr Sroka if (!cdns_ctrl->caps1->has_dma) {
19667c3fc998SValentin Korenblit u8 data_dma_width = cdns_ctrl->caps2.data_dma_width;
1967ec4ba01eSPiotr Sroka
19687c3fc998SValentin Korenblit int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3;
19697c3fc998SValentin Korenblit
19707c3fc998SValentin Korenblit if (data_dma_width == 4)
1971ec4ba01eSPiotr Sroka iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words);
19727c3fc998SValentin Korenblit #ifdef CONFIG_64BIT
19737c3fc998SValentin Korenblit else
19747c3fc998SValentin Korenblit writesq(cdns_ctrl->io.virt, buf, len_in_words);
19757c3fc998SValentin Korenblit #endif
19767c3fc998SValentin Korenblit
1977ec4ba01eSPiotr Sroka if (sdma_size > len) {
19787c3fc998SValentin Korenblit int written_bytes = (data_dma_width == 4) ?
19797c3fc998SValentin Korenblit len_in_words << 2 : len_in_words << 3;
19807c3fc998SValentin Korenblit
1981ec4ba01eSPiotr Sroka /* copy rest of data */
19827c3fc998SValentin Korenblit memcpy(cdns_ctrl->buf, buf + written_bytes,
19837c3fc998SValentin Korenblit len - written_bytes);
19847c3fc998SValentin Korenblit
1985ec4ba01eSPiotr Sroka /* write all expected by nand controller data */
19867c3fc998SValentin Korenblit if (data_dma_width == 4)
19877c3fc998SValentin Korenblit iowrite32_rep(cdns_ctrl->io.virt,
19887c3fc998SValentin Korenblit cdns_ctrl->buf,
1989ec4ba01eSPiotr Sroka sdma_size / 4 - len_in_words);
19907c3fc998SValentin Korenblit #ifdef CONFIG_64BIT
19917c3fc998SValentin Korenblit else
19927c3fc998SValentin Korenblit writesq(cdns_ctrl->io.virt, cdns_ctrl->buf,
19937c3fc998SValentin Korenblit sdma_size / 8 - len_in_words);
19947c3fc998SValentin Korenblit #endif
1995ec4ba01eSPiotr Sroka }
1996ec4ba01eSPiotr Sroka
1997ec4ba01eSPiotr Sroka return 0;
1998ec4ba01eSPiotr Sroka }
1999ec4ba01eSPiotr Sroka
2000777260a5SPiotr Sroka if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, len)) {
2001ec4ba01eSPiotr Sroka status = cadence_nand_slave_dma_transfer(cdns_ctrl, (void *)buf,
2002ec4ba01eSPiotr Sroka cdns_ctrl->io.dma,
2003ec4ba01eSPiotr Sroka len, DMA_TO_DEVICE);
2004ec4ba01eSPiotr Sroka if (status == 0)
2005ec4ba01eSPiotr Sroka return 0;
2006ec4ba01eSPiotr Sroka
2007ec4ba01eSPiotr Sroka dev_warn(cdns_ctrl->dev,
2008ec4ba01eSPiotr Sroka "Slave DMA transfer failed. Try again using bounce buffer.");
2009ec4ba01eSPiotr Sroka }
2010ec4ba01eSPiotr Sroka
2011ec4ba01eSPiotr Sroka /* If DMA transfer is not possible or failed then use bounce buffer. */
2012ec4ba01eSPiotr Sroka memcpy(cdns_ctrl->buf, buf, len);
2013ec4ba01eSPiotr Sroka
2014ec4ba01eSPiotr Sroka status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf,
2015ec4ba01eSPiotr Sroka cdns_ctrl->io.dma,
2016ec4ba01eSPiotr Sroka sdma_size, DMA_TO_DEVICE);
2017ec4ba01eSPiotr Sroka
2018ec4ba01eSPiotr Sroka if (status)
2019ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Slave DMA transfer failed");
2020ec4ba01eSPiotr Sroka
2021ec4ba01eSPiotr Sroka return status;
2022ec4ba01eSPiotr Sroka }
2023ec4ba01eSPiotr Sroka
cadence_nand_force_byte_access(struct nand_chip * chip,bool force_8bit)2024ec4ba01eSPiotr Sroka static int cadence_nand_force_byte_access(struct nand_chip *chip,
2025ec4ba01eSPiotr Sroka bool force_8bit)
2026ec4ba01eSPiotr Sroka {
2027ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
2028ec4ba01eSPiotr Sroka
2029ec4ba01eSPiotr Sroka /*
2030ec4ba01eSPiotr Sroka * Callers of this function do not verify if the NAND is using a 16-bit
2031ec4ba01eSPiotr Sroka * an 8-bit bus for normal operations, so we need to take care of that
2032ec4ba01eSPiotr Sroka * here by leaving the configuration unchanged if the NAND does not have
2033ec4ba01eSPiotr Sroka * the NAND_BUSWIDTH_16 flag set.
2034ec4ba01eSPiotr Sroka */
2035ec4ba01eSPiotr Sroka if (!(chip->options & NAND_BUSWIDTH_16))
2036ec4ba01eSPiotr Sroka return 0;
2037ec4ba01eSPiotr Sroka
20384c5f69aeSye xingchen return cadence_nand_set_access_width16(cdns_ctrl, !force_8bit);
2039ec4ba01eSPiotr Sroka }
2040ec4ba01eSPiotr Sroka
cadence_nand_cmd_opcode(struct nand_chip * chip,const struct nand_subop * subop)2041ec4ba01eSPiotr Sroka static int cadence_nand_cmd_opcode(struct nand_chip *chip,
2042ec4ba01eSPiotr Sroka const struct nand_subop *subop)
2043ec4ba01eSPiotr Sroka {
2044ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
2045ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
2046ec4ba01eSPiotr Sroka const struct nand_op_instr *instr;
2047ec4ba01eSPiotr Sroka unsigned int op_id = 0;
2048ec4ba01eSPiotr Sroka u64 mini_ctrl_cmd = 0;
2049ec4ba01eSPiotr Sroka int ret;
2050ec4ba01eSPiotr Sroka
2051ec4ba01eSPiotr Sroka instr = &subop->instrs[op_id];
2052ec4ba01eSPiotr Sroka
2053ec4ba01eSPiotr Sroka if (instr->delay_ns > 0)
2054ec4ba01eSPiotr Sroka mini_ctrl_cmd |= GCMD_LAY_TWB;
2055ec4ba01eSPiotr Sroka
2056ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
2057ec4ba01eSPiotr Sroka GCMD_LAY_INSTR_CMD);
2058ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_CMD,
2059ec4ba01eSPiotr Sroka instr->ctx.cmd.opcode);
2060ec4ba01eSPiotr Sroka
2061ec4ba01eSPiotr Sroka ret = cadence_nand_generic_cmd_send(cdns_ctrl,
2062ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
2063ec4ba01eSPiotr Sroka mini_ctrl_cmd);
2064ec4ba01eSPiotr Sroka if (ret)
2065ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "send cmd %x failed\n",
2066ec4ba01eSPiotr Sroka instr->ctx.cmd.opcode);
2067ec4ba01eSPiotr Sroka
2068ec4ba01eSPiotr Sroka return ret;
2069ec4ba01eSPiotr Sroka }
2070ec4ba01eSPiotr Sroka
cadence_nand_cmd_address(struct nand_chip * chip,const struct nand_subop * subop)2071ec4ba01eSPiotr Sroka static int cadence_nand_cmd_address(struct nand_chip *chip,
2072ec4ba01eSPiotr Sroka const struct nand_subop *subop)
2073ec4ba01eSPiotr Sroka {
2074ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
2075ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
2076ec4ba01eSPiotr Sroka const struct nand_op_instr *instr;
2077ec4ba01eSPiotr Sroka unsigned int op_id = 0;
2078ec4ba01eSPiotr Sroka u64 mini_ctrl_cmd = 0;
2079ec4ba01eSPiotr Sroka unsigned int offset, naddrs;
2080ec4ba01eSPiotr Sroka u64 address = 0;
2081ec4ba01eSPiotr Sroka const u8 *addrs;
2082ec4ba01eSPiotr Sroka int ret;
2083ec4ba01eSPiotr Sroka int i;
2084ec4ba01eSPiotr Sroka
2085ec4ba01eSPiotr Sroka instr = &subop->instrs[op_id];
2086ec4ba01eSPiotr Sroka
2087ec4ba01eSPiotr Sroka if (instr->delay_ns > 0)
2088ec4ba01eSPiotr Sroka mini_ctrl_cmd |= GCMD_LAY_TWB;
2089ec4ba01eSPiotr Sroka
2090ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
2091ec4ba01eSPiotr Sroka GCMD_LAY_INSTR_ADDR);
2092ec4ba01eSPiotr Sroka
2093ec4ba01eSPiotr Sroka offset = nand_subop_get_addr_start_off(subop, op_id);
2094ec4ba01eSPiotr Sroka naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
2095ec4ba01eSPiotr Sroka addrs = &instr->ctx.addr.addrs[offset];
2096ec4ba01eSPiotr Sroka
2097ec4ba01eSPiotr Sroka for (i = 0; i < naddrs; i++)
2098ec4ba01eSPiotr Sroka address |= (u64)addrs[i] << (8 * i);
2099ec4ba01eSPiotr Sroka
2100ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR,
2101ec4ba01eSPiotr Sroka address);
2102ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR_SIZE,
2103ec4ba01eSPiotr Sroka naddrs - 1);
2104ec4ba01eSPiotr Sroka
2105ec4ba01eSPiotr Sroka ret = cadence_nand_generic_cmd_send(cdns_ctrl,
2106ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
2107ec4ba01eSPiotr Sroka mini_ctrl_cmd);
2108ec4ba01eSPiotr Sroka if (ret)
2109ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "send address %llx failed\n", address);
2110ec4ba01eSPiotr Sroka
2111ec4ba01eSPiotr Sroka return ret;
2112ec4ba01eSPiotr Sroka }
2113ec4ba01eSPiotr Sroka
cadence_nand_cmd_erase(struct nand_chip * chip,const struct nand_subop * subop)2114ec4ba01eSPiotr Sroka static int cadence_nand_cmd_erase(struct nand_chip *chip,
2115ec4ba01eSPiotr Sroka const struct nand_subop *subop)
2116ec4ba01eSPiotr Sroka {
2117ec4ba01eSPiotr Sroka unsigned int op_id;
2118ec4ba01eSPiotr Sroka
2119ec4ba01eSPiotr Sroka if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_ERASE1) {
2120ec4ba01eSPiotr Sroka int i;
2121ec4ba01eSPiotr Sroka const struct nand_op_instr *instr = NULL;
2122ec4ba01eSPiotr Sroka unsigned int offset, naddrs;
2123ec4ba01eSPiotr Sroka const u8 *addrs;
2124ec4ba01eSPiotr Sroka u32 page = 0;
2125ec4ba01eSPiotr Sroka
2126ec4ba01eSPiotr Sroka instr = &subop->instrs[1];
2127ec4ba01eSPiotr Sroka offset = nand_subop_get_addr_start_off(subop, 1);
2128ec4ba01eSPiotr Sroka naddrs = nand_subop_get_num_addr_cyc(subop, 1);
2129ec4ba01eSPiotr Sroka addrs = &instr->ctx.addr.addrs[offset];
2130ec4ba01eSPiotr Sroka
2131ec4ba01eSPiotr Sroka for (i = 0; i < naddrs; i++)
2132ec4ba01eSPiotr Sroka page |= (u32)addrs[i] << (8 * i);
2133ec4ba01eSPiotr Sroka
2134ec4ba01eSPiotr Sroka return cadence_nand_erase(chip, page);
2135ec4ba01eSPiotr Sroka }
2136ec4ba01eSPiotr Sroka
2137ec4ba01eSPiotr Sroka /*
2138ec4ba01eSPiotr Sroka * If it is not an erase operation then handle operation
2139ec4ba01eSPiotr Sroka * by calling exec_op function.
2140ec4ba01eSPiotr Sroka */
2141ec4ba01eSPiotr Sroka for (op_id = 0; op_id < subop->ninstrs; op_id++) {
2142ec4ba01eSPiotr Sroka int ret;
2143ec4ba01eSPiotr Sroka const struct nand_operation nand_op = {
2144ec4ba01eSPiotr Sroka .cs = chip->cur_cs,
2145ec4ba01eSPiotr Sroka .instrs = &subop->instrs[op_id],
2146ec4ba01eSPiotr Sroka .ninstrs = 1};
2147ec4ba01eSPiotr Sroka ret = chip->controller->ops->exec_op(chip, &nand_op, false);
2148ec4ba01eSPiotr Sroka if (ret)
2149ec4ba01eSPiotr Sroka return ret;
2150ec4ba01eSPiotr Sroka }
2151ec4ba01eSPiotr Sroka
2152ec4ba01eSPiotr Sroka return 0;
2153ec4ba01eSPiotr Sroka }
2154ec4ba01eSPiotr Sroka
cadence_nand_cmd_data(struct nand_chip * chip,const struct nand_subop * subop)2155ec4ba01eSPiotr Sroka static int cadence_nand_cmd_data(struct nand_chip *chip,
2156ec4ba01eSPiotr Sroka const struct nand_subop *subop)
2157ec4ba01eSPiotr Sroka {
2158ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
2159ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
2160ec4ba01eSPiotr Sroka const struct nand_op_instr *instr;
2161ec4ba01eSPiotr Sroka unsigned int offset, op_id = 0;
2162ec4ba01eSPiotr Sroka u64 mini_ctrl_cmd = 0;
2163ec4ba01eSPiotr Sroka int len = 0;
2164ec4ba01eSPiotr Sroka int ret;
2165ec4ba01eSPiotr Sroka
2166ec4ba01eSPiotr Sroka instr = &subop->instrs[op_id];
2167ec4ba01eSPiotr Sroka
2168ec4ba01eSPiotr Sroka if (instr->delay_ns > 0)
2169ec4ba01eSPiotr Sroka mini_ctrl_cmd |= GCMD_LAY_TWB;
2170ec4ba01eSPiotr Sroka
2171ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
2172ec4ba01eSPiotr Sroka GCMD_LAY_INSTR_DATA);
2173ec4ba01eSPiotr Sroka
2174ec4ba01eSPiotr Sroka if (instr->type == NAND_OP_DATA_OUT_INSTR)
2175ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_DIR,
2176ec4ba01eSPiotr Sroka GCMD_DIR_WRITE);
2177ec4ba01eSPiotr Sroka
2178ec4ba01eSPiotr Sroka len = nand_subop_get_data_len(subop, op_id);
2179ec4ba01eSPiotr Sroka offset = nand_subop_get_data_start_off(subop, op_id);
2180ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_SECT_CNT, 1);
2181ec4ba01eSPiotr Sroka mini_ctrl_cmd |= FIELD_PREP(GCMD_LAST_SIZE, len);
2182ec4ba01eSPiotr Sroka if (instr->ctx.data.force_8bit) {
2183ec4ba01eSPiotr Sroka ret = cadence_nand_force_byte_access(chip, true);
2184ec4ba01eSPiotr Sroka if (ret) {
2185ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
2186ec4ba01eSPiotr Sroka "cannot change byte access generic data cmd failed\n");
2187ec4ba01eSPiotr Sroka return ret;
2188ec4ba01eSPiotr Sroka }
2189ec4ba01eSPiotr Sroka }
2190ec4ba01eSPiotr Sroka
2191ec4ba01eSPiotr Sroka ret = cadence_nand_generic_cmd_send(cdns_ctrl,
2192ec4ba01eSPiotr Sroka cdns_chip->cs[chip->cur_cs],
2193ec4ba01eSPiotr Sroka mini_ctrl_cmd);
2194ec4ba01eSPiotr Sroka if (ret) {
2195ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "send generic data cmd failed\n");
2196ec4ba01eSPiotr Sroka return ret;
2197ec4ba01eSPiotr Sroka }
2198ec4ba01eSPiotr Sroka
2199ec4ba01eSPiotr Sroka if (instr->type == NAND_OP_DATA_IN_INSTR) {
2200ec4ba01eSPiotr Sroka void *buf = instr->ctx.data.buf.in + offset;
2201ec4ba01eSPiotr Sroka
2202ec4ba01eSPiotr Sroka ret = cadence_nand_read_buf(cdns_ctrl, buf, len);
2203ec4ba01eSPiotr Sroka } else {
2204ec4ba01eSPiotr Sroka const void *buf = instr->ctx.data.buf.out + offset;
2205ec4ba01eSPiotr Sroka
2206ec4ba01eSPiotr Sroka ret = cadence_nand_write_buf(cdns_ctrl, buf, len);
2207ec4ba01eSPiotr Sroka }
2208ec4ba01eSPiotr Sroka
2209ec4ba01eSPiotr Sroka if (ret) {
2210ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "data transfer failed for generic command\n");
2211ec4ba01eSPiotr Sroka return ret;
2212ec4ba01eSPiotr Sroka }
2213ec4ba01eSPiotr Sroka
2214ec4ba01eSPiotr Sroka if (instr->ctx.data.force_8bit) {
2215ec4ba01eSPiotr Sroka ret = cadence_nand_force_byte_access(chip, false);
2216ec4ba01eSPiotr Sroka if (ret) {
2217ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
2218ec4ba01eSPiotr Sroka "cannot change byte access generic data cmd failed\n");
2219ec4ba01eSPiotr Sroka }
2220ec4ba01eSPiotr Sroka }
2221ec4ba01eSPiotr Sroka
2222ec4ba01eSPiotr Sroka return ret;
2223ec4ba01eSPiotr Sroka }
2224ec4ba01eSPiotr Sroka
cadence_nand_cmd_waitrdy(struct nand_chip * chip,const struct nand_subop * subop)2225ec4ba01eSPiotr Sroka static int cadence_nand_cmd_waitrdy(struct nand_chip *chip,
2226ec4ba01eSPiotr Sroka const struct nand_subop *subop)
2227ec4ba01eSPiotr Sroka {
2228ec4ba01eSPiotr Sroka int status;
2229ec4ba01eSPiotr Sroka unsigned int op_id = 0;
2230ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
2231ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
2232ec4ba01eSPiotr Sroka const struct nand_op_instr *instr = &subop->instrs[op_id];
2233ec4ba01eSPiotr Sroka u32 timeout_us = instr->ctx.waitrdy.timeout_ms * 1000;
2234ec4ba01eSPiotr Sroka
2235ec4ba01eSPiotr Sroka status = cadence_nand_wait_for_value(cdns_ctrl, RBN_SETINGS,
2236ec4ba01eSPiotr Sroka timeout_us,
2237ec4ba01eSPiotr Sroka BIT(cdns_chip->cs[chip->cur_cs]),
2238ec4ba01eSPiotr Sroka false);
2239ec4ba01eSPiotr Sroka return status;
2240ec4ba01eSPiotr Sroka }
2241ec4ba01eSPiotr Sroka
2242ec4ba01eSPiotr Sroka static const struct nand_op_parser cadence_nand_op_parser = NAND_OP_PARSER(
2243ec4ba01eSPiotr Sroka NAND_OP_PARSER_PATTERN(
2244ec4ba01eSPiotr Sroka cadence_nand_cmd_erase,
2245ec4ba01eSPiotr Sroka NAND_OP_PARSER_PAT_CMD_ELEM(false),
2246ec4ba01eSPiotr Sroka NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ERASE_ADDRESS_CYC),
2247ec4ba01eSPiotr Sroka NAND_OP_PARSER_PAT_CMD_ELEM(false),
2248ec4ba01eSPiotr Sroka NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2249ec4ba01eSPiotr Sroka NAND_OP_PARSER_PATTERN(
2250ec4ba01eSPiotr Sroka cadence_nand_cmd_opcode,
2251ec4ba01eSPiotr Sroka NAND_OP_PARSER_PAT_CMD_ELEM(false)),
2252ec4ba01eSPiotr Sroka NAND_OP_PARSER_PATTERN(
2253ec4ba01eSPiotr Sroka cadence_nand_cmd_address,
2254ec4ba01eSPiotr Sroka NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC)),
2255ec4ba01eSPiotr Sroka NAND_OP_PARSER_PATTERN(
2256ec4ba01eSPiotr Sroka cadence_nand_cmd_data,
2257ec4ba01eSPiotr Sroka NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_DATA_SIZE)),
2258ec4ba01eSPiotr Sroka NAND_OP_PARSER_PATTERN(
2259ec4ba01eSPiotr Sroka cadence_nand_cmd_data,
2260ec4ba01eSPiotr Sroka NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE)),
2261ec4ba01eSPiotr Sroka NAND_OP_PARSER_PATTERN(
2262ec4ba01eSPiotr Sroka cadence_nand_cmd_waitrdy,
2263ec4ba01eSPiotr Sroka NAND_OP_PARSER_PAT_WAITRDY_ELEM(false))
2264ec4ba01eSPiotr Sroka );
2265ec4ba01eSPiotr Sroka
cadence_nand_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)2266ec4ba01eSPiotr Sroka static int cadence_nand_exec_op(struct nand_chip *chip,
2267ec4ba01eSPiotr Sroka const struct nand_operation *op,
2268ec4ba01eSPiotr Sroka bool check_only)
2269ec4ba01eSPiotr Sroka {
2270ce446b4bSBoris Brezillon if (!check_only) {
2271ec4ba01eSPiotr Sroka int status = cadence_nand_select_target(chip);
2272ec4ba01eSPiotr Sroka
2273ec4ba01eSPiotr Sroka if (status)
2274ec4ba01eSPiotr Sroka return status;
2275ce446b4bSBoris Brezillon }
2276ec4ba01eSPiotr Sroka
2277ec4ba01eSPiotr Sroka return nand_op_parser_exec_op(chip, &cadence_nand_op_parser, op,
2278ec4ba01eSPiotr Sroka check_only);
2279ec4ba01eSPiotr Sroka }
2280ec4ba01eSPiotr Sroka
cadence_nand_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)2281ec4ba01eSPiotr Sroka static int cadence_nand_ooblayout_free(struct mtd_info *mtd, int section,
2282ec4ba01eSPiotr Sroka struct mtd_oob_region *oobregion)
2283ec4ba01eSPiotr Sroka {
2284ec4ba01eSPiotr Sroka struct nand_chip *chip = mtd_to_nand(mtd);
2285ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
2286ec4ba01eSPiotr Sroka
2287ec4ba01eSPiotr Sroka if (section)
2288ec4ba01eSPiotr Sroka return -ERANGE;
2289ec4ba01eSPiotr Sroka
2290ec4ba01eSPiotr Sroka oobregion->offset = cdns_chip->bbm_len;
2291ec4ba01eSPiotr Sroka oobregion->length = cdns_chip->avail_oob_size
2292ec4ba01eSPiotr Sroka - cdns_chip->bbm_len;
2293ec4ba01eSPiotr Sroka
2294ec4ba01eSPiotr Sroka return 0;
2295ec4ba01eSPiotr Sroka }
2296ec4ba01eSPiotr Sroka
cadence_nand_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)2297ec4ba01eSPiotr Sroka static int cadence_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
2298ec4ba01eSPiotr Sroka struct mtd_oob_region *oobregion)
2299ec4ba01eSPiotr Sroka {
2300ec4ba01eSPiotr Sroka struct nand_chip *chip = mtd_to_nand(mtd);
2301ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
2302ec4ba01eSPiotr Sroka
2303ec4ba01eSPiotr Sroka if (section)
2304ec4ba01eSPiotr Sroka return -ERANGE;
2305ec4ba01eSPiotr Sroka
2306ec4ba01eSPiotr Sroka oobregion->offset = cdns_chip->avail_oob_size;
2307ec4ba01eSPiotr Sroka oobregion->length = chip->ecc.total;
2308ec4ba01eSPiotr Sroka
2309ec4ba01eSPiotr Sroka return 0;
2310ec4ba01eSPiotr Sroka }
2311ec4ba01eSPiotr Sroka
2312ec4ba01eSPiotr Sroka static const struct mtd_ooblayout_ops cadence_nand_ooblayout_ops = {
2313ec4ba01eSPiotr Sroka .free = cadence_nand_ooblayout_free,
2314ec4ba01eSPiotr Sroka .ecc = cadence_nand_ooblayout_ecc,
2315ec4ba01eSPiotr Sroka };
2316ec4ba01eSPiotr Sroka
calc_cycl(u32 timing,u32 clock)2317ec4ba01eSPiotr Sroka static int calc_cycl(u32 timing, u32 clock)
2318ec4ba01eSPiotr Sroka {
2319ec4ba01eSPiotr Sroka if (timing == 0 || clock == 0)
2320ec4ba01eSPiotr Sroka return 0;
2321ec4ba01eSPiotr Sroka
2322ec4ba01eSPiotr Sroka if ((timing % clock) > 0)
2323ec4ba01eSPiotr Sroka return timing / clock;
2324ec4ba01eSPiotr Sroka else
2325ec4ba01eSPiotr Sroka return timing / clock - 1;
2326ec4ba01eSPiotr Sroka }
2327ec4ba01eSPiotr Sroka
2328ec4ba01eSPiotr Sroka /* Calculate max data valid window. */
calc_tdvw_max(u32 trp_cnt,u32 clk_period,u32 trhoh_min,u32 board_delay_skew_min,u32 ext_mode)2329ec4ba01eSPiotr Sroka static inline u32 calc_tdvw_max(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
2330ec4ba01eSPiotr Sroka u32 board_delay_skew_min, u32 ext_mode)
2331ec4ba01eSPiotr Sroka {
2332ec4ba01eSPiotr Sroka if (ext_mode == 0)
2333ec4ba01eSPiotr Sroka clk_period /= 2;
2334ec4ba01eSPiotr Sroka
2335ec4ba01eSPiotr Sroka return (trp_cnt + 1) * clk_period + trhoh_min +
2336ec4ba01eSPiotr Sroka board_delay_skew_min;
2337ec4ba01eSPiotr Sroka }
2338ec4ba01eSPiotr Sroka
2339ec4ba01eSPiotr Sroka /* Calculate data valid window. */
calc_tdvw(u32 trp_cnt,u32 clk_period,u32 trhoh_min,u32 trea_max,u32 ext_mode)2340ec4ba01eSPiotr Sroka static inline u32 calc_tdvw(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
2341ec4ba01eSPiotr Sroka u32 trea_max, u32 ext_mode)
2342ec4ba01eSPiotr Sroka {
2343ec4ba01eSPiotr Sroka if (ext_mode == 0)
2344ec4ba01eSPiotr Sroka clk_period /= 2;
2345ec4ba01eSPiotr Sroka
2346ec4ba01eSPiotr Sroka return (trp_cnt + 1) * clk_period + trhoh_min - trea_max;
2347ec4ba01eSPiotr Sroka }
2348ec4ba01eSPiotr Sroka
2349ec4ba01eSPiotr Sroka static int
cadence_nand_setup_interface(struct nand_chip * chip,int chipnr,const struct nand_interface_config * conf)23504c46667bSMiquel Raynal cadence_nand_setup_interface(struct nand_chip *chip, int chipnr,
23514c46667bSMiquel Raynal const struct nand_interface_config *conf)
2352ec4ba01eSPiotr Sroka {
2353ec4ba01eSPiotr Sroka const struct nand_sdr_timings *sdr;
2354ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
2355ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
2356ec4ba01eSPiotr Sroka struct cadence_nand_timings *t = &cdns_chip->timings;
2357ec4ba01eSPiotr Sroka u32 reg;
2358ec4ba01eSPiotr Sroka u32 board_delay = cdns_ctrl->board_delay;
2359ec4ba01eSPiotr Sroka u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL,
2360ec4ba01eSPiotr Sroka cdns_ctrl->nf_clk_rate);
2361ec4ba01eSPiotr Sroka u32 tceh_cnt, tcs_cnt, tadl_cnt, tccs_cnt;
2362ec4ba01eSPiotr Sroka u32 tfeat_cnt, trhz_cnt, tvdly_cnt;
2363ec4ba01eSPiotr Sroka u32 trhw_cnt, twb_cnt, twh_cnt = 0, twhr_cnt;
2364ec4ba01eSPiotr Sroka u32 twp_cnt = 0, trp_cnt = 0, trh_cnt = 0;
2365ec4ba01eSPiotr Sroka u32 if_skew = cdns_ctrl->caps1->if_skew;
2366ec4ba01eSPiotr Sroka u32 board_delay_skew_min = board_delay - if_skew;
2367ec4ba01eSPiotr Sroka u32 board_delay_skew_max = board_delay + if_skew;
2368ec4ba01eSPiotr Sroka u32 dqs_sampl_res, phony_dqs_mod;
2369ec4ba01eSPiotr Sroka u32 tdvw, tdvw_min, tdvw_max;
2370ec4ba01eSPiotr Sroka u32 ext_rd_mode, ext_wr_mode;
2371ec4ba01eSPiotr Sroka u32 dll_phy_dqs_timing = 0, phony_dqs_timing = 0, rd_del_sel = 0;
2372ec4ba01eSPiotr Sroka u32 sampling_point;
2373ec4ba01eSPiotr Sroka
2374ec4ba01eSPiotr Sroka sdr = nand_get_sdr_timings(conf);
2375ec4ba01eSPiotr Sroka if (IS_ERR(sdr))
2376ec4ba01eSPiotr Sroka return PTR_ERR(sdr);
2377ec4ba01eSPiotr Sroka
2378ec4ba01eSPiotr Sroka memset(t, 0, sizeof(*t));
2379ec4ba01eSPiotr Sroka /* Sampling point calculation. */
2380ec4ba01eSPiotr Sroka
2381ec4ba01eSPiotr Sroka if (cdns_ctrl->caps2.is_phy_type_dll)
2382ec4ba01eSPiotr Sroka phony_dqs_mod = 2;
2383ec4ba01eSPiotr Sroka else
2384ec4ba01eSPiotr Sroka phony_dqs_mod = 1;
2385ec4ba01eSPiotr Sroka
2386ec4ba01eSPiotr Sroka dqs_sampl_res = clk_period / phony_dqs_mod;
2387ec4ba01eSPiotr Sroka
2388ec4ba01eSPiotr Sroka tdvw_min = sdr->tREA_max + board_delay_skew_max;
2389ec4ba01eSPiotr Sroka /*
2390ec4ba01eSPiotr Sroka * The idea of those calculation is to get the optimum value
2391ec4ba01eSPiotr Sroka * for tRP and tRH timings. If it is NOT possible to sample data
2392ec4ba01eSPiotr Sroka * with optimal tRP/tRH settings, the parameters will be extended.
2393ec4ba01eSPiotr Sroka * If clk_period is 50ns (the lowest value) this condition is met
2394dbb7b2e0SMiquel Raynal * for SDR timing modes 1, 2, 3, 4 and 5.
2395dbb7b2e0SMiquel Raynal * If clk_period is 20ns the condition is met only for SDR timing
2396dbb7b2e0SMiquel Raynal * mode 5.
2397ec4ba01eSPiotr Sroka */
2398ec4ba01eSPiotr Sroka if (sdr->tRC_min <= clk_period &&
2399ec4ba01eSPiotr Sroka sdr->tRP_min <= (clk_period / 2) &&
2400ec4ba01eSPiotr Sroka sdr->tREH_min <= (clk_period / 2)) {
2401ec4ba01eSPiotr Sroka /* Performance mode. */
2402ec4ba01eSPiotr Sroka ext_rd_mode = 0;
2403ec4ba01eSPiotr Sroka tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
2404ec4ba01eSPiotr Sroka sdr->tREA_max, ext_rd_mode);
2405ec4ba01eSPiotr Sroka tdvw_max = calc_tdvw_max(trp_cnt, clk_period, sdr->tRHOH_min,
2406ec4ba01eSPiotr Sroka board_delay_skew_min,
2407ec4ba01eSPiotr Sroka ext_rd_mode);
2408ec4ba01eSPiotr Sroka /*
2409ec4ba01eSPiotr Sroka * Check if data valid window and sampling point can be found
2410ec4ba01eSPiotr Sroka * and is not on the edge (ie. we have hold margin).
2411ec4ba01eSPiotr Sroka * If not extend the tRP timings.
2412ec4ba01eSPiotr Sroka */
2413ec4ba01eSPiotr Sroka if (tdvw > 0) {
2414ec4ba01eSPiotr Sroka if (tdvw_max <= tdvw_min ||
2415ec4ba01eSPiotr Sroka (tdvw_max % dqs_sampl_res) == 0) {
2416ec4ba01eSPiotr Sroka /*
2417ec4ba01eSPiotr Sroka * No valid sampling point so the RE pulse need
2418ec4ba01eSPiotr Sroka * to be widen widening by half clock cycle.
2419ec4ba01eSPiotr Sroka */
2420ec4ba01eSPiotr Sroka ext_rd_mode = 1;
2421ec4ba01eSPiotr Sroka }
2422ec4ba01eSPiotr Sroka } else {
2423ec4ba01eSPiotr Sroka /*
2424ec4ba01eSPiotr Sroka * There is no valid window
2425ec4ba01eSPiotr Sroka * to be able to sample data the tRP need to be widen.
2426ec4ba01eSPiotr Sroka * Very safe calculations are performed here.
2427ec4ba01eSPiotr Sroka */
2428ec4ba01eSPiotr Sroka trp_cnt = (sdr->tREA_max + board_delay_skew_max
2429ec4ba01eSPiotr Sroka + dqs_sampl_res) / clk_period;
2430ec4ba01eSPiotr Sroka ext_rd_mode = 1;
2431ec4ba01eSPiotr Sroka }
2432ec4ba01eSPiotr Sroka
2433ec4ba01eSPiotr Sroka } else {
2434ec4ba01eSPiotr Sroka /* Extended read mode. */
2435ec4ba01eSPiotr Sroka u32 trh;
2436ec4ba01eSPiotr Sroka
2437ec4ba01eSPiotr Sroka ext_rd_mode = 1;
2438ec4ba01eSPiotr Sroka trp_cnt = calc_cycl(sdr->tRP_min, clk_period);
2439ec4ba01eSPiotr Sroka trh = sdr->tRC_min - ((trp_cnt + 1) * clk_period);
2440ec4ba01eSPiotr Sroka if (sdr->tREH_min >= trh)
2441ec4ba01eSPiotr Sroka trh_cnt = calc_cycl(sdr->tREH_min, clk_period);
2442ec4ba01eSPiotr Sroka else
2443ec4ba01eSPiotr Sroka trh_cnt = calc_cycl(trh, clk_period);
2444ec4ba01eSPiotr Sroka
2445ec4ba01eSPiotr Sroka tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
2446ec4ba01eSPiotr Sroka sdr->tREA_max, ext_rd_mode);
2447ec4ba01eSPiotr Sroka /*
2448ec4ba01eSPiotr Sroka * Check if data valid window and sampling point can be found
2449ec4ba01eSPiotr Sroka * or if it is at the edge check if previous is valid
2450ec4ba01eSPiotr Sroka * - if not extend the tRP timings.
2451ec4ba01eSPiotr Sroka */
2452ec4ba01eSPiotr Sroka if (tdvw > 0) {
2453ec4ba01eSPiotr Sroka tdvw_max = calc_tdvw_max(trp_cnt, clk_period,
2454ec4ba01eSPiotr Sroka sdr->tRHOH_min,
2455ec4ba01eSPiotr Sroka board_delay_skew_min,
2456ec4ba01eSPiotr Sroka ext_rd_mode);
2457ec4ba01eSPiotr Sroka
2458ec4ba01eSPiotr Sroka if ((((tdvw_max / dqs_sampl_res)
2459ec4ba01eSPiotr Sroka * dqs_sampl_res) <= tdvw_min) ||
2460ec4ba01eSPiotr Sroka (((tdvw_max % dqs_sampl_res) == 0) &&
2461ec4ba01eSPiotr Sroka (((tdvw_max / dqs_sampl_res - 1)
2462ec4ba01eSPiotr Sroka * dqs_sampl_res) <= tdvw_min))) {
2463ec4ba01eSPiotr Sroka /*
2464ec4ba01eSPiotr Sroka * Data valid window width is lower than
2465ec4ba01eSPiotr Sroka * sampling resolution and do not hit any
2466ec4ba01eSPiotr Sroka * sampling point to be sure the sampling point
2467ec4ba01eSPiotr Sroka * will be found the RE low pulse width will be
2468ec4ba01eSPiotr Sroka * extended by one clock cycle.
2469ec4ba01eSPiotr Sroka */
2470ec4ba01eSPiotr Sroka trp_cnt = trp_cnt + 1;
2471ec4ba01eSPiotr Sroka }
2472ec4ba01eSPiotr Sroka } else {
2473ec4ba01eSPiotr Sroka /*
2474ec4ba01eSPiotr Sroka * There is no valid window to be able to sample data.
2475ec4ba01eSPiotr Sroka * The tRP need to be widen.
2476ec4ba01eSPiotr Sroka * Very safe calculations are performed here.
2477ec4ba01eSPiotr Sroka */
2478ec4ba01eSPiotr Sroka trp_cnt = (sdr->tREA_max + board_delay_skew_max
2479ec4ba01eSPiotr Sroka + dqs_sampl_res) / clk_period;
2480ec4ba01eSPiotr Sroka }
2481ec4ba01eSPiotr Sroka }
2482ec4ba01eSPiotr Sroka
2483ec4ba01eSPiotr Sroka tdvw_max = calc_tdvw_max(trp_cnt, clk_period,
2484ec4ba01eSPiotr Sroka sdr->tRHOH_min,
2485ec4ba01eSPiotr Sroka board_delay_skew_min, ext_rd_mode);
2486ec4ba01eSPiotr Sroka
2487ec4ba01eSPiotr Sroka if (sdr->tWC_min <= clk_period &&
2488ec4ba01eSPiotr Sroka (sdr->tWP_min + if_skew) <= (clk_period / 2) &&
2489ec4ba01eSPiotr Sroka (sdr->tWH_min + if_skew) <= (clk_period / 2)) {
2490ec4ba01eSPiotr Sroka ext_wr_mode = 0;
2491ec4ba01eSPiotr Sroka } else {
2492ec4ba01eSPiotr Sroka u32 twh;
2493ec4ba01eSPiotr Sroka
2494ec4ba01eSPiotr Sroka ext_wr_mode = 1;
2495ec4ba01eSPiotr Sroka twp_cnt = calc_cycl(sdr->tWP_min + if_skew, clk_period);
2496ec4ba01eSPiotr Sroka if ((twp_cnt + 1) * clk_period < (sdr->tALS_min + if_skew))
2497ec4ba01eSPiotr Sroka twp_cnt = calc_cycl(sdr->tALS_min + if_skew,
2498ec4ba01eSPiotr Sroka clk_period);
2499ec4ba01eSPiotr Sroka
2500ec4ba01eSPiotr Sroka twh = (sdr->tWC_min - (twp_cnt + 1) * clk_period);
2501ec4ba01eSPiotr Sroka if (sdr->tWH_min >= twh)
2502ec4ba01eSPiotr Sroka twh = sdr->tWH_min;
2503ec4ba01eSPiotr Sroka
2504ec4ba01eSPiotr Sroka twh_cnt = calc_cycl(twh + if_skew, clk_period);
2505ec4ba01eSPiotr Sroka }
2506ec4ba01eSPiotr Sroka
2507ec4ba01eSPiotr Sroka reg = FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRH, trh_cnt);
2508ec4ba01eSPiotr Sroka reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRP, trp_cnt);
2509ec4ba01eSPiotr Sroka reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWH, twh_cnt);
2510ec4ba01eSPiotr Sroka reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWP, twp_cnt);
2511ec4ba01eSPiotr Sroka t->async_toggle_timings = reg;
2512ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "ASYNC_TOGGLE_TIMINGS_SDR\t%x\n", reg);
2513ec4ba01eSPiotr Sroka
2514ec4ba01eSPiotr Sroka tadl_cnt = calc_cycl((sdr->tADL_min + if_skew), clk_period);
2515ec4ba01eSPiotr Sroka tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period);
2516ec4ba01eSPiotr Sroka twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period);
2517ec4ba01eSPiotr Sroka trhw_cnt = calc_cycl((sdr->tRHW_min + if_skew), clk_period);
2518ec4ba01eSPiotr Sroka reg = FIELD_PREP(TIMINGS0_TADL, tadl_cnt);
2519ec4ba01eSPiotr Sroka
2520ec4ba01eSPiotr Sroka /*
2521ec4ba01eSPiotr Sroka * If timing exceeds delay field in timing register
2522ec4ba01eSPiotr Sroka * then use maximum value.
2523ec4ba01eSPiotr Sroka */
2524ec4ba01eSPiotr Sroka if (FIELD_FIT(TIMINGS0_TCCS, tccs_cnt))
2525ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TIMINGS0_TCCS, tccs_cnt);
2526ec4ba01eSPiotr Sroka else
2527ec4ba01eSPiotr Sroka reg |= TIMINGS0_TCCS;
2528ec4ba01eSPiotr Sroka
2529ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TIMINGS0_TWHR, twhr_cnt);
2530ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TIMINGS0_TRHW, trhw_cnt);
2531ec4ba01eSPiotr Sroka t->timings0 = reg;
2532ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "TIMINGS0_SDR\t%x\n", reg);
2533ec4ba01eSPiotr Sroka
2534ec4ba01eSPiotr Sroka /* The following is related to single signal so skew is not needed. */
2535ec4ba01eSPiotr Sroka trhz_cnt = calc_cycl(sdr->tRHZ_max, clk_period);
2536ec4ba01eSPiotr Sroka trhz_cnt = trhz_cnt + 1;
2537ec4ba01eSPiotr Sroka twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period);
2538ec4ba01eSPiotr Sroka /*
2539ec4ba01eSPiotr Sroka * Because of the two stage syncflop the value must be increased by 3
2540ec4ba01eSPiotr Sroka * first value is related with sync, second value is related
2541ec4ba01eSPiotr Sroka * with output if delay.
2542ec4ba01eSPiotr Sroka */
2543ec4ba01eSPiotr Sroka twb_cnt = twb_cnt + 3 + 5;
2544ec4ba01eSPiotr Sroka /*
2545ec4ba01eSPiotr Sroka * The following is related to the we edge of the random data input
2546ec4ba01eSPiotr Sroka * sequence so skew is not needed.
2547ec4ba01eSPiotr Sroka */
2548ec4ba01eSPiotr Sroka tvdly_cnt = calc_cycl(500000 + if_skew, clk_period);
2549ec4ba01eSPiotr Sroka reg = FIELD_PREP(TIMINGS1_TRHZ, trhz_cnt);
2550ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TIMINGS1_TWB, twb_cnt);
2551ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TIMINGS1_TVDLY, tvdly_cnt);
2552ec4ba01eSPiotr Sroka t->timings1 = reg;
2553ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "TIMINGS1_SDR\t%x\n", reg);
2554ec4ba01eSPiotr Sroka
2555ec4ba01eSPiotr Sroka tfeat_cnt = calc_cycl(sdr->tFEAT_max, clk_period);
2556ec4ba01eSPiotr Sroka if (tfeat_cnt < twb_cnt)
2557ec4ba01eSPiotr Sroka tfeat_cnt = twb_cnt;
2558ec4ba01eSPiotr Sroka
2559ec4ba01eSPiotr Sroka tceh_cnt = calc_cycl(sdr->tCEH_min, clk_period);
2560ec4ba01eSPiotr Sroka tcs_cnt = calc_cycl((sdr->tCS_min + if_skew), clk_period);
2561ec4ba01eSPiotr Sroka
2562ec4ba01eSPiotr Sroka reg = FIELD_PREP(TIMINGS2_TFEAT, tfeat_cnt);
2563ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TIMINGS2_CS_HOLD_TIME, tceh_cnt);
2564ec4ba01eSPiotr Sroka reg |= FIELD_PREP(TIMINGS2_CS_SETUP_TIME, tcs_cnt);
2565ec4ba01eSPiotr Sroka t->timings2 = reg;
2566ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "TIMINGS2_SDR\t%x\n", reg);
2567ec4ba01eSPiotr Sroka
2568ec4ba01eSPiotr Sroka if (cdns_ctrl->caps2.is_phy_type_dll) {
2569ec4ba01eSPiotr Sroka reg = DLL_PHY_CTRL_DLL_RST_N;
2570ec4ba01eSPiotr Sroka if (ext_wr_mode)
2571ec4ba01eSPiotr Sroka reg |= DLL_PHY_CTRL_EXTENDED_WR_MODE;
2572ec4ba01eSPiotr Sroka if (ext_rd_mode)
2573ec4ba01eSPiotr Sroka reg |= DLL_PHY_CTRL_EXTENDED_RD_MODE;
2574ec4ba01eSPiotr Sroka
2575ec4ba01eSPiotr Sroka reg |= FIELD_PREP(DLL_PHY_CTRL_RS_HIGH_WAIT_CNT, 7);
2576ec4ba01eSPiotr Sroka reg |= FIELD_PREP(DLL_PHY_CTRL_RS_IDLE_CNT, 7);
2577ec4ba01eSPiotr Sroka t->dll_phy_ctrl = reg;
2578ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "DLL_PHY_CTRL_SDR\t%x\n", reg);
2579ec4ba01eSPiotr Sroka }
2580ec4ba01eSPiotr Sroka
2581ec4ba01eSPiotr Sroka /* Sampling point calculation. */
2582ec4ba01eSPiotr Sroka if ((tdvw_max % dqs_sampl_res) > 0)
2583ec4ba01eSPiotr Sroka sampling_point = tdvw_max / dqs_sampl_res;
2584ec4ba01eSPiotr Sroka else
2585ec4ba01eSPiotr Sroka sampling_point = (tdvw_max / dqs_sampl_res - 1);
2586ec4ba01eSPiotr Sroka
2587ec4ba01eSPiotr Sroka if (sampling_point * dqs_sampl_res > tdvw_min) {
2588ec4ba01eSPiotr Sroka dll_phy_dqs_timing =
2589ec4ba01eSPiotr Sroka FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_OE_END, 4);
2590ec4ba01eSPiotr Sroka dll_phy_dqs_timing |= PHY_DQS_TIMING_USE_PHONY_DQS;
2591ec4ba01eSPiotr Sroka phony_dqs_timing = sampling_point / phony_dqs_mod;
2592ec4ba01eSPiotr Sroka
2593ec4ba01eSPiotr Sroka if ((sampling_point % 2) > 0) {
2594ec4ba01eSPiotr Sroka dll_phy_dqs_timing |= PHY_DQS_TIMING_PHONY_DQS_SEL;
2595ec4ba01eSPiotr Sroka if ((tdvw_max % dqs_sampl_res) == 0)
2596ec4ba01eSPiotr Sroka /*
2597ec4ba01eSPiotr Sroka * Calculation for sampling point at the edge
2598ec4ba01eSPiotr Sroka * of data and being odd number.
2599ec4ba01eSPiotr Sroka */
2600ec4ba01eSPiotr Sroka phony_dqs_timing = (tdvw_max / dqs_sampl_res)
2601ec4ba01eSPiotr Sroka / phony_dqs_mod - 1;
2602ec4ba01eSPiotr Sroka
2603ec4ba01eSPiotr Sroka if (!cdns_ctrl->caps2.is_phy_type_dll)
2604ec4ba01eSPiotr Sroka phony_dqs_timing--;
2605ec4ba01eSPiotr Sroka
2606ec4ba01eSPiotr Sroka } else {
2607ec4ba01eSPiotr Sroka phony_dqs_timing--;
2608ec4ba01eSPiotr Sroka }
2609ec4ba01eSPiotr Sroka rd_del_sel = phony_dqs_timing + 3;
2610ec4ba01eSPiotr Sroka } else {
2611ec4ba01eSPiotr Sroka dev_warn(cdns_ctrl->dev,
2612ec4ba01eSPiotr Sroka "ERROR : cannot find valid sampling point\n");
2613ec4ba01eSPiotr Sroka }
2614ec4ba01eSPiotr Sroka
2615ec4ba01eSPiotr Sroka reg = FIELD_PREP(PHY_CTRL_PHONY_DQS, phony_dqs_timing);
2616ec4ba01eSPiotr Sroka if (cdns_ctrl->caps2.is_phy_type_dll)
2617ec4ba01eSPiotr Sroka reg |= PHY_CTRL_SDR_DQS;
2618ec4ba01eSPiotr Sroka t->phy_ctrl = reg;
2619ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "PHY_CTRL_REG_SDR\t%x\n", reg);
2620ec4ba01eSPiotr Sroka
2621ec4ba01eSPiotr Sroka if (cdns_ctrl->caps2.is_phy_type_dll) {
2622ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "PHY_TSEL_REG_SDR\t%x\n", 0);
2623ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "PHY_DQ_TIMING_REG_SDR\t%x\n", 2);
2624ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "PHY_DQS_TIMING_REG_SDR\t%x\n",
2625ec4ba01eSPiotr Sroka dll_phy_dqs_timing);
2626ec4ba01eSPiotr Sroka t->phy_dqs_timing = dll_phy_dqs_timing;
2627ec4ba01eSPiotr Sroka
2628ec4ba01eSPiotr Sroka reg = FIELD_PREP(PHY_GATE_LPBK_CTRL_RDS, rd_del_sel);
2629ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "PHY_GATE_LPBK_CTRL_REG_SDR\t%x\n",
2630ec4ba01eSPiotr Sroka reg);
2631ec4ba01eSPiotr Sroka t->phy_gate_lpbk_ctrl = reg;
2632ec4ba01eSPiotr Sroka
2633ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "PHY_DLL_MASTER_CTRL_REG_SDR\t%lx\n",
2634ec4ba01eSPiotr Sroka PHY_DLL_MASTER_CTRL_BYPASS_MODE);
2635ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev, "PHY_DLL_SLAVE_CTRL_REG_SDR\t%x\n", 0);
2636ec4ba01eSPiotr Sroka }
2637ec4ba01eSPiotr Sroka
2638ec4ba01eSPiotr Sroka return 0;
2639ec4ba01eSPiotr Sroka }
2640ec4ba01eSPiotr Sroka
cadence_nand_attach_chip(struct nand_chip * chip)2641fb0f6f33SYueHaibing static int cadence_nand_attach_chip(struct nand_chip *chip)
2642ec4ba01eSPiotr Sroka {
2643ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
2644ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
2645e4578af0SPiotr Sroka u32 ecc_size;
2646ec4ba01eSPiotr Sroka struct mtd_info *mtd = nand_to_mtd(chip);
2647ec4ba01eSPiotr Sroka int ret;
2648ec4ba01eSPiotr Sroka
2649ec4ba01eSPiotr Sroka if (chip->options & NAND_BUSWIDTH_16) {
2650ec4ba01eSPiotr Sroka ret = cadence_nand_set_access_width16(cdns_ctrl, true);
2651ec4ba01eSPiotr Sroka if (ret)
2652ec4ba01eSPiotr Sroka return ret;
2653ec4ba01eSPiotr Sroka }
2654ec4ba01eSPiotr Sroka
2655ec4ba01eSPiotr Sroka chip->bbt_options |= NAND_BBT_USE_FLASH;
2656ec4ba01eSPiotr Sroka chip->bbt_options |= NAND_BBT_NO_OOB;
2657bace41f8SMiquel Raynal chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2658ec4ba01eSPiotr Sroka
2659ec4ba01eSPiotr Sroka chip->options |= NAND_NO_SUBPAGE_WRITE;
2660ec4ba01eSPiotr Sroka
2661ec4ba01eSPiotr Sroka cdns_chip->bbm_offs = chip->badblockpos;
2662ec4ba01eSPiotr Sroka cdns_chip->bbm_offs &= ~0x01;
26639bf1903bSPiotr Sroka /* this value should be even number */
2664ec4ba01eSPiotr Sroka cdns_chip->bbm_len = 2;
2665ec4ba01eSPiotr Sroka
2666ec4ba01eSPiotr Sroka ret = nand_ecc_choose_conf(chip,
2667ec4ba01eSPiotr Sroka &cdns_ctrl->ecc_caps,
2668ec4ba01eSPiotr Sroka mtd->oobsize - cdns_chip->bbm_len);
2669ec4ba01eSPiotr Sroka if (ret) {
2670ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "ECC configuration failed\n");
2671ec4ba01eSPiotr Sroka return ret;
2672ec4ba01eSPiotr Sroka }
2673ec4ba01eSPiotr Sroka
2674ec4ba01eSPiotr Sroka dev_dbg(cdns_ctrl->dev,
2675ec4ba01eSPiotr Sroka "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
2676ec4ba01eSPiotr Sroka chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
2677ec4ba01eSPiotr Sroka
2678ec4ba01eSPiotr Sroka /* Error correction configuration. */
2679ec4ba01eSPiotr Sroka cdns_chip->sector_size = chip->ecc.size;
2680ec4ba01eSPiotr Sroka cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size;
2681e4578af0SPiotr Sroka ecc_size = cdns_chip->sector_count * chip->ecc.bytes;
2682ec4ba01eSPiotr Sroka
2683ec4ba01eSPiotr Sroka cdns_chip->avail_oob_size = mtd->oobsize - ecc_size;
2684ec4ba01eSPiotr Sroka
2685397deafcSPiotr Sroka if (cdns_chip->avail_oob_size > cdns_ctrl->bch_metadata_size)
2686397deafcSPiotr Sroka cdns_chip->avail_oob_size = cdns_ctrl->bch_metadata_size;
2687ec4ba01eSPiotr Sroka
2688ec4ba01eSPiotr Sroka if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size)
2689ec4ba01eSPiotr Sroka > mtd->oobsize)
2690ec4ba01eSPiotr Sroka cdns_chip->avail_oob_size -= 4;
2691ec4ba01eSPiotr Sroka
2692ec4ba01eSPiotr Sroka ret = cadence_nand_get_ecc_strength_idx(cdns_ctrl, chip->ecc.strength);
2693ec4ba01eSPiotr Sroka if (ret < 0)
2694ec4ba01eSPiotr Sroka return -EINVAL;
2695ec4ba01eSPiotr Sroka
2696ec4ba01eSPiotr Sroka cdns_chip->corr_str_idx = (u8)ret;
2697ec4ba01eSPiotr Sroka
2698ec4ba01eSPiotr Sroka if (cadence_nand_wait_for_value(cdns_ctrl, CTRL_STATUS,
2699ec4ba01eSPiotr Sroka 1000000,
2700ec4ba01eSPiotr Sroka CTRL_STATUS_CTRL_BUSY, true))
2701ec4ba01eSPiotr Sroka return -ETIMEDOUT;
2702ec4ba01eSPiotr Sroka
2703ec4ba01eSPiotr Sroka cadence_nand_set_ecc_strength(cdns_ctrl,
2704ec4ba01eSPiotr Sroka cdns_chip->corr_str_idx);
2705ec4ba01eSPiotr Sroka
2706ec4ba01eSPiotr Sroka cadence_nand_set_erase_detection(cdns_ctrl, true,
2707ec4ba01eSPiotr Sroka chip->ecc.strength);
2708ec4ba01eSPiotr Sroka
2709ec4ba01eSPiotr Sroka /* Override the default read operations. */
2710ec4ba01eSPiotr Sroka chip->ecc.read_page = cadence_nand_read_page;
2711ec4ba01eSPiotr Sroka chip->ecc.read_page_raw = cadence_nand_read_page_raw;
2712ec4ba01eSPiotr Sroka chip->ecc.write_page = cadence_nand_write_page;
2713ec4ba01eSPiotr Sroka chip->ecc.write_page_raw = cadence_nand_write_page_raw;
2714ec4ba01eSPiotr Sroka chip->ecc.read_oob = cadence_nand_read_oob;
2715ec4ba01eSPiotr Sroka chip->ecc.write_oob = cadence_nand_write_oob;
2716ec4ba01eSPiotr Sroka chip->ecc.read_oob_raw = cadence_nand_read_oob_raw;
2717ec4ba01eSPiotr Sroka chip->ecc.write_oob_raw = cadence_nand_write_oob_raw;
2718ec4ba01eSPiotr Sroka
2719ec4ba01eSPiotr Sroka if ((mtd->writesize + mtd->oobsize) > cdns_ctrl->buf_size)
2720ec4ba01eSPiotr Sroka cdns_ctrl->buf_size = mtd->writesize + mtd->oobsize;
2721ec4ba01eSPiotr Sroka
2722ec4ba01eSPiotr Sroka /* Is 32-bit DMA supported? */
2723ec4ba01eSPiotr Sroka ret = dma_set_mask(cdns_ctrl->dev, DMA_BIT_MASK(32));
2724ec4ba01eSPiotr Sroka if (ret) {
2725ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "no usable DMA configuration\n");
2726ec4ba01eSPiotr Sroka return ret;
2727ec4ba01eSPiotr Sroka }
2728ec4ba01eSPiotr Sroka
2729ec4ba01eSPiotr Sroka mtd_set_ooblayout(mtd, &cadence_nand_ooblayout_ops);
2730ec4ba01eSPiotr Sroka
2731ec4ba01eSPiotr Sroka return 0;
2732ec4ba01eSPiotr Sroka }
2733ec4ba01eSPiotr Sroka
2734ec4ba01eSPiotr Sroka static const struct nand_controller_ops cadence_nand_controller_ops = {
2735ec4ba01eSPiotr Sroka .attach_chip = cadence_nand_attach_chip,
2736ec4ba01eSPiotr Sroka .exec_op = cadence_nand_exec_op,
27374c46667bSMiquel Raynal .setup_interface = cadence_nand_setup_interface,
2738ec4ba01eSPiotr Sroka };
2739ec4ba01eSPiotr Sroka
cadence_nand_chip_init(struct cdns_nand_ctrl * cdns_ctrl,struct device_node * np)2740ec4ba01eSPiotr Sroka static int cadence_nand_chip_init(struct cdns_nand_ctrl *cdns_ctrl,
2741ec4ba01eSPiotr Sroka struct device_node *np)
2742ec4ba01eSPiotr Sroka {
2743ec4ba01eSPiotr Sroka struct cdns_nand_chip *cdns_chip;
2744ec4ba01eSPiotr Sroka struct mtd_info *mtd;
2745ec4ba01eSPiotr Sroka struct nand_chip *chip;
2746ec4ba01eSPiotr Sroka int nsels, ret, i;
2747ec4ba01eSPiotr Sroka u32 cs;
2748ec4ba01eSPiotr Sroka
2749ec4ba01eSPiotr Sroka nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
2750ec4ba01eSPiotr Sroka if (nsels <= 0) {
2751ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "missing/invalid reg property\n");
2752ec4ba01eSPiotr Sroka return -EINVAL;
2753ec4ba01eSPiotr Sroka }
2754ec4ba01eSPiotr Sroka
2755ec4ba01eSPiotr Sroka /* Allocate the nand chip structure. */
2756ec4ba01eSPiotr Sroka cdns_chip = devm_kzalloc(cdns_ctrl->dev, sizeof(*cdns_chip) +
2757ec4ba01eSPiotr Sroka (nsels * sizeof(u8)),
2758ec4ba01eSPiotr Sroka GFP_KERNEL);
2759ec4ba01eSPiotr Sroka if (!cdns_chip) {
2760ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "could not allocate chip structure\n");
2761ec4ba01eSPiotr Sroka return -ENOMEM;
2762ec4ba01eSPiotr Sroka }
2763ec4ba01eSPiotr Sroka
2764ec4ba01eSPiotr Sroka cdns_chip->nsels = nsels;
2765ec4ba01eSPiotr Sroka
2766ec4ba01eSPiotr Sroka for (i = 0; i < nsels; i++) {
2767ec4ba01eSPiotr Sroka /* Retrieve CS id. */
2768ec4ba01eSPiotr Sroka ret = of_property_read_u32_index(np, "reg", i, &cs);
2769ec4ba01eSPiotr Sroka if (ret) {
2770ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
2771ec4ba01eSPiotr Sroka "could not retrieve reg property: %d\n",
2772ec4ba01eSPiotr Sroka ret);
2773ec4ba01eSPiotr Sroka return ret;
2774ec4ba01eSPiotr Sroka }
2775ec4ba01eSPiotr Sroka
2776ec4ba01eSPiotr Sroka if (cs >= cdns_ctrl->caps2.max_banks) {
2777ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
2778ec4ba01eSPiotr Sroka "invalid reg value: %u (max CS = %d)\n",
2779ec4ba01eSPiotr Sroka cs, cdns_ctrl->caps2.max_banks);
2780ec4ba01eSPiotr Sroka return -EINVAL;
2781ec4ba01eSPiotr Sroka }
2782ec4ba01eSPiotr Sroka
2783ec4ba01eSPiotr Sroka if (test_and_set_bit(cs, &cdns_ctrl->assigned_cs)) {
2784ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
2785ec4ba01eSPiotr Sroka "CS %d already assigned\n", cs);
2786ec4ba01eSPiotr Sroka return -EINVAL;
2787ec4ba01eSPiotr Sroka }
2788ec4ba01eSPiotr Sroka
2789ec4ba01eSPiotr Sroka cdns_chip->cs[i] = cs;
2790ec4ba01eSPiotr Sroka }
2791ec4ba01eSPiotr Sroka
2792ec4ba01eSPiotr Sroka chip = &cdns_chip->chip;
2793ec4ba01eSPiotr Sroka chip->controller = &cdns_ctrl->controller;
2794ec4ba01eSPiotr Sroka nand_set_flash_node(chip, np);
2795ec4ba01eSPiotr Sroka
2796ec4ba01eSPiotr Sroka mtd = nand_to_mtd(chip);
2797ec4ba01eSPiotr Sroka mtd->dev.parent = cdns_ctrl->dev;
2798ec4ba01eSPiotr Sroka
2799ec4ba01eSPiotr Sroka /*
2800ec4ba01eSPiotr Sroka * Default to HW ECC engine mode. If the nand-ecc-mode property is given
2801ec4ba01eSPiotr Sroka * in the DT node, this entry will be overwritten in nand_scan_ident().
2802ec4ba01eSPiotr Sroka */
2803bace41f8SMiquel Raynal chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2804ec4ba01eSPiotr Sroka
2805ec4ba01eSPiotr Sroka ret = nand_scan(chip, cdns_chip->nsels);
2806ec4ba01eSPiotr Sroka if (ret) {
2807ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "could not scan the nand chip\n");
2808ec4ba01eSPiotr Sroka return ret;
2809ec4ba01eSPiotr Sroka }
2810ec4ba01eSPiotr Sroka
2811ec4ba01eSPiotr Sroka ret = mtd_device_register(mtd, NULL, 0);
2812ec4ba01eSPiotr Sroka if (ret) {
2813ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
2814ec4ba01eSPiotr Sroka "failed to register mtd device: %d\n", ret);
2815ec4ba01eSPiotr Sroka nand_cleanup(chip);
2816ec4ba01eSPiotr Sroka return ret;
2817ec4ba01eSPiotr Sroka }
2818ec4ba01eSPiotr Sroka
2819ec4ba01eSPiotr Sroka list_add_tail(&cdns_chip->node, &cdns_ctrl->chips);
2820ec4ba01eSPiotr Sroka
2821ec4ba01eSPiotr Sroka return 0;
2822ec4ba01eSPiotr Sroka }
2823ec4ba01eSPiotr Sroka
cadence_nand_chips_cleanup(struct cdns_nand_ctrl * cdns_ctrl)2824ec4ba01eSPiotr Sroka static void cadence_nand_chips_cleanup(struct cdns_nand_ctrl *cdns_ctrl)
2825ec4ba01eSPiotr Sroka {
2826ec4ba01eSPiotr Sroka struct cdns_nand_chip *entry, *temp;
28278b88f4e0SMiquel Raynal struct nand_chip *chip;
28288b88f4e0SMiquel Raynal int ret;
2829ec4ba01eSPiotr Sroka
2830ec4ba01eSPiotr Sroka list_for_each_entry_safe(entry, temp, &cdns_ctrl->chips, node) {
28318b88f4e0SMiquel Raynal chip = &entry->chip;
28328b88f4e0SMiquel Raynal ret = mtd_device_unregister(nand_to_mtd(chip));
28338b88f4e0SMiquel Raynal WARN_ON(ret);
28348b88f4e0SMiquel Raynal nand_cleanup(chip);
2835ec4ba01eSPiotr Sroka list_del(&entry->node);
2836ec4ba01eSPiotr Sroka }
2837ec4ba01eSPiotr Sroka }
2838ec4ba01eSPiotr Sroka
cadence_nand_chips_init(struct cdns_nand_ctrl * cdns_ctrl)2839ec4ba01eSPiotr Sroka static int cadence_nand_chips_init(struct cdns_nand_ctrl *cdns_ctrl)
2840ec4ba01eSPiotr Sroka {
2841ec4ba01eSPiotr Sroka struct device_node *np = cdns_ctrl->dev->of_node;
2842ec4ba01eSPiotr Sroka struct device_node *nand_np;
2843ec4ba01eSPiotr Sroka int max_cs = cdns_ctrl->caps2.max_banks;
2844ec4ba01eSPiotr Sroka int nchips, ret;
2845ec4ba01eSPiotr Sroka
2846ec4ba01eSPiotr Sroka nchips = of_get_child_count(np);
2847ec4ba01eSPiotr Sroka
2848ec4ba01eSPiotr Sroka if (nchips > max_cs) {
2849ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
2850ec4ba01eSPiotr Sroka "too many NAND chips: %d (max = %d CS)\n",
2851ec4ba01eSPiotr Sroka nchips, max_cs);
2852ec4ba01eSPiotr Sroka return -EINVAL;
2853ec4ba01eSPiotr Sroka }
2854ec4ba01eSPiotr Sroka
2855ec4ba01eSPiotr Sroka for_each_child_of_node(np, nand_np) {
2856ec4ba01eSPiotr Sroka ret = cadence_nand_chip_init(cdns_ctrl, nand_np);
2857ec4ba01eSPiotr Sroka if (ret) {
2858ec4ba01eSPiotr Sroka of_node_put(nand_np);
2859ec4ba01eSPiotr Sroka cadence_nand_chips_cleanup(cdns_ctrl);
2860ec4ba01eSPiotr Sroka return ret;
2861ec4ba01eSPiotr Sroka }
2862ec4ba01eSPiotr Sroka }
2863ec4ba01eSPiotr Sroka
2864ec4ba01eSPiotr Sroka return 0;
2865ec4ba01eSPiotr Sroka }
2866ec4ba01eSPiotr Sroka
2867ec4ba01eSPiotr Sroka static void
cadence_nand_irq_cleanup(int irqnum,struct cdns_nand_ctrl * cdns_ctrl)2868ec4ba01eSPiotr Sroka cadence_nand_irq_cleanup(int irqnum, struct cdns_nand_ctrl *cdns_ctrl)
2869ec4ba01eSPiotr Sroka {
2870ec4ba01eSPiotr Sroka /* Disable interrupts. */
2871ec4ba01eSPiotr Sroka writel_relaxed(INTR_ENABLE_INTR_EN, cdns_ctrl->reg + INTR_ENABLE);
2872ec4ba01eSPiotr Sroka }
2873ec4ba01eSPiotr Sroka
cadence_nand_init(struct cdns_nand_ctrl * cdns_ctrl)2874ec4ba01eSPiotr Sroka static int cadence_nand_init(struct cdns_nand_ctrl *cdns_ctrl)
2875ec4ba01eSPiotr Sroka {
2876ec4ba01eSPiotr Sroka dma_cap_mask_t mask;
2877ec4ba01eSPiotr Sroka int ret;
2878ec4ba01eSPiotr Sroka
2879ec4ba01eSPiotr Sroka cdns_ctrl->cdma_desc = dma_alloc_coherent(cdns_ctrl->dev,
2880ec4ba01eSPiotr Sroka sizeof(*cdns_ctrl->cdma_desc),
2881ec4ba01eSPiotr Sroka &cdns_ctrl->dma_cdma_desc,
2882ec4ba01eSPiotr Sroka GFP_KERNEL);
2883ec4ba01eSPiotr Sroka if (!cdns_ctrl->dma_cdma_desc)
2884ec4ba01eSPiotr Sroka return -ENOMEM;
2885ec4ba01eSPiotr Sroka
2886ec4ba01eSPiotr Sroka cdns_ctrl->buf_size = SZ_16K;
2887ec4ba01eSPiotr Sroka cdns_ctrl->buf = kmalloc(cdns_ctrl->buf_size, GFP_KERNEL);
2888ec4ba01eSPiotr Sroka if (!cdns_ctrl->buf) {
2889ec4ba01eSPiotr Sroka ret = -ENOMEM;
2890ec4ba01eSPiotr Sroka goto free_buf_desc;
2891ec4ba01eSPiotr Sroka }
2892ec4ba01eSPiotr Sroka
2893ec4ba01eSPiotr Sroka if (devm_request_irq(cdns_ctrl->dev, cdns_ctrl->irq, cadence_nand_isr,
2894ec4ba01eSPiotr Sroka IRQF_SHARED, "cadence-nand-controller",
2895ec4ba01eSPiotr Sroka cdns_ctrl)) {
2896ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Unable to allocate IRQ\n");
2897ec4ba01eSPiotr Sroka ret = -ENODEV;
2898ec4ba01eSPiotr Sroka goto free_buf;
2899ec4ba01eSPiotr Sroka }
2900ec4ba01eSPiotr Sroka
2901ec4ba01eSPiotr Sroka spin_lock_init(&cdns_ctrl->irq_lock);
2902ec4ba01eSPiotr Sroka init_completion(&cdns_ctrl->complete);
2903ec4ba01eSPiotr Sroka
2904ec4ba01eSPiotr Sroka ret = cadence_nand_hw_init(cdns_ctrl);
2905ec4ba01eSPiotr Sroka if (ret)
2906ec4ba01eSPiotr Sroka goto disable_irq;
2907ec4ba01eSPiotr Sroka
2908ec4ba01eSPiotr Sroka dma_cap_zero(mask);
2909ec4ba01eSPiotr Sroka dma_cap_set(DMA_MEMCPY, mask);
2910ec4ba01eSPiotr Sroka
2911ec4ba01eSPiotr Sroka if (cdns_ctrl->caps1->has_dma) {
2912ec4ba01eSPiotr Sroka cdns_ctrl->dmac = dma_request_channel(mask, NULL, NULL);
2913ec4ba01eSPiotr Sroka if (!cdns_ctrl->dmac) {
2914ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev,
2915ec4ba01eSPiotr Sroka "Unable to get a DMA channel\n");
2916ec4ba01eSPiotr Sroka ret = -EBUSY;
2917ec4ba01eSPiotr Sroka goto disable_irq;
2918ec4ba01eSPiotr Sroka }
2919ec4ba01eSPiotr Sroka }
2920ec4ba01eSPiotr Sroka
2921ec4ba01eSPiotr Sroka nand_controller_init(&cdns_ctrl->controller);
2922ec4ba01eSPiotr Sroka INIT_LIST_HEAD(&cdns_ctrl->chips);
2923ec4ba01eSPiotr Sroka
2924ec4ba01eSPiotr Sroka cdns_ctrl->controller.ops = &cadence_nand_controller_ops;
2925ec4ba01eSPiotr Sroka cdns_ctrl->curr_corr_str_idx = 0xFF;
2926ec4ba01eSPiotr Sroka
2927ec4ba01eSPiotr Sroka ret = cadence_nand_chips_init(cdns_ctrl);
2928ec4ba01eSPiotr Sroka if (ret) {
2929ec4ba01eSPiotr Sroka dev_err(cdns_ctrl->dev, "Failed to register MTD: %d\n",
2930ec4ba01eSPiotr Sroka ret);
2931ec4ba01eSPiotr Sroka goto dma_release_chnl;
2932ec4ba01eSPiotr Sroka }
2933ec4ba01eSPiotr Sroka
2934ec4ba01eSPiotr Sroka kfree(cdns_ctrl->buf);
2935ec4ba01eSPiotr Sroka cdns_ctrl->buf = kzalloc(cdns_ctrl->buf_size, GFP_KERNEL);
2936ec4ba01eSPiotr Sroka if (!cdns_ctrl->buf) {
2937ec4ba01eSPiotr Sroka ret = -ENOMEM;
2938ec4ba01eSPiotr Sroka goto dma_release_chnl;
2939ec4ba01eSPiotr Sroka }
2940ec4ba01eSPiotr Sroka
2941ec4ba01eSPiotr Sroka return 0;
2942ec4ba01eSPiotr Sroka
2943ec4ba01eSPiotr Sroka dma_release_chnl:
2944ec4ba01eSPiotr Sroka if (cdns_ctrl->dmac)
2945ec4ba01eSPiotr Sroka dma_release_channel(cdns_ctrl->dmac);
2946ec4ba01eSPiotr Sroka
2947ec4ba01eSPiotr Sroka disable_irq:
2948ec4ba01eSPiotr Sroka cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl);
2949ec4ba01eSPiotr Sroka
2950ec4ba01eSPiotr Sroka free_buf:
2951ec4ba01eSPiotr Sroka kfree(cdns_ctrl->buf);
2952ec4ba01eSPiotr Sroka
2953ec4ba01eSPiotr Sroka free_buf_desc:
2954ec4ba01eSPiotr Sroka dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc),
2955ec4ba01eSPiotr Sroka cdns_ctrl->cdma_desc, cdns_ctrl->dma_cdma_desc);
2956ec4ba01eSPiotr Sroka
2957ec4ba01eSPiotr Sroka return ret;
2958ec4ba01eSPiotr Sroka }
2959ec4ba01eSPiotr Sroka
2960ec4ba01eSPiotr Sroka /* Driver exit point. */
cadence_nand_remove(struct cdns_nand_ctrl * cdns_ctrl)2961ec4ba01eSPiotr Sroka static void cadence_nand_remove(struct cdns_nand_ctrl *cdns_ctrl)
2962ec4ba01eSPiotr Sroka {
2963ec4ba01eSPiotr Sroka cadence_nand_chips_cleanup(cdns_ctrl);
2964ec4ba01eSPiotr Sroka cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl);
2965ec4ba01eSPiotr Sroka kfree(cdns_ctrl->buf);
2966ec4ba01eSPiotr Sroka dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc),
2967ec4ba01eSPiotr Sroka cdns_ctrl->cdma_desc, cdns_ctrl->dma_cdma_desc);
2968ec4ba01eSPiotr Sroka
2969ec4ba01eSPiotr Sroka if (cdns_ctrl->dmac)
2970ec4ba01eSPiotr Sroka dma_release_channel(cdns_ctrl->dmac);
2971ec4ba01eSPiotr Sroka }
2972ec4ba01eSPiotr Sroka
2973ec4ba01eSPiotr Sroka struct cadence_nand_dt {
2974ec4ba01eSPiotr Sroka struct cdns_nand_ctrl cdns_ctrl;
2975ec4ba01eSPiotr Sroka struct clk *clk;
2976ec4ba01eSPiotr Sroka };
2977ec4ba01eSPiotr Sroka
2978ec4ba01eSPiotr Sroka static const struct cadence_nand_dt_devdata cadence_nand_default = {
2979ec4ba01eSPiotr Sroka .if_skew = 0,
2980ec4ba01eSPiotr Sroka .has_dma = 1,
2981ec4ba01eSPiotr Sroka };
2982ec4ba01eSPiotr Sroka
2983ec4ba01eSPiotr Sroka static const struct of_device_id cadence_nand_dt_ids[] = {
2984ec4ba01eSPiotr Sroka {
2985ec4ba01eSPiotr Sroka .compatible = "cdns,hp-nfc",
2986ec4ba01eSPiotr Sroka .data = &cadence_nand_default
2987ec4ba01eSPiotr Sroka }, {}
2988ec4ba01eSPiotr Sroka };
2989ec4ba01eSPiotr Sroka
2990ec4ba01eSPiotr Sroka MODULE_DEVICE_TABLE(of, cadence_nand_dt_ids);
2991ec4ba01eSPiotr Sroka
cadence_nand_dt_probe(struct platform_device * ofdev)2992ec4ba01eSPiotr Sroka static int cadence_nand_dt_probe(struct platform_device *ofdev)
2993ec4ba01eSPiotr Sroka {
2994ec4ba01eSPiotr Sroka struct resource *res;
2995ec4ba01eSPiotr Sroka struct cadence_nand_dt *dt;
2996ec4ba01eSPiotr Sroka struct cdns_nand_ctrl *cdns_ctrl;
2997ec4ba01eSPiotr Sroka int ret;
2998ec4ba01eSPiotr Sroka const struct of_device_id *of_id;
2999ec4ba01eSPiotr Sroka const struct cadence_nand_dt_devdata *devdata;
3000ec4ba01eSPiotr Sroka u32 val;
3001ec4ba01eSPiotr Sroka
3002ec4ba01eSPiotr Sroka of_id = of_match_device(cadence_nand_dt_ids, &ofdev->dev);
3003ec4ba01eSPiotr Sroka if (of_id) {
3004ec4ba01eSPiotr Sroka ofdev->id_entry = of_id->data;
3005ec4ba01eSPiotr Sroka devdata = of_id->data;
3006ec4ba01eSPiotr Sroka } else {
3007ec4ba01eSPiotr Sroka pr_err("Failed to find the right device id.\n");
3008ec4ba01eSPiotr Sroka return -ENOMEM;
3009ec4ba01eSPiotr Sroka }
3010ec4ba01eSPiotr Sroka
3011ec4ba01eSPiotr Sroka dt = devm_kzalloc(&ofdev->dev, sizeof(*dt), GFP_KERNEL);
3012ec4ba01eSPiotr Sroka if (!dt)
3013ec4ba01eSPiotr Sroka return -ENOMEM;
3014ec4ba01eSPiotr Sroka
3015ec4ba01eSPiotr Sroka cdns_ctrl = &dt->cdns_ctrl;
3016ec4ba01eSPiotr Sroka cdns_ctrl->caps1 = devdata;
3017ec4ba01eSPiotr Sroka
3018ec4ba01eSPiotr Sroka cdns_ctrl->dev = &ofdev->dev;
3019ec4ba01eSPiotr Sroka cdns_ctrl->irq = platform_get_irq(ofdev, 0);
302029d9640bSYueHaibing if (cdns_ctrl->irq < 0)
3021ec4ba01eSPiotr Sroka return cdns_ctrl->irq;
302229d9640bSYueHaibing
3023ec4ba01eSPiotr Sroka dev_info(cdns_ctrl->dev, "IRQ: nr %d\n", cdns_ctrl->irq);
3024ec4ba01eSPiotr Sroka
3025ec4ba01eSPiotr Sroka cdns_ctrl->reg = devm_platform_ioremap_resource(ofdev, 0);
3026fb1c7e82SLiu Shixin if (IS_ERR(cdns_ctrl->reg))
3027ec4ba01eSPiotr Sroka return PTR_ERR(cdns_ctrl->reg);
3028ec4ba01eSPiotr Sroka
3029a28ed09dSYang Yingliang cdns_ctrl->io.virt = devm_platform_get_and_ioremap_resource(ofdev, 1, &res);
3030fb1c7e82SLiu Shixin if (IS_ERR(cdns_ctrl->io.virt))
3031ec4ba01eSPiotr Sroka return PTR_ERR(cdns_ctrl->io.virt);
3032a28ed09dSYang Yingliang cdns_ctrl->io.dma = res->start;
3033ec4ba01eSPiotr Sroka
3034ec4ba01eSPiotr Sroka dt->clk = devm_clk_get(cdns_ctrl->dev, "nf_clk");
3035ec4ba01eSPiotr Sroka if (IS_ERR(dt->clk))
3036ec4ba01eSPiotr Sroka return PTR_ERR(dt->clk);
3037ec4ba01eSPiotr Sroka
3038ec4ba01eSPiotr Sroka cdns_ctrl->nf_clk_rate = clk_get_rate(dt->clk);
3039ec4ba01eSPiotr Sroka
3040ec4ba01eSPiotr Sroka ret = of_property_read_u32(ofdev->dev.of_node,
3041ec4ba01eSPiotr Sroka "cdns,board-delay-ps", &val);
3042ec4ba01eSPiotr Sroka if (ret) {
3043ec4ba01eSPiotr Sroka val = 4830;
3044ec4ba01eSPiotr Sroka dev_info(cdns_ctrl->dev,
3045ec4ba01eSPiotr Sroka "missing cdns,board-delay-ps property, %d was set\n",
3046ec4ba01eSPiotr Sroka val);
3047ec4ba01eSPiotr Sroka }
3048ec4ba01eSPiotr Sroka cdns_ctrl->board_delay = val;
3049ec4ba01eSPiotr Sroka
3050ec4ba01eSPiotr Sroka ret = cadence_nand_init(cdns_ctrl);
3051ec4ba01eSPiotr Sroka if (ret)
3052ec4ba01eSPiotr Sroka return ret;
3053ec4ba01eSPiotr Sroka
3054ec4ba01eSPiotr Sroka platform_set_drvdata(ofdev, dt);
3055ec4ba01eSPiotr Sroka return 0;
3056ec4ba01eSPiotr Sroka }
3057ec4ba01eSPiotr Sroka
cadence_nand_dt_remove(struct platform_device * ofdev)3058*ec185b18SUwe Kleine-König static void cadence_nand_dt_remove(struct platform_device *ofdev)
3059ec4ba01eSPiotr Sroka {
3060ec4ba01eSPiotr Sroka struct cadence_nand_dt *dt = platform_get_drvdata(ofdev);
3061ec4ba01eSPiotr Sroka
3062ec4ba01eSPiotr Sroka cadence_nand_remove(&dt->cdns_ctrl);
3063ec4ba01eSPiotr Sroka }
3064ec4ba01eSPiotr Sroka
3065ec4ba01eSPiotr Sroka static struct platform_driver cadence_nand_dt_driver = {
3066ec4ba01eSPiotr Sroka .probe = cadence_nand_dt_probe,
3067*ec185b18SUwe Kleine-König .remove_new = cadence_nand_dt_remove,
3068ec4ba01eSPiotr Sroka .driver = {
3069ec4ba01eSPiotr Sroka .name = "cadence-nand-controller",
3070ec4ba01eSPiotr Sroka .of_match_table = cadence_nand_dt_ids,
3071ec4ba01eSPiotr Sroka },
3072ec4ba01eSPiotr Sroka };
3073ec4ba01eSPiotr Sroka
3074ec4ba01eSPiotr Sroka module_platform_driver(cadence_nand_dt_driver);
3075ec4ba01eSPiotr Sroka
3076ec4ba01eSPiotr Sroka MODULE_AUTHOR("Piotr Sroka <piotrs@cadence.com>");
3077ec4ba01eSPiotr Sroka MODULE_LICENSE("GPL v2");
3078ec4ba01eSPiotr Sroka MODULE_DESCRIPTION("Driver for Cadence NAND flash controller");
3079ec4ba01eSPiotr Sroka
3080