Searched refs:PCIe (Results 1 – 25 of 126) sorted by relevance
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25 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space.27 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space.29 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space.31 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space.33 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space.35 0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space.39 0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space.41 0xFB000000 0xFBFFFFFF CP-1 / PCIe#1 Memory space.43 0xFC000000 0xFCFFFFFF CP-1 / PCIe#2 Memory space.45 0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space.[all …]
30 bool "Enable Aardvark PCIe driver"35 Say Y here if you want to enable PCIe controller support on36 Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on47 bool "Enable Aspeed PCIe driver"51 Say Y here if you want to enable PCIe controller support on60 PCIe host controllers, such as the one emulated by QEMU.63 bool "Enable Armada-8K PCIe driver (DesignWare core)"67 Say Y here if you want to enable PCIe controller support on68 Armada-8K SoCs. The PCIe controller on Armada-8K is based on72 bool "Renesas RCar Gen2 PCIe driver"[all …]
1 # Redfish PCIe Resources11 Redfish has resources that describe PCIe devices and functions available on a17 The Redfish PCIe resources are here:27 This feature is intended to meet the Redfish requirements for the PCIe resources34 model used in OpenBMC. The producer will provide the required PCIe values read36 the Redfish PCIe resources.42 gathering and caching PCIe hardware data and maintaining the D-Bus interfaces43 and properties. The actual hardware mechanism that is used to gather the PCIe49 the required data and send it to the PCIe daemon through IPMI, etc.51 When reading hardware directly, the PCIe daemon must be aware of power state[all …]
113 be MCTP, PCIe-DOE, or even TCP socket. For MCTP, the lower physical layer can be118 PCIe-DOE, or TCP setting up the transport layer connection could be easy. In119 this design, we only consider SPDM over standard MCTP,TCP & PCIe-DOE connection.135 For SPDM-over-PCIe-DOE, SPDM daemon need the PCIe device BDF to handle DOE136 mailbox discovery. Given that not all PCIe devices support DOE support SPDM, we138 need a way to pass the device info to the dameon. However, PCIe device141 needs should be the PCIe device ID, which is identified by `VendorId:DeviceId`.142 For the convenience of configuration, we should pass PCIe device ID to the143 daemon, so that the daemon can enumerate all the PCIe devices and find the144 matching devices by their device ID. There are different ways to pass PCIe[all …]
29 bool "Apalis Evaluation Board PCIe Initialisation"31 Bring up the Apalis PCIe port with the PCIe switch as found on the32 Apalis Evaluation board. Note that by default the PCIe port is also
29 bool "Apalis Evaluation Board PCIe Initialisation"31 Bring up the Apalis type specific 4 lane PCIe port as well as the32 Apalis PCIe port with the PCIe switch as found on the Apalis
16 PCIe, enumerator33 PCIe, enumerator64 {CableClass::PCIe, "PCIe"},81 {ConnectorType::PCIe, "PCIe"},
45 PCIe, enumerator84 {FunctionProtocol::PCIe, "PCIe"},
12 PCIe, enumerator59 {Protocol::PCIe, "PCIe"},
1 SUMMARY = "PECI PCIe"2 DESCRIPTION = "Gathers PCIe information using PECI \17 SYSTEMD_SERVICE:${PN} += "xyz.openbmc_project.PCIe.service"
78 PCIe host bridge84 PCIe Expander Bridge (``-device pxb-pcie``)86 PCIe Root Port (``-device pcie-root-port``)90 PCIe-to-PCI bridge (``-device pcie-pci-bridge``)94 PCIe NVMe device (``-device nvme``)
102 Sys can get the total number of PCIe slots from BMC using this command. When BMC103 receives this command, BMC can enumerate over all the PCIe slots and create a104 hashmap with all the available PCIe slot name - I2C bus number mappings. BMC can105 then send the total number of PCIe slots as part of this command response.118 | 0x01 | Total number of PCIe slots | Total number of PCIe slots |124 command with Entry ID as 1, BMC can go and fetch the first PCIe slot name - I2C125 bus number mapping from the hashmap created above and then send the PCIe slot140 | 0x01 | I2C bus number | The I2C bus number which is input to the above PCIe slot |141 | 0x02 | PCIe slo[all...]
1 Armada-8K PCIe DT details:4 Armada-8k uses synopsis designware PCIe controller.12 define the mapping of the PCIe interface to interrupt numbers.
17 PCIe and some other sensor interfaces.25 serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,34 peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.43 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.61 standard I/O interfaces, including a full-sized mini-PCIe slot,
21 Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,32 switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
2 It can work in two mode: standalone mode and PCIe endpoint mode.23 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)54 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)55 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)64 - PCIe65 - One PCIe x4 gold-finger66 - One PCIe x4 connector67 - One PCIe x2 end-point device (C293 Crypto co-processor)
16 SDRAM. It has a Panther Point platform controller hub, PCIe38 Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also48 LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
16 Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2,29 Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2,
2 Description=Start up the Nvidia GPU PCIe card platform
2 Description=POWER9 PCIe Power-off Workaround
21 Currently only PCIe devices are allowed as primary devices, this restriction24 and standby devices are not plugged into the same PCIe slot.34 device via the PCIe based hotplug handler and traffic will go through
17 - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and18 standard PCIe card
16 4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot,
31 string "PCIe compatible of Kernel DT"93 bool "Workaround for PCIe erratum A010315"