Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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66c433ed |
| 31-Mar-2019 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
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8303467e |
| 15-Mar-2019 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
- DPAA2 fixes and DDR errata workaround for LS1021A
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15809705 |
| 06-Mar-2019 |
Alison Wang <alison.wang@nxp.com> |
armv7: ls102xa: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workarou
armv7: ls102xa: Add workaround for DDR erratum A-008850
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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58008cba |
| 23-Jul-2018 |
Michal Simek <michal.simek@xilinx.com> |
Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@kon
Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
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Revision tags: v2018.07, v2018.03, v2018.01 |
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9fd95ef0 |
| 08-Dec-2017 |
Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> |
ata: Migrate CONFIG_SCSI_AHCI to Kconfig
And use 'imply' liberally.
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
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Revision tags: v2017.11 |
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8a33cb8b |
| 12-Sep-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
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0e8a4264 |
| 04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv7: Add workaround for USB erratum A-009007
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values
Program register USB_PHY_RX_OVRD_IN_HI in certain
armv7: Add workaround for USB erratum A-009007
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values
Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
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e10d1142 |
| 04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv7: Add workaround for USB erratum A-008997
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings
Change confi
armv7: Add workaround for USB erratum A-008997
Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings
Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
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c1853f6f |
| 04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv7: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test fai
armv7: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
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83fa7118 |
| 04-Sep-2017 |
Ran Wang <ran.wang_1@nxp.com> |
armv7: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Op
armv7: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
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63b2316c |
| 11-Aug-2017 |
Ashish Kumar <Ashish.Kumar@nxp.com> |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O cohere
fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters.
This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
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6500ec7a |
| 04-Aug-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_CMD_PCI to Kconfig
This converts the following to Kconfig: CONFIG_CMD_PCI
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Phi
Convert CONFIG_CMD_PCI to Kconfig
This converts the following to Kconfig: CONFIG_CMD_PCI
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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8d3a2568 |
| 11-Jul-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
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fedb428c |
| 14-Jun-2017 |
Simon Glass <sjg@chromium.org> |
Convert CONFIG_SCSI to Kconfig
This converts the following to Kconfig: CONFIG_SCSI
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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0675f992 |
| 19-Jan-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
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19538f30 |
| 13-Dec-2016 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
kconfig: move FSL_PCIE_COMPAT to platform Kconfig
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
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66e399b6 |
| 28-Dec-2016 |
York Sun <york.sun@nxp.com> |
ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in confi
ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files.
Signed-off-by: York Sun <york.sun@nxp.com>
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ba1b6fb5 |
| 28-Dec-2016 |
York Sun <york.sun@nxp.com> |
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig
Use Kconfig to select errata workaround.
Signed-off-by: York Sun <york.sun@nxp.com>
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d26e34c4 |
| 28-Dec-2016 |
York Sun <york.sun@nxp.com> |
fsl_ddr: Move DDR config options to driver Kconfig
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8
fsl_ddr: Move DDR config options to driver Kconfig
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
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90b80386 |
| 28-Dec-2016 |
York Sun <york.sun@nxp.com> |
crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig
Use Kconfig option to set little- or big-endian access to secure boot and trust architecture.
Signed-off-by: York Sun <york.sun@nxp.com>
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2c2e2c9e |
| 28-Dec-2016 |
York Sun <york.sun@nxp.com> |
crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Su
crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun <york.sun@nxp.com>
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194eded1 |
| 04-Dec-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-mpc85xx
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72ccd31e |
| 02-Dec-2016 |
York Sun <york.sun@nxp.com> |
armv7: ls1021a: Move SECURE_BOOT option to Kconfig
Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option.
Signed-off-by: York Sun <york.sun@nxp.com>
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711b5341 |
| 12-Oct-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts: include/configs/ls1021aqds.h include/configs/ls1021atwr.h
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53d76829 |
| 04-Oct-2016 |
York Sun <york.sun@nxp.com> |
armv7: ls1021a: Move DDR config options to Kconfig
Move DDR3, DDR4 and related config options to Kconfig and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Gl
armv7: ls1021a: Move DDR config options to Kconfig
Move DDR3, DDR4 and related config options to Kconfig and clean up existing uses.
Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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