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Searched refs:ODT (Results 1 – 25 of 35) sorted by relevance

12

/openbmc/u-boot/drivers/ram/aspeed/
H A DKconfig47 prompt "DDR4 PHY side ODT"
51 bool "DDR4 PHY side ODT 80 ohm"
54 select DDR4 PHY side ODT 80 ohm
57 bool "DDR4 PHY side ODT 60 ohm"
60 select DDR4 PHY side ODT 60 ohm
63 bool "DDR4 PHY side ODT 48 ohm"
69 bool "DDR4 PHY side ODT 40 ohm"
76 prompt "DDR4 DRAM side ODT"
80 bool "DDR4 DRAM side ODT 80 ohm"
86 bool "DDR4 DRAM side ODT 60 ohm"
[all …]
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg136 # DDR2 ODT Read Timing (default values)
145 # DDR2 ODT Write Timing (default values)
177 # DDR ODT Control (Low)
186 # DDR ODT Control (High)
192 # CPU ODT Control
197 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
198 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
199 # bit14: 1, M_STARTBURST_IN ODT enabled
200 # bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
201 # bit20-16: 0, Pad N channel driving strength for ODT
[all …]
H A Dkwbimage-lsxhl.cfg136 # DDR2 ODT Read Timing (default values)
145 # DDR2 ODT Write Timing (default values)
177 # DDR ODT Control (Low)
186 # DDR ODT Control (High)
192 # CPU ODT Control
197 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
198 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
199 # bit14: 1, M_STARTBURST_IN ODT enabled
200 # bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
201 # bit20-16: 0, Pad N channel driving strength for ODT
[all …]
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg126 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
134 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
160 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
168 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
173 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
177 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
178 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
179 # bit14: 1, M_STARTBURST_IN ODT enabled
180 # bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
181 # bit20-16: 0, Pad N channel driving strength for ODT
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
85 ODT = ram->next->bios.timing_10_ODT; in nvkm_sddr3_calc()
92 ODT = (ram->mr[1] & 0x004) >> 2 | in nvkm_sddr3_calc()
112 ram->mr[1] |= (ODT & 0x1) << 2; in nvkm_sddr3_calc()
113 ram->mr[1] |= (ODT & 0x2) << 5; in nvkm_sddr3_calc()
114 ram->mr[1] |= (ODT & 0x4) << 7; in nvkm_sddr3_calc()
H A Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
70 ODT = ram->next->bios.timing_10_ODT & 3; in nvkm_sddr2_calc()
82 ODT = (ram->mr[1] & 0x004) >> 2 | in nvkm_sddr2_calc()
96 ram->mr[1] |= (ODT & 0x1) << 2; in nvkm_sddr2_calc()
97 ram->mr[1] |= (ODT & 0x2) << 5; in nvkm_sddr2_calc()
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
81 ODT = ram->next->bios.timing_10_ODT; in nvkm_gddr3_calc()
98 ODT = (ram->mr[1] & 0xc) >> 2; in nvkm_gddr3_calc()
113 ram->mr[1] |= (ODT & 0x03) << 2; in nvkm_gddr3_calc()
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage-memphis.cfg110 # bit2: 1, DDR ODT control lsd disabled
112 # bit6: 0, DDR ODT control msb disabled
135 # bit15-12: 0100, internal ODT assertion 4 cycles after read
142 # bit11-8 : 0100, internal ODT assertion x cycles after write
157 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
161 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
166 DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
170 # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
171 # bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
172 # bit14 :1, STARTBURST ODT enabled
[all …]
H A Dkwbimage_256M8_1.cfg173 # bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
198 # (ODT turn off delay 2,5 clk cycles)
199 # bit 15-12: 4, internal ODT time based on bit 7-4
201 # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
228 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
238 DATA 0xFFD01498 0x00000004 # DDR ODT Control (High)
243 DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
247 # bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
248 # bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
249 # bit 14: 1, STARTBURST ODT enabled
[all …]
H A Dkwbimage_128M16_1.cfg175 # bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1]
198 # (ODT turn off delay 2,5 clk cycles)
199 # bit 15-12: 4, internal ODT time based on bit 7-4
201 # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
228 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
238 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
243 DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
247 # bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
248 # bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
249 # bit 14: 1, STARTBURST ODT enabled
[all …]
H A Dkwbimage.cfg107 # bit2: 1, DDR ODT control lsd disabled
109 # bit6: 1, DDR ODT control msb, enabled
142 DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
146 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
147 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
151 DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
152 # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
153 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
155 # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
/openbmc/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
133 DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
138 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
140 DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
142 # bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
143 # bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
144 # bit14: 1, M_STARTBURST_IN ODT: Enabled
[all …]
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage-ns2l.cfg95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
131 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
[all …]
H A Dkwbimage.cfg95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
131 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
[all …]
H A Dkwbimage-is2.cfg95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
131 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
[all …]
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
116 DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
131 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
[all …]
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg96 # bit2: 0, DDR ODT control lsd (disabled)
98 # bit6: 1, DDR ODT control msb, (disabled)
117 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
118 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
134 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
136 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
140 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
133 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
134 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
135 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
139 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg98 # bit2: 0, DDR ODT control lsd (disabled)
100 # bit6: 1, DDR ODT control msb, (disabled)
119 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
120 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
136 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
137 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
138 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
142 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
133 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
134 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
135 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
139 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg101 # bit2: 0, DDR ODT control lsd (disabled)
103 # bit6: 1, DDR ODT control msb, (disabled)
122 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
123 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
139 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
140 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
141 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
145 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
/openbmc/u-boot/board/Synology/ds109/
H A Dkwbimage.cfg99 # bit2: 0, DDR ODT control lsd (disabled)
101 # bit6: 1, DDR ODT control msb, (disabled)
120 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
121 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
139 DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
140 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
141 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
145 DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg99 # bit2: 0, DDR ODT control lsd (disabled)
101 # bit6: 1, DDR ODT control msb, (disabled)
120 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
121 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
137 DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
143 DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
144 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
148 DATA 0xffd0149c 0x0000e803 # CPU ODT Control
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg96 # bit2: 1, DDR ODT control lsd (disabled)
98 # bit6: 0, DDR ODT control msb, (disabled)
117 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
118 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
134 DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
140 DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
141 # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
145 DATA 0xffd0149c 0x0000e803 # CPU ODT Control
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg95 # bit2: 0, DDR ODT control lsd (disabled)
97 # bit6: 1, DDR ODT control msb, (disabled)
116 DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
133 DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
139 DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
140 # bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
144 DATA 0xffd0149c 0x0000e803 # CPU ODT Control

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