Lines Matching refs:ODT
110 # bit2: 1, DDR ODT control lsd disabled
112 # bit6: 0, DDR ODT control msb disabled
135 # bit15-12: 0100, internal ODT assertion 4 cycles after read
136 # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
142 # bit11-8 : 0100, internal ODT assertion x cycles after write
143 # bit15-12: 1000, internal ODT de-assertion x cycles after write
157 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
161 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
162 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
166 DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
167 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
168 # bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
170 # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
171 # bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
172 # bit14 :1, STARTBURST ODT enabled
173 # bit15 :1, Use ODT Block