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Searched refs:NUM_FCLK_DPM_LEVELS (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h102 #define NUM_FCLK_DPM_LEVELS 4 macro
113 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
H A Dsmu11_driver_if.h43 #define NUM_FCLK_DPM_LEVELS 8 macro
58 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
426 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ];
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu12_driver_if.h107 #define NUM_FCLK_DPM_LEVELS 4 macro
119 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
H A Dsmu11_driver_if_vangogh.h110 #define NUM_FCLK_DPM_LEVELS 4 macro
138 df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
H A Dsmu13_driver_if_aldebaran.h34 #define NUM_FCLK_DPM_LEVELS 8 macro
302 uint32_t FidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
303 uint8_t DidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
H A Dsmu13_driver_if_v13_0_7.h45 #define NUM_FCLK_DPM_LEVELS 8 macro
1060 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1131 …uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM s…
1132 …uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK …
1133 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state
1404 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
H A Dsmu13_driver_if_v13_0_0.h44 #define NUM_FCLK_DPM_LEVELS 8 macro
1051 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1129 …uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM s…
1130 …uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK …
1131 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state
1411 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
H A Dsmu11_driver_if_arcturus.h40 #define NUM_FCLK_DPM_LEVELS 8 macro
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
520 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
H A Dsmu_v13_0_6_pmfw.h31 #define NUM_FCLK_DPM_LEVELS 4 macro
H A Dsmu11_driver_if_sienna_cichlid.h48 #define NUM_FCLK_DPM_LEVELS 8 macro
67 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
691 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
1051 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c218 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
228 if (dpm_level >= NUM_FCLK_DPM_LEVELS) in renoir_get_dpm_clk_limited()
572 count = NUM_FCLK_DPM_LEVELS; in renoir_print_clk_levels()
774 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in renoir_get_dpm_clock_table()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c2233 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in vangogh_get_dpm_clock_table()
2238 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { in vangogh_get_dpm_clock_table()
H A Darcturus_ppt.c1792 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
H A Dsienna_cichlid_ppt.c2736 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable()
3374 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_processpptables.c336 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
H A Dsmu10_hwmgr.c516 NUM_FCLK_DPM_LEVELS, in smu10_populate_clock_table()
H A Dvega20_hwmgr.c3620 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS, in vega20_set_fclk_to_highest_dpm_level()