Revision tags: v6.6.25, v6.6.24, v6.6.23 |
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#
310ae9eb |
| 27-Feb-2024 |
Asad Kamal <asad.kamal@amd.com> |
drm/amd/pm: Fix esm reg mask use to get pcie speed
[ Upstream commit b485b899e5b8f83723833feca30a1a1e3df778df ]
Fix mask used for esm ctrl register to get pcie link speed on smu_v11_0_3, smu_v13_0_
drm/amd/pm: Fix esm reg mask use to get pcie speed
[ Upstream commit b485b899e5b8f83723833feca30a1a1e3df778df ]
Fix mask used for esm ctrl register to get pcie link speed on smu_v11_0_3, smu_v13_0_2 & smu_v13_0_6
Fixes: 511a95552ec8 ("drm/amd/pm: Add SMU 13.0.6 support") Fixes: c05d1c401572 ("drm/amd/swsmu: add aldebaran smu13 ip support (v3)") Fixes: f1c378593153 ("drm/amd/powerplay: add Arcturus support for gpu metrics export") Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45 |
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#
9366c2e8 |
| 10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Rename AMDGPU_PP_SENSOR_GPU_POWER
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <ale
drm/amd: Rename AMDGPU_PP_SENSOR_GPU_POWER
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47f1724d |
| 10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`
Some GPUs have been overloading average power values and input power values. To disambiguate these, introduce a new `AMDGPU_PP_SENSOR_GPU_INPUT_
drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`
Some GPUs have been overloading average power values and input power values. To disambiguate these, introduce a new `AMDGPU_PP_SENSOR_GPU_INPUT_POWER` and the GPUs that share input power update to use this instead of average power.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2746 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.44, v6.1.43, v6.1.42, v6.1.41 |
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#
8d066f2b |
| 24-Jul-2023 |
Ran Sun <sunran001@208suo.com> |
drm/amd/pm: Clean up errors in arcturus_ppt.c
Fix the following errors reported by checkpatch:
ERROR: spaces required around that '=' (ctx:VxW) ERROR: spaces required around that '>=' (ctx:WxV)
Si
drm/amd/pm: Clean up errors in arcturus_ppt.c
Fix the following errors reported by checkpatch:
ERROR: spaces required around that '=' (ctx:VxW) ERROR: spaces required around that '>=' (ctx:WxV)
Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35 |
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#
d934e537 |
| 20-Jun-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amd/pm: fix smu i2c data read risk
the smu driver_table is used for all types of smu tables data transcation (e.g: PPtable, Metrics, i2c, Ecc..).
it is necessary to hold this lock to avoiding d
drm/amd/pm: fix smu i2c data read risk
the smu driver_table is used for all types of smu tables data transcation (e.g: PPtable, Metrics, i2c, Ecc..).
it is necessary to hold this lock to avoiding data tampering during the i2c read operation.
Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
62b73bd5 |
| 20-Jun-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amd/pm: fix smu i2c data read risk
the smu driver_table is used for all types of smu tables data transcation (e.g: PPtable, Metrics, i2c, Ecc..).
it is necessary to hold this lock to avoiding d
drm/amd/pm: fix smu i2c data read risk
the smu driver_table is used for all types of smu tables data transcation (e.g: PPtable, Metrics, i2c, Ecc..).
it is necessary to hold this lock to avoiding data tampering during the i2c read operation.
Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0 |
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#
3059cd8c |
| 28-Sep-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: disable cstate feature for gpu reset scenario
Suggested by PMFW team and same as what did for gfxoff feature. This can address some Mode1Reset failures observed on SMU13.0.0.
Signed-off
drm/amd/pm: disable cstate feature for gpu reset scenario
Suggested by PMFW team and same as what did for gfxoff feature. This can address some Mode1Reset failures observed on SMU13.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.0.x Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b31d6ada |
| 28-Sep-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: disable cstate feature for gpu reset scenario
Suggested by PMFW team and same as what did for gfxoff feature. This can address some Mode1Reset failures observed on SMU13.0.0.
Signed-off
drm/amd/pm: disable cstate feature for gpu reset scenario
Suggested by PMFW team and same as what did for gfxoff feature. This can address some Mode1Reset failures observed on SMU13.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.0.x
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Revision tags: v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37 |
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#
543faf57 |
| 29-Apr-2022 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Fix incorrect variable for size of clocks array
[v2] No Changes, added RB [v1] Size of pp_clock_levels_with_latency is PP_MAX_CLOCK_LEVELS, not MAX_NUM_CLOCKS. Both are currently define
amdgpu/pm: Fix incorrect variable for size of clocks array
[v2] No Changes, added RB [v1] Size of pp_clock_levels_with_latency is PP_MAX_CLOCK_LEVELS, not MAX_NUM_CLOCKS. Both are currently defined as 16, modifying in case one value is modified in future Changed code in both arcturus and aldabaran.
Also removed unneeded var count, and used min_t function
Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
da1db031 |
| 26-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
So we can eventaully use them in the common smu code for accessing the SMU mailboxes without needing a lot of per asic logic in the common
drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
So we can eventaully use them in the common smu code for accessing the SMU mailboxes without needing a lot of per asic logic in the common code.
Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7 |
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#
2d282665 |
| 07-Dec-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: update the data type for retrieving enabled ppfeatures
Use uint64_t instead of an array of uint32_t. This can avoid some non-necessary intermediate uint32_t -> uint64_t conversions.
Sig
drm/amd/pm: update the data type for retrieving enabled ppfeatures
Use uint64_t instead of an array of uint32_t. This can avoid some non-necessary intermediate uint32_t -> uint64_t conversions.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f89154b6 |
| 28-Jan-2022 |
Changcheng Deng <deng.changcheng@zte.com.cn> |
drm/amd/pm: remove duplicate include in 'arcturus_ppt.c'
'amdgpu_dpm.h' included in 'arcturus_ppt.c' is duplicated.
Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.
drm/amd/pm: remove duplicate include in 'arcturus_ppt.c'
'amdgpu_dpm.h' included in 'arcturus_ppt.c' is duplicated.
Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e281d594 |
| 27-Jan-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/swsmu/i2c: return an error if the SMU is not running
Return an error if someone tries to use the i2c bus when the SMU is not running. Otherwise we can end up sending commands to the SMU
drm/amdgpu/swsmu/i2c: return an error if the SMU is not running
Return an error if someone tries to use the i2c bus when the SMU is not running. Otherwise we can end up sending commands to the SMU which will either get ignored or could cause other issues depending on what state the GPU and SMU are in.
Cc: Luben.Tuikov@amd.com Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2f60dd50 |
| 19-Jan-2022 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amd: Expose the FRU SMU I2C bus
Expose both SMU I2C buses. Some boards use the same bus for both the RAS and FRU EEPROMs and others use different buses. This enables the additional I2C bus and
drm/amd: Expose the FRU SMU I2C bus
Expose both SMU I2C buses. Some boards use the same bus for both the RAS and FRU EEPROMs and others use different buses. This enables the additional I2C bus and sets the right buses to use for RAS and FRU EEPROM access.
Cc: Roy Sun <Roy.Sun@amd.com> Co-developed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.6 |
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#
56383e8f |
| 28-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: drop unneeded smu->sensor_lock
As all those related APIs are already well protected by adev->pm.mutex and smu->message_lock.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Gu
drm/amd/pm: drop unneeded smu->sensor_lock
As all those related APIs are already well protected by adev->pm.mutex and smu->message_lock.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
da11407f |
| 28-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: drop unneeded smu->metrics_lock
As all those related APIs are already well protected by adev->pm.mutex and smu->message_lock.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: G
drm/amd/pm: drop unneeded smu->metrics_lock
As all those related APIs are already well protected by adev->pm.mutex and smu->message_lock.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e0638c7a |
| 28-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: drop unneeded lock protection smu->mutex
As all those APIs are already protected either by adev->pm.mutex or smu->message_lock.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by:
drm/amd/pm: drop unneeded lock protection smu->mutex
As all those APIs are already protected either by adev->pm.mutex or smu->message_lock.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.5, v5.15.4, v5.15.3 |
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#
837d542a |
| 15-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: relocate the power related headers
Instead of centralizing all headers in the same folder. Separate them into different folders and place them among those source files those who really n
drm/amd/pm: relocate the power related headers
Instead of centralizing all headers in the same folder. Separate them into different folders and place them among those source files those who really need them.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ebfc2533 |
| 21-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: do not expose the smu_context structure used internally in power
This can cover the power implementation details. And as what did for powerplay framework, we hook the smu_context to adev
drm/amd/pm: do not expose the smu_context structure used internally in power
This can cover the power implementation details. And as what did for powerplay framework, we hook the smu_context to adev->powerplay.pp_handle.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4da8b639 |
| 17-Dec-2021 |
sashank saye <sashank.saye@amd.com> |
drm/amdgpu: Send Message to SMU on aldebaran passthrough for sbr handling
For Aldebaran chip passthrough case we need to intimate SMU about special handling for SBR.On older chips we send LightSBR t
drm/amdgpu: Send Message to SMU on aldebaran passthrough for sbr handling
For Aldebaran chip passthrough case we need to intimate SMU about special handling for SBR.On older chips we send LightSBR to SMU, enabling the same for Aldebaran. Slight difference, compared to previous chips, is on Aldebaran, SMU would do a heavy reset on SBR. Hence, the word Heavy instead of Light SBR is used for SMU to differentiate.
Reviewed by: Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by: sashank saye <sashank.saye@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
91e16017 |
| 14-Dec-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Skip power state allocation
Power states are not valid for arcturus and aldebaran, no need to allocate memory.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Yang Wang <kev
drm/amd/pm: Skip power state allocation
Power states are not valid for arcturus and aldebaran, no need to allocate memory.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
94a80b5b |
| 23-Nov-2021 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Modify implmentations of get_power_profile_mode to use amdgpu_pp_profile_name
After modifying navi10 in previous commit, extend the changes so all implementations of pp_hwmgr_func->get_
amdgpu/pm: Modify implmentations of get_power_profile_mode to use amdgpu_pp_profile_name
After modifying navi10 in previous commit, extend the changes so all implementations of pp_hwmgr_func->get_power_profile_mode and pptable_funcs->get_power_profile_mode use amdgpu_pp_profile_name
== Test == LOGFILE=pp_profile_strings.test.log AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
lspci -nn | grep "VGA\|Display" > $LOGFILE FILES="pp_power_profile_mode "
for f in $FILES do echo === $f === >> $LOGFILE cat $HWMON_DIR/device/$f >> $LOGFILE done cat $LOGFILE
Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.2, v5.15.1, v5.15 |
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#
47b67c99 |
| 22-Oct-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Disable fan control if not supported
On arcturus, not all platforms use PMFW based fan control. On such ASICs fan control by PMFW will be disabled in PPTable. Disable hwmon knobs for fan
drm/amd/pm: Disable fan control if not supported
On arcturus, not all platforms use PMFW based fan control. On such ASICs fan control by PMFW will be disabled in PPTable. Disable hwmon knobs for fan control also as it is not possible to report or control fan speed on such platforms through driver.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63 |
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#
ee121f7e |
| 08-Sep-2021 |
Lang Yu <lang.yu@amd.com> |
drm/amdgpu: fix sysfs_emit/sysfs_emit_at warnings(v2)
sysfs_emit and sysfs_emit_at requrie a page boundary aligned buf address. Make them happy!
v2: use an inline function.
Warning Log: [ 492.545
drm/amdgpu: fix sysfs_emit/sysfs_emit_at warnings(v2)
sysfs_emit and sysfs_emit_at requrie a page boundary aligned buf address. Make them happy!
v2: use an inline function.
Warning Log: [ 492.545174] invalid sysfs_emit_at: buf:00000000f19bdfde at:0 [ 492.546416] WARNING: CPU: 7 PID: 1304 at fs/sysfs/file.c:765 sysfs_emit_at+0x4a/0xa0 [ 492.654805] Call Trace: [ 492.655353] ? smu_cmn_get_metrics_table+0x40/0x50 [amdgpu] [ 492.656780] vangogh_print_clk_levels+0x369/0x410 [amdgpu] [ 492.658245] vangogh_common_print_clk_levels+0x77/0x80 [amdgpu] [ 492.659733] ? preempt_schedule_common+0x18/0x30 [ 492.660713] smu_print_ppclk_levels+0x65/0x90 [amdgpu] [ 492.662107] amdgpu_get_pp_od_clk_voltage+0x13d/0x190 [amdgpu] [ 492.663620] dev_attr_show+0x1d/0x40
Signed-off-by: Lang Yu <lang.yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8f48ba30 |
| 08-Sep-2021 |
Lang Yu <lang.yu@amd.com> |
drm/amdgpu: fix sysfs_emit/sysfs_emit_at warnings(v2)
sysfs_emit and sysfs_emit_at requrie a page boundary aligned buf address. Make them happy!
v2: use an inline function.
Warning Log: [ 492.545
drm/amdgpu: fix sysfs_emit/sysfs_emit_at warnings(v2)
sysfs_emit and sysfs_emit_at requrie a page boundary aligned buf address. Make them happy!
v2: use an inline function.
Warning Log: [ 492.545174] invalid sysfs_emit_at: buf:00000000f19bdfde at:0 [ 492.546416] WARNING: CPU: 7 PID: 1304 at fs/sysfs/file.c:765 sysfs_emit_at+0x4a/0xa0 [ 492.654805] Call Trace: [ 492.655353] ? smu_cmn_get_metrics_table+0x40/0x50 [amdgpu] [ 492.656780] vangogh_print_clk_levels+0x369/0x410 [amdgpu] [ 492.658245] vangogh_common_print_clk_levels+0x77/0x80 [amdgpu] [ 492.659733] ? preempt_schedule_common+0x18/0x30 [ 492.660713] smu_print_ppclk_levels+0x65/0x90 [amdgpu] [ 492.662107] amdgpu_get_pp_od_clk_voltage+0x13d/0x190 [amdgpu] [ 492.663620] dev_attr_show+0x1d/0x40
Signed-off-by: Lang Yu <lang.yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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