Home
last modified time | relevance | path

Searched refs:MHz (Results 1 – 25 of 180) sorted by relevance

12345678

/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h69 #define MHz 1000000 macro
71 #define OSC_HZ (24*MHz)
72 #define LPLL_HZ (600*MHz)
73 #define BPLL_HZ (600*MHz)
74 #define GPLL_HZ (594*MHz)
75 #define CPLL_HZ (384*MHz)
76 #define PPLL_HZ (676*MHz)
78 #define PMU_PCLK_HZ (48*MHz)
80 #define ACLKM_CORE_L_HZ (300*MHz)
81 #define ATCLK_CORE_L_HZ (300*MHz)
[all …]
H A Dcru_rk3328.h47 #define MHz 1000000 macro
49 #define OSC_HZ (24 * MHz)
50 #define APLL_HZ (600 * MHz)
51 #define GPLL_HZ (576 * MHz)
52 #define CPLL_HZ (594 * MHz)
54 #define CLK_CORE_HZ (600 * MHz)
55 #define ACLKM_CORE_HZ (300 * MHz)
56 #define PCLK_DBG_HZ (300 * MHz)
62 #define PWM_CLOCK_HZ (74 * MHz)
H A Dcru_rk322x.h10 #define MHz 1000000 macro
11 #define OSC_HZ (24 * MHz)
13 #define APLL_HZ (600 * MHz)
14 #define GPLL_HZ (594 * MHz)
H A Dcru_rk3128.h11 #define MHz 1000000 macro
12 #define OSC_HZ (24 * MHz)
14 #define APLL_HZ (600 * MHz)
15 #define GPLL_HZ (594 * MHz)
/openbmc/u-boot/doc/
H A DREADME.Heterogeneous-SoCs90 CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
91 DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
92 DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
93 CCB:666.667 MHz,
94 DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
95 CPRI:600 MHz
96 MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
97 FMAN1: 666.667 MHz
98 QMAN: 333.333 MHz
H A DREADME.fsl-hwconfig11 route either a 11.2896MHz or a 12.288MHz clock. The default is
12 12.288MHz. This option has two effects. First, the MUX on the board
18 Select the 11.2896MHz clock
21 Select the 12.288MHz clock
/openbmc/u-boot/board/freescale/t102xqds/
H A Dt1024_sd_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_spi_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_nand_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A DREADME114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
115 - Software programmable in 1 MHz increments from 1-200 MHz.
118 - 100 MHz, 125 MHz and 156.25 MHz options.
119 - Spread-spectrum option for 100 MHz.
196 0x6F 100MHz 125MHz 1101
197 0xD6 100MHz 100MHz 1111
198 0x99 156.25MHz 100MHz 1011
204 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
205 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
206 Bin3: 1000MHz 1600MT/s 400MHz 500MHz
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/fbset/fbset-modes/om-gta01/
H A Dfb.modes4 # D: 26.000 MHz, H: 43.334 kHz, V: 65.657 Hz
11 # D: 26.000 MHz, H: 43.334 kHz, V: 65.657 Hz
18 # D: 8.475 MHz, H: 24.635 kHz, V: 75.569 Hz
25 # D: 8.475 MHz, H: 24.635 kHz, V: 75.569 Hz
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
/openbmc/u-boot/board/freescale/t208xrdb/
H A Dt2080_sd_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
H A Dt2080_nand_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
H A Dt2080_spi_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
/openbmc/u-boot/board/boundary/nitrogen6x/
H A Dddr-setup.cfg18 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
20 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
22 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
/openbmc/u-boot/board/freescale/p1022ds/
H A DREADME13 'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
17 is 11MHz), disable eTsec2 and TDM
20 and AUDIO codec clock sources only setting as 11MHz or 12MHz !
/openbmc/u-boot/board/toradex/apalis_imx6/
H A Dddr-setup.cfg19 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
21 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
23 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
/openbmc/u-boot/board/toradex/colibri_imx6/
H A Dddr-setup.cfg19 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
21 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
23 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
/openbmc/u-boot/board/freescale/t208xqds/
H A Dt2080_spi_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
12 #SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
H A Dt2080_sd_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
12 #SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
H A Dt2080_nand_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
12 #SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
/openbmc/u-boot/board/sbc8548/
H A DREADME5 MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
6 memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
26 a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
29 The second enables PCI support and builds for a 33MHz clock rate. Note
30 that if a 33MHz 32bit card is inserted in the slot, then the whole board
31 will clock down to a 33MHz base clock instead of the default 66MHz. This
33 were previously running at 66MHz. If you want to use a 33MHz PCI card,
35 to flash prior to powering down the board and inserting the 33MHz PCI
40 default 66MHz. Options four and five are just repeats of option two
45 a 33MHz PCI configuration is currently untested.)
[all …]
/openbmc/u-boot/doc/SPI/
H A DREADME.ftssp010_spi_test6 CPU: FA626TE 528 MHz
7 AHB: 132 MHz
8 APB: 66 MHz
/openbmc/u-boot/board/freescale/ls1012afrdm/
H A DREADME22 to 108/54 MHz
38 - 25 MHz crystal for LS1012A
39 - 8 MHz Crystal for K20
40 - 24 MHz for SC16IS740IPW SPI to Dual UART bridge

12345678