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Searched refs:Low (Results 1 – 25 of 66) sorted by relevance

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/openbmc/u-boot/arch/arm/dts/
H A Dstih410-b2260.dts77 /* Low speed expansion connector */
83 /* Low speed expansion connector */
89 /* Low speed expansion connector */
96 /* Low speed expansion connector */
102 /* Low speed expansion connector */
H A Dkirkwood-openrd.dtsi63 * Low: RS-232
81 * Low: UART
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dpower_distribution.hpp26 Low, enumerator
66 {TransferSensitivityType::Low, "Low"},
/openbmc/u-boot/arch/arm/
H A DKconfig.debug4 bool "Low-level debugging functions"
12 prompt "Low-level debugging port"
16 bool "Low-level debugging via 8250 UART"
/openbmc/u-boot/drivers/video/bridge/
H A DKconfig14 The Parade PS8622 and PS8625 are DisplayPort-to-LVDS (Low voltage
24 The NXP PTN3460 is a DisplayPort-to-LVDS (Low voltage differential
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/liblc3/
H A Dliblc3_1.0.4.bb1 SUMMARY = "Low Complexity Communication Codec (LC3)"
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg35 # DDR Controller Control Low
53 # DDR Timing (Low)
177 # DDR ODT Control (Low)
188 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
189 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
H A Dkwbimage-lsxhl.cfg35 # DDR Controller Control Low
53 # DDR Timing (Low)
177 # DDR ODT Control (Low)
188 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
189 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
/openbmc/u-boot/board/Synology/ds109/
H A Dopenocd.cfg45 mww 0xD0001404 0x39743000 ;# Dunit Control Low Register
46 mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
63 mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
H A Dkwbimage.cfg34 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
45 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
139 DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg34 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
51 DATA 0xFFD01408 0x22125451 # DDR Timing (Low)
160 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
169 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
170 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
/openbmc/u-boot/drivers/video/rockchip/
H A DKconfig16 Multimedia Interface (HDMI), Low-voltage Differential Signalling
52 This enables Low-voltage Differential Signaling(LVDS) display
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg35 DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
46 DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
136 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage-memphis.cfg53 DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
65 DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
131 DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
157 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg33 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
44 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
136 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg36 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
47 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
139 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg31 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
42 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
134 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg30 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
41 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
133 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg30 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
41 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
133 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
/openbmc/u-boot/arch/arm/mach-sti/
H A DKconfig25 - Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces)
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-filter/libnfnetlink/
H A Dlibnfnetlink_1.0.2.bb1 SUMMARY = "Low-level library for netfilter related kernel/userspace communication"
/openbmc/openbmc/meta-openembedded/meta-perl/recipes-perl/libcompress/
H A Dlibcompress-raw-bzip2-perl_2.213.bb1 SUMMARY = "Low-Level Interface to bzip2 compression library"
H A Dlibcompress-raw-lzma-perl_2.213.bb1 SUMMARY = "Low-Level Interface to lzma compresion library."
/openbmc/openbmc/meta-openembedded/meta-initramfs/recipes-devtools/klibc/files/
H A D0001-klibc-add-getrandom-syscall.patch24 * Low-level I/O (generally architecture-specific);
H A D0001-klibc_2.0.4-add-kexec_file_load-syscall.patch24 * Low-level I/O (generally architecture-specific);

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