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Searched refs:I915_MAX_PIPES (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_bw.h26 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
50 int min_cdclk[I915_MAX_PIPES];
51 unsigned int data_rate[I915_MAX_PIPES];
52 u8 num_active_planes[I915_MAX_PIPES];
H A Dintel_display_irq.h73 void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
75 … i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
76 … i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]);
77 void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]);
78 … i8xx_pipestat_irq_handler(struct drm_i915_private *i915, u16 iir, u32 pipe_stats[I915_MAX_PIPES]);
H A Dskl_watermark.h54 struct skl_ddb_entry ddb[I915_MAX_PIPES];
55 unsigned int weight[I915_MAX_PIPES];
56 u8 slices[I915_MAX_PIPES];
H A Dintel_cdclk.h42 int min_cdclk[I915_MAX_PIPES];
44 u8 min_voltage_level[I915_MAX_PIPES];
H A Dintel_display_device.h86 u8 num_sprites[I915_MAX_PIPES];
87 u8 num_scalers[I915_MAX_PIPES];
117 u32 cursor_offsets[I915_MAX_PIPES];
H A Dintel_display_limits.h23 I915_MAX_PIPES = _PIPE_EDP enumerator
H A Dintel_pmdemand.h37 int ddi_clocks[I915_MAX_PIPES];
H A Dintel_frontbuffer.c300 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > in intel_frontbuffer_track()
302 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); in intel_frontbuffer_track()
H A Dintel_display_irq.c412 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument
478 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) in i8xx_pipestat_irq_handler() argument
495 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument
519 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument
546 u32 pipe_stats[I915_MAX_PIPES]) in valleyview_pipestat_irq_handler() argument
H A Dintel_display_core.h500 u32 chv_dpll_md[I915_MAX_PIPES];
H A Dintel_dvo.c416 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init_dev()
H A Dintel_display.h223 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
H A Dintel_display_device.c884 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); in intel_display_device_info_runtime_init()
H A Dintel_display_types.h1755 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
H A Dskl_watermark.c826 u8 dbuf_mask[I915_MAX_PIPES];
3065 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_dbuf_is_misconfigured()
3086 I915_MAX_PIPES, crtc->pipe)) in skl_dbuf_is_misconfigured()
H A Dintel_display.c6753 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_commit_modeset_enables()
6790 entries, I915_MAX_PIPES, pipe)) in skl_commit_modeset_enables()
6858 entries, I915_MAX_PIPES, pipe)); in skl_commit_modeset_enables()
6983 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; in intel_atomic_commit_tail()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dfb_decoder.c187 for (i = 0; i < I915_MAX_PIPES; i++) in get_active_pipe()
211 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_primary_plane()
342 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_cursor_plane()
421 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_sprite_plane()
H A Dfb_decoder.h163 struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES];
H A Dgvt.h115 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
H A Ddisplay.c79 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_irq.c264 u32 pipe_stats[I915_MAX_PIPES] = {}; in valleyview_irq_handler()
350 u32 pipe_stats[I915_MAX_PIPES] = {}; in cherryview_irq_handler()
1000 u32 pipe_stats[I915_MAX_PIPES] = {}; in i8xx_irq_handler()
1102 u32 pipe_stats[I915_MAX_PIPES] = {}; in i915_irq_handler()
1228 u32 pipe_stats[I915_MAX_PIPES] = {}; in i965_irq_handler()
H A Di915_drv.h240 u32 de_irq_mask[I915_MAX_PIPES];
242 u32 pipestat_irq_mask[I915_MAX_PIPES];