142a0d256SVille Syrjälä // SPDX-License-Identifier: MIT
242a0d256SVille Syrjälä /*
342a0d256SVille Syrjälä * Copyright © 2022 Intel Corporation
442a0d256SVille Syrjälä */
542a0d256SVille Syrjälä
642a0d256SVille Syrjälä #include <drm/drm_blend.h>
742a0d256SVille Syrjälä
894b49d53SJani Nikula #include "i915_drv.h"
994b49d53SJani Nikula #include "i915_fixed.h"
1094b49d53SJani Nikula #include "i915_reg.h"
1194b49d53SJani Nikula #include "i9xx_wm.h"
1242a0d256SVille Syrjälä #include "intel_atomic.h"
1342a0d256SVille Syrjälä #include "intel_atomic_plane.h"
1442a0d256SVille Syrjälä #include "intel_bw.h"
15636f973cSVille Syrjälä #include "intel_crtc.h"
1642a0d256SVille Syrjälä #include "intel_de.h"
1742a0d256SVille Syrjälä #include "intel_display.h"
1842a0d256SVille Syrjälä #include "intel_display_power.h"
1942a0d256SVille Syrjälä #include "intel_display_types.h"
2042a0d256SVille Syrjälä #include "intel_fb.h"
2142a0d256SVille Syrjälä #include "intel_pcode.h"
2294b49d53SJani Nikula #include "intel_wm.h"
2394b49d53SJani Nikula #include "skl_watermark.h"
24689e61a4SJani Nikula #include "skl_watermark_regs.h"
2542a0d256SVille Syrjälä
2642a0d256SVille Syrjälä static void skl_sagv_disable(struct drm_i915_private *i915);
2742a0d256SVille Syrjälä
2842a0d256SVille Syrjälä /* Stores plane specific WM parameters */
2942a0d256SVille Syrjälä struct skl_wm_params {
3042a0d256SVille Syrjälä bool x_tiled, y_tiled;
3142a0d256SVille Syrjälä bool rc_surface;
3242a0d256SVille Syrjälä bool is_planar;
3342a0d256SVille Syrjälä u32 width;
3442a0d256SVille Syrjälä u8 cpp;
3542a0d256SVille Syrjälä u32 plane_pixel_rate;
3642a0d256SVille Syrjälä u32 y_min_scanlines;
3742a0d256SVille Syrjälä u32 plane_bytes_per_line;
3842a0d256SVille Syrjälä uint_fixed_16_16_t plane_blocks_per_line;
3942a0d256SVille Syrjälä uint_fixed_16_16_t y_tile_minimum;
4042a0d256SVille Syrjälä u32 linetime_us;
4142a0d256SVille Syrjälä u32 dbuf_block_size;
4242a0d256SVille Syrjälä };
4342a0d256SVille Syrjälä
intel_enabled_dbuf_slices_mask(struct drm_i915_private * i915)4442a0d256SVille Syrjälä u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915)
4542a0d256SVille Syrjälä {
4642a0d256SVille Syrjälä u8 enabled_slices = 0;
4742a0d256SVille Syrjälä enum dbuf_slice slice;
4842a0d256SVille Syrjälä
4942a0d256SVille Syrjälä for_each_dbuf_slice(i915, slice) {
5000136429SJani Nikula if (intel_de_read(i915, DBUF_CTL_S(slice)) & DBUF_POWER_STATE)
5142a0d256SVille Syrjälä enabled_slices |= BIT(slice);
5242a0d256SVille Syrjälä }
5342a0d256SVille Syrjälä
5442a0d256SVille Syrjälä return enabled_slices;
5542a0d256SVille Syrjälä }
5642a0d256SVille Syrjälä
5742a0d256SVille Syrjälä /*
5842a0d256SVille Syrjälä * FIXME: We still don't have the proper code detect if we need to apply the WA,
5942a0d256SVille Syrjälä * so assume we'll always need it in order to avoid underruns.
6042a0d256SVille Syrjälä */
skl_needs_memory_bw_wa(struct drm_i915_private * i915)6142a0d256SVille Syrjälä static bool skl_needs_memory_bw_wa(struct drm_i915_private *i915)
6242a0d256SVille Syrjälä {
6342a0d256SVille Syrjälä return DISPLAY_VER(i915) == 9;
6442a0d256SVille Syrjälä }
6542a0d256SVille Syrjälä
6642a0d256SVille Syrjälä static bool
intel_has_sagv(struct drm_i915_private * i915)6742a0d256SVille Syrjälä intel_has_sagv(struct drm_i915_private *i915)
6842a0d256SVille Syrjälä {
6943e6fad1SVille Syrjälä return HAS_SAGV(i915) &&
7042a0d256SVille Syrjälä i915->display.sagv.status != I915_SAGV_NOT_CONTROLLED;
7142a0d256SVille Syrjälä }
7242a0d256SVille Syrjälä
7342a0d256SVille Syrjälä static u32
intel_sagv_block_time(struct drm_i915_private * i915)7442a0d256SVille Syrjälä intel_sagv_block_time(struct drm_i915_private *i915)
7542a0d256SVille Syrjälä {
76825477e7SRadhakrishna Sripada if (DISPLAY_VER(i915) >= 14) {
77825477e7SRadhakrishna Sripada u32 val;
78825477e7SRadhakrishna Sripada
7900136429SJani Nikula val = intel_de_read(i915, MTL_LATENCY_SAGV);
80825477e7SRadhakrishna Sripada
81825477e7SRadhakrishna Sripada return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val);
82825477e7SRadhakrishna Sripada } else if (DISPLAY_VER(i915) >= 12) {
8342a0d256SVille Syrjälä u32 val = 0;
8442a0d256SVille Syrjälä int ret;
8542a0d256SVille Syrjälä
8642a0d256SVille Syrjälä ret = snb_pcode_read(&i915->uncore,
8742a0d256SVille Syrjälä GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
8842a0d256SVille Syrjälä &val, NULL);
8942a0d256SVille Syrjälä if (ret) {
9042a0d256SVille Syrjälä drm_dbg_kms(&i915->drm, "Couldn't read SAGV block time!\n");
9142a0d256SVille Syrjälä return 0;
9242a0d256SVille Syrjälä }
9342a0d256SVille Syrjälä
9442a0d256SVille Syrjälä return val;
9542a0d256SVille Syrjälä } else if (DISPLAY_VER(i915) == 11) {
9642a0d256SVille Syrjälä return 10;
9743e6fad1SVille Syrjälä } else if (HAS_SAGV(i915)) {
9842a0d256SVille Syrjälä return 30;
9942a0d256SVille Syrjälä } else {
10042a0d256SVille Syrjälä return 0;
10142a0d256SVille Syrjälä }
10242a0d256SVille Syrjälä }
10342a0d256SVille Syrjälä
intel_sagv_init(struct drm_i915_private * i915)10442a0d256SVille Syrjälä static void intel_sagv_init(struct drm_i915_private *i915)
10542a0d256SVille Syrjälä {
10643e6fad1SVille Syrjälä if (!HAS_SAGV(i915))
10742a0d256SVille Syrjälä i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
10842a0d256SVille Syrjälä
10942a0d256SVille Syrjälä /*
11042a0d256SVille Syrjälä * Probe to see if we have working SAGV control.
11142a0d256SVille Syrjälä * For icl+ this was already determined by intel_bw_init_hw().
11242a0d256SVille Syrjälä */
11342a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 11)
11442a0d256SVille Syrjälä skl_sagv_disable(i915);
11542a0d256SVille Syrjälä
11642a0d256SVille Syrjälä drm_WARN_ON(&i915->drm, i915->display.sagv.status == I915_SAGV_UNKNOWN);
11742a0d256SVille Syrjälä
11842a0d256SVille Syrjälä i915->display.sagv.block_time_us = intel_sagv_block_time(i915);
11942a0d256SVille Syrjälä
12042a0d256SVille Syrjälä drm_dbg_kms(&i915->drm, "SAGV supported: %s, original SAGV block time: %u us\n",
12142a0d256SVille Syrjälä str_yes_no(intel_has_sagv(i915)), i915->display.sagv.block_time_us);
12242a0d256SVille Syrjälä
12342a0d256SVille Syrjälä /* avoid overflow when adding with wm0 latency/etc. */
12442a0d256SVille Syrjälä if (drm_WARN(&i915->drm, i915->display.sagv.block_time_us > U16_MAX,
12542a0d256SVille Syrjälä "Excessive SAGV block time %u, ignoring\n",
12642a0d256SVille Syrjälä i915->display.sagv.block_time_us))
12742a0d256SVille Syrjälä i915->display.sagv.block_time_us = 0;
12842a0d256SVille Syrjälä
12942a0d256SVille Syrjälä if (!intel_has_sagv(i915))
13042a0d256SVille Syrjälä i915->display.sagv.block_time_us = 0;
13142a0d256SVille Syrjälä }
13242a0d256SVille Syrjälä
13342a0d256SVille Syrjälä /*
13442a0d256SVille Syrjälä * SAGV dynamically adjusts the system agent voltage and clock frequencies
13542a0d256SVille Syrjälä * depending on power and performance requirements. The display engine access
13642a0d256SVille Syrjälä * to system memory is blocked during the adjustment time. Because of the
13742a0d256SVille Syrjälä * blocking time, having this enabled can cause full system hangs and/or pipe
13842a0d256SVille Syrjälä * underruns if we don't meet all of the following requirements:
13942a0d256SVille Syrjälä *
14042a0d256SVille Syrjälä * - <= 1 pipe enabled
14142a0d256SVille Syrjälä * - All planes can enable watermarks for latencies >= SAGV engine block time
14242a0d256SVille Syrjälä * - We're not using an interlaced display configuration
14342a0d256SVille Syrjälä */
skl_sagv_enable(struct drm_i915_private * i915)14442a0d256SVille Syrjälä static void skl_sagv_enable(struct drm_i915_private *i915)
14542a0d256SVille Syrjälä {
14642a0d256SVille Syrjälä int ret;
14742a0d256SVille Syrjälä
14842a0d256SVille Syrjälä if (!intel_has_sagv(i915))
14942a0d256SVille Syrjälä return;
15042a0d256SVille Syrjälä
15142a0d256SVille Syrjälä if (i915->display.sagv.status == I915_SAGV_ENABLED)
15242a0d256SVille Syrjälä return;
15342a0d256SVille Syrjälä
15442a0d256SVille Syrjälä drm_dbg_kms(&i915->drm, "Enabling SAGV\n");
15542a0d256SVille Syrjälä ret = snb_pcode_write(&i915->uncore, GEN9_PCODE_SAGV_CONTROL,
15642a0d256SVille Syrjälä GEN9_SAGV_ENABLE);
15742a0d256SVille Syrjälä
15842a0d256SVille Syrjälä /* We don't need to wait for SAGV when enabling */
15942a0d256SVille Syrjälä
16042a0d256SVille Syrjälä /*
16142a0d256SVille Syrjälä * Some skl systems, pre-release machines in particular,
16242a0d256SVille Syrjälä * don't actually have SAGV.
16342a0d256SVille Syrjälä */
16442a0d256SVille Syrjälä if (IS_SKYLAKE(i915) && ret == -ENXIO) {
16542a0d256SVille Syrjälä drm_dbg(&i915->drm, "No SAGV found on system, ignoring\n");
16642a0d256SVille Syrjälä i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
16742a0d256SVille Syrjälä return;
16842a0d256SVille Syrjälä } else if (ret < 0) {
16942a0d256SVille Syrjälä drm_err(&i915->drm, "Failed to enable SAGV\n");
17042a0d256SVille Syrjälä return;
17142a0d256SVille Syrjälä }
17242a0d256SVille Syrjälä
17342a0d256SVille Syrjälä i915->display.sagv.status = I915_SAGV_ENABLED;
17442a0d256SVille Syrjälä }
17542a0d256SVille Syrjälä
skl_sagv_disable(struct drm_i915_private * i915)17642a0d256SVille Syrjälä static void skl_sagv_disable(struct drm_i915_private *i915)
17742a0d256SVille Syrjälä {
17842a0d256SVille Syrjälä int ret;
17942a0d256SVille Syrjälä
18042a0d256SVille Syrjälä if (!intel_has_sagv(i915))
18142a0d256SVille Syrjälä return;
18242a0d256SVille Syrjälä
18342a0d256SVille Syrjälä if (i915->display.sagv.status == I915_SAGV_DISABLED)
18442a0d256SVille Syrjälä return;
18542a0d256SVille Syrjälä
18642a0d256SVille Syrjälä drm_dbg_kms(&i915->drm, "Disabling SAGV\n");
18742a0d256SVille Syrjälä /* bspec says to keep retrying for at least 1 ms */
18842a0d256SVille Syrjälä ret = skl_pcode_request(&i915->uncore, GEN9_PCODE_SAGV_CONTROL,
18942a0d256SVille Syrjälä GEN9_SAGV_DISABLE,
19042a0d256SVille Syrjälä GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
19142a0d256SVille Syrjälä 1);
19242a0d256SVille Syrjälä /*
19342a0d256SVille Syrjälä * Some skl systems, pre-release machines in particular,
19442a0d256SVille Syrjälä * don't actually have SAGV.
19542a0d256SVille Syrjälä */
19642a0d256SVille Syrjälä if (IS_SKYLAKE(i915) && ret == -ENXIO) {
19742a0d256SVille Syrjälä drm_dbg(&i915->drm, "No SAGV found on system, ignoring\n");
19842a0d256SVille Syrjälä i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
19942a0d256SVille Syrjälä return;
20042a0d256SVille Syrjälä } else if (ret < 0) {
20142a0d256SVille Syrjälä drm_err(&i915->drm, "Failed to disable SAGV (%d)\n", ret);
20242a0d256SVille Syrjälä return;
20342a0d256SVille Syrjälä }
20442a0d256SVille Syrjälä
20542a0d256SVille Syrjälä i915->display.sagv.status = I915_SAGV_DISABLED;
20642a0d256SVille Syrjälä }
20742a0d256SVille Syrjälä
skl_sagv_pre_plane_update(struct intel_atomic_state * state)20842a0d256SVille Syrjälä static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
20942a0d256SVille Syrjälä {
21042a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
21142a0d256SVille Syrjälä const struct intel_bw_state *new_bw_state =
21242a0d256SVille Syrjälä intel_atomic_get_new_bw_state(state);
21342a0d256SVille Syrjälä
21442a0d256SVille Syrjälä if (!new_bw_state)
21542a0d256SVille Syrjälä return;
21642a0d256SVille Syrjälä
21742a0d256SVille Syrjälä if (!intel_can_enable_sagv(i915, new_bw_state))
21842a0d256SVille Syrjälä skl_sagv_disable(i915);
21942a0d256SVille Syrjälä }
22042a0d256SVille Syrjälä
skl_sagv_post_plane_update(struct intel_atomic_state * state)22142a0d256SVille Syrjälä static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
22242a0d256SVille Syrjälä {
22342a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
22442a0d256SVille Syrjälä const struct intel_bw_state *new_bw_state =
22542a0d256SVille Syrjälä intel_atomic_get_new_bw_state(state);
22642a0d256SVille Syrjälä
22742a0d256SVille Syrjälä if (!new_bw_state)
22842a0d256SVille Syrjälä return;
22942a0d256SVille Syrjälä
23042a0d256SVille Syrjälä if (intel_can_enable_sagv(i915, new_bw_state))
23142a0d256SVille Syrjälä skl_sagv_enable(i915);
23242a0d256SVille Syrjälä }
23342a0d256SVille Syrjälä
icl_sagv_pre_plane_update(struct intel_atomic_state * state)23442a0d256SVille Syrjälä static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
23542a0d256SVille Syrjälä {
23642a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
23742a0d256SVille Syrjälä const struct intel_bw_state *old_bw_state =
23842a0d256SVille Syrjälä intel_atomic_get_old_bw_state(state);
23942a0d256SVille Syrjälä const struct intel_bw_state *new_bw_state =
24042a0d256SVille Syrjälä intel_atomic_get_new_bw_state(state);
24142a0d256SVille Syrjälä u16 old_mask, new_mask;
24242a0d256SVille Syrjälä
24342a0d256SVille Syrjälä if (!new_bw_state)
24442a0d256SVille Syrjälä return;
24542a0d256SVille Syrjälä
24642a0d256SVille Syrjälä old_mask = old_bw_state->qgv_points_mask;
24742a0d256SVille Syrjälä new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
24842a0d256SVille Syrjälä
24942a0d256SVille Syrjälä if (old_mask == new_mask)
25042a0d256SVille Syrjälä return;
25142a0d256SVille Syrjälä
25242a0d256SVille Syrjälä WARN_ON(!new_bw_state->base.changed);
25342a0d256SVille Syrjälä
25442a0d256SVille Syrjälä drm_dbg_kms(&i915->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
25542a0d256SVille Syrjälä old_mask, new_mask);
25642a0d256SVille Syrjälä
25742a0d256SVille Syrjälä /*
25842a0d256SVille Syrjälä * Restrict required qgv points before updating the configuration.
25942a0d256SVille Syrjälä * According to BSpec we can't mask and unmask qgv points at the same
26042a0d256SVille Syrjälä * time. Also masking should be done before updating the configuration
26142a0d256SVille Syrjälä * and unmasking afterwards.
26242a0d256SVille Syrjälä */
26342a0d256SVille Syrjälä icl_pcode_restrict_qgv_points(i915, new_mask);
26442a0d256SVille Syrjälä }
26542a0d256SVille Syrjälä
icl_sagv_post_plane_update(struct intel_atomic_state * state)26642a0d256SVille Syrjälä static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
26742a0d256SVille Syrjälä {
26842a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
26942a0d256SVille Syrjälä const struct intel_bw_state *old_bw_state =
27042a0d256SVille Syrjälä intel_atomic_get_old_bw_state(state);
27142a0d256SVille Syrjälä const struct intel_bw_state *new_bw_state =
27242a0d256SVille Syrjälä intel_atomic_get_new_bw_state(state);
27342a0d256SVille Syrjälä u16 old_mask, new_mask;
27442a0d256SVille Syrjälä
27542a0d256SVille Syrjälä if (!new_bw_state)
27642a0d256SVille Syrjälä return;
27742a0d256SVille Syrjälä
27842a0d256SVille Syrjälä old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
27942a0d256SVille Syrjälä new_mask = new_bw_state->qgv_points_mask;
28042a0d256SVille Syrjälä
28142a0d256SVille Syrjälä if (old_mask == new_mask)
28242a0d256SVille Syrjälä return;
28342a0d256SVille Syrjälä
28442a0d256SVille Syrjälä WARN_ON(!new_bw_state->base.changed);
28542a0d256SVille Syrjälä
28642a0d256SVille Syrjälä drm_dbg_kms(&i915->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
28742a0d256SVille Syrjälä old_mask, new_mask);
28842a0d256SVille Syrjälä
28942a0d256SVille Syrjälä /*
29042a0d256SVille Syrjälä * Allow required qgv points after updating the configuration.
29142a0d256SVille Syrjälä * According to BSpec we can't mask and unmask qgv points at the same
29242a0d256SVille Syrjälä * time. Also masking should be done before updating the configuration
29342a0d256SVille Syrjälä * and unmasking afterwards.
29442a0d256SVille Syrjälä */
29542a0d256SVille Syrjälä icl_pcode_restrict_qgv_points(i915, new_mask);
29642a0d256SVille Syrjälä }
29742a0d256SVille Syrjälä
intel_sagv_pre_plane_update(struct intel_atomic_state * state)29842a0d256SVille Syrjälä void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
29942a0d256SVille Syrjälä {
30042a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
30142a0d256SVille Syrjälä
30242a0d256SVille Syrjälä /*
30342a0d256SVille Syrjälä * Just return if we can't control SAGV or don't have it.
30442a0d256SVille Syrjälä * This is different from situation when we have SAGV but just can't
30542a0d256SVille Syrjälä * afford it due to DBuf limitation - in case if SAGV is completely
30642a0d256SVille Syrjälä * disabled in a BIOS, we are not even allowed to send a PCode request,
30742a0d256SVille Syrjälä * as it will throw an error. So have to check it here.
30842a0d256SVille Syrjälä */
30942a0d256SVille Syrjälä if (!intel_has_sagv(i915))
31042a0d256SVille Syrjälä return;
31142a0d256SVille Syrjälä
31242a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 11)
31342a0d256SVille Syrjälä icl_sagv_pre_plane_update(state);
31442a0d256SVille Syrjälä else
31542a0d256SVille Syrjälä skl_sagv_pre_plane_update(state);
31642a0d256SVille Syrjälä }
31742a0d256SVille Syrjälä
intel_sagv_post_plane_update(struct intel_atomic_state * state)31842a0d256SVille Syrjälä void intel_sagv_post_plane_update(struct intel_atomic_state *state)
31942a0d256SVille Syrjälä {
32042a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
32142a0d256SVille Syrjälä
32242a0d256SVille Syrjälä /*
32342a0d256SVille Syrjälä * Just return if we can't control SAGV or don't have it.
32442a0d256SVille Syrjälä * This is different from situation when we have SAGV but just can't
32542a0d256SVille Syrjälä * afford it due to DBuf limitation - in case if SAGV is completely
32642a0d256SVille Syrjälä * disabled in a BIOS, we are not even allowed to send a PCode request,
32742a0d256SVille Syrjälä * as it will throw an error. So have to check it here.
32842a0d256SVille Syrjälä */
32942a0d256SVille Syrjälä if (!intel_has_sagv(i915))
33042a0d256SVille Syrjälä return;
33142a0d256SVille Syrjälä
33242a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 11)
33342a0d256SVille Syrjälä icl_sagv_post_plane_update(state);
33442a0d256SVille Syrjälä else
33542a0d256SVille Syrjälä skl_sagv_post_plane_update(state);
33642a0d256SVille Syrjälä }
33742a0d256SVille Syrjälä
skl_crtc_can_enable_sagv(const struct intel_crtc_state * crtc_state)33842a0d256SVille Syrjälä static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
33942a0d256SVille Syrjälä {
34042a0d256SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
34142a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
34242a0d256SVille Syrjälä enum plane_id plane_id;
34342a0d256SVille Syrjälä int max_level = INT_MAX;
34442a0d256SVille Syrjälä
34542a0d256SVille Syrjälä if (!intel_has_sagv(i915))
34642a0d256SVille Syrjälä return false;
34742a0d256SVille Syrjälä
34842a0d256SVille Syrjälä if (!crtc_state->hw.active)
34942a0d256SVille Syrjälä return true;
35042a0d256SVille Syrjälä
35142a0d256SVille Syrjälä if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
35242a0d256SVille Syrjälä return false;
35342a0d256SVille Syrjälä
35442a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
35542a0d256SVille Syrjälä const struct skl_plane_wm *wm =
35642a0d256SVille Syrjälä &crtc_state->wm.skl.optimal.planes[plane_id];
35742a0d256SVille Syrjälä int level;
35842a0d256SVille Syrjälä
35942a0d256SVille Syrjälä /* Skip this plane if it's not enabled */
36042a0d256SVille Syrjälä if (!wm->wm[0].enable)
36142a0d256SVille Syrjälä continue;
36242a0d256SVille Syrjälä
36342a0d256SVille Syrjälä /* Find the highest enabled wm level for this plane */
3647ee6f99dSVille Syrjälä for (level = i915->display.wm.num_levels - 1;
36542a0d256SVille Syrjälä !wm->wm[level].enable; --level)
36642a0d256SVille Syrjälä { }
36742a0d256SVille Syrjälä
36842a0d256SVille Syrjälä /* Highest common enabled wm level for all planes */
36942a0d256SVille Syrjälä max_level = min(level, max_level);
37042a0d256SVille Syrjälä }
37142a0d256SVille Syrjälä
37242a0d256SVille Syrjälä /* No enabled planes? */
37342a0d256SVille Syrjälä if (max_level == INT_MAX)
37442a0d256SVille Syrjälä return true;
37542a0d256SVille Syrjälä
37642a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
37742a0d256SVille Syrjälä const struct skl_plane_wm *wm =
37842a0d256SVille Syrjälä &crtc_state->wm.skl.optimal.planes[plane_id];
37942a0d256SVille Syrjälä
38042a0d256SVille Syrjälä /*
38142a0d256SVille Syrjälä * All enabled planes must have enabled a common wm level that
38242a0d256SVille Syrjälä * can tolerate memory latencies higher than sagv_block_time_us
38342a0d256SVille Syrjälä */
38442a0d256SVille Syrjälä if (wm->wm[0].enable && !wm->wm[max_level].can_sagv)
38542a0d256SVille Syrjälä return false;
38642a0d256SVille Syrjälä }
38742a0d256SVille Syrjälä
38842a0d256SVille Syrjälä return true;
38942a0d256SVille Syrjälä }
39042a0d256SVille Syrjälä
tgl_crtc_can_enable_sagv(const struct intel_crtc_state * crtc_state)39142a0d256SVille Syrjälä static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
39242a0d256SVille Syrjälä {
39342a0d256SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
39442a0d256SVille Syrjälä enum plane_id plane_id;
39542a0d256SVille Syrjälä
39642a0d256SVille Syrjälä if (!crtc_state->hw.active)
39742a0d256SVille Syrjälä return true;
39842a0d256SVille Syrjälä
39942a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
40042a0d256SVille Syrjälä const struct skl_plane_wm *wm =
40142a0d256SVille Syrjälä &crtc_state->wm.skl.optimal.planes[plane_id];
40242a0d256SVille Syrjälä
40342a0d256SVille Syrjälä if (wm->wm[0].enable && !wm->sagv.wm0.enable)
40442a0d256SVille Syrjälä return false;
40542a0d256SVille Syrjälä }
40642a0d256SVille Syrjälä
40742a0d256SVille Syrjälä return true;
40842a0d256SVille Syrjälä }
40942a0d256SVille Syrjälä
intel_crtc_can_enable_sagv(const struct intel_crtc_state * crtc_state)41042a0d256SVille Syrjälä static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
41142a0d256SVille Syrjälä {
41242a0d256SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
41342a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
41442a0d256SVille Syrjälä
415419e505dSVille Syrjälä if (!i915->params.enable_sagv)
416419e505dSVille Syrjälä return false;
417419e505dSVille Syrjälä
41842a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 12)
41942a0d256SVille Syrjälä return tgl_crtc_can_enable_sagv(crtc_state);
42042a0d256SVille Syrjälä else
42142a0d256SVille Syrjälä return skl_crtc_can_enable_sagv(crtc_state);
42242a0d256SVille Syrjälä }
42342a0d256SVille Syrjälä
intel_can_enable_sagv(struct drm_i915_private * i915,const struct intel_bw_state * bw_state)42442a0d256SVille Syrjälä bool intel_can_enable_sagv(struct drm_i915_private *i915,
42542a0d256SVille Syrjälä const struct intel_bw_state *bw_state)
42642a0d256SVille Syrjälä {
42742a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 11 &&
42842a0d256SVille Syrjälä bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
42942a0d256SVille Syrjälä return false;
43042a0d256SVille Syrjälä
43142a0d256SVille Syrjälä return bw_state->pipe_sagv_reject == 0;
43242a0d256SVille Syrjälä }
43342a0d256SVille Syrjälä
intel_compute_sagv_mask(struct intel_atomic_state * state)43442a0d256SVille Syrjälä static int intel_compute_sagv_mask(struct intel_atomic_state *state)
43542a0d256SVille Syrjälä {
43642a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
43742a0d256SVille Syrjälä int ret;
43842a0d256SVille Syrjälä struct intel_crtc *crtc;
43942a0d256SVille Syrjälä struct intel_crtc_state *new_crtc_state;
44042a0d256SVille Syrjälä struct intel_bw_state *new_bw_state = NULL;
44142a0d256SVille Syrjälä const struct intel_bw_state *old_bw_state = NULL;
44242a0d256SVille Syrjälä int i;
44342a0d256SVille Syrjälä
44442a0d256SVille Syrjälä for_each_new_intel_crtc_in_state(state, crtc,
44542a0d256SVille Syrjälä new_crtc_state, i) {
44642a0d256SVille Syrjälä new_bw_state = intel_atomic_get_bw_state(state);
44742a0d256SVille Syrjälä if (IS_ERR(new_bw_state))
44842a0d256SVille Syrjälä return PTR_ERR(new_bw_state);
44942a0d256SVille Syrjälä
45042a0d256SVille Syrjälä old_bw_state = intel_atomic_get_old_bw_state(state);
45142a0d256SVille Syrjälä
45242a0d256SVille Syrjälä if (intel_crtc_can_enable_sagv(new_crtc_state))
45342a0d256SVille Syrjälä new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
45442a0d256SVille Syrjälä else
45542a0d256SVille Syrjälä new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
45642a0d256SVille Syrjälä }
45742a0d256SVille Syrjälä
45842a0d256SVille Syrjälä if (!new_bw_state)
45942a0d256SVille Syrjälä return 0;
46042a0d256SVille Syrjälä
46142a0d256SVille Syrjälä new_bw_state->active_pipes =
46242a0d256SVille Syrjälä intel_calc_active_pipes(state, old_bw_state->active_pipes);
46342a0d256SVille Syrjälä
46442a0d256SVille Syrjälä if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
46542a0d256SVille Syrjälä ret = intel_atomic_lock_global_state(&new_bw_state->base);
46642a0d256SVille Syrjälä if (ret)
46742a0d256SVille Syrjälä return ret;
46842a0d256SVille Syrjälä }
46942a0d256SVille Syrjälä
47042a0d256SVille Syrjälä if (intel_can_enable_sagv(i915, new_bw_state) !=
47142a0d256SVille Syrjälä intel_can_enable_sagv(i915, old_bw_state)) {
47242a0d256SVille Syrjälä ret = intel_atomic_serialize_global_state(&new_bw_state->base);
47342a0d256SVille Syrjälä if (ret)
47442a0d256SVille Syrjälä return ret;
47542a0d256SVille Syrjälä } else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
47642a0d256SVille Syrjälä ret = intel_atomic_lock_global_state(&new_bw_state->base);
47742a0d256SVille Syrjälä if (ret)
47842a0d256SVille Syrjälä return ret;
47942a0d256SVille Syrjälä }
48042a0d256SVille Syrjälä
48142a0d256SVille Syrjälä for_each_new_intel_crtc_in_state(state, crtc,
48242a0d256SVille Syrjälä new_crtc_state, i) {
48342a0d256SVille Syrjälä struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
48442a0d256SVille Syrjälä
48542a0d256SVille Syrjälä /*
48642a0d256SVille Syrjälä * We store use_sagv_wm in the crtc state rather than relying on
48742a0d256SVille Syrjälä * that bw state since we have no convenient way to get at the
48842a0d256SVille Syrjälä * latter from the plane commit hooks (especially in the legacy
48942a0d256SVille Syrjälä * cursor case)
49042a0d256SVille Syrjälä */
49142a0d256SVille Syrjälä pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(i915) &&
49242a0d256SVille Syrjälä DISPLAY_VER(i915) >= 12 &&
49342a0d256SVille Syrjälä intel_can_enable_sagv(i915, new_bw_state);
49442a0d256SVille Syrjälä }
49542a0d256SVille Syrjälä
49642a0d256SVille Syrjälä return 0;
49742a0d256SVille Syrjälä }
49842a0d256SVille Syrjälä
skl_ddb_entry_init(struct skl_ddb_entry * entry,u16 start,u16 end)49942a0d256SVille Syrjälä static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
50042a0d256SVille Syrjälä u16 start, u16 end)
50142a0d256SVille Syrjälä {
50242a0d256SVille Syrjälä entry->start = start;
50342a0d256SVille Syrjälä entry->end = end;
50442a0d256SVille Syrjälä
50542a0d256SVille Syrjälä return end;
50642a0d256SVille Syrjälä }
50742a0d256SVille Syrjälä
intel_dbuf_slice_size(struct drm_i915_private * i915)50842a0d256SVille Syrjälä static int intel_dbuf_slice_size(struct drm_i915_private *i915)
50942a0d256SVille Syrjälä {
5105af5169dSMatt Roper return DISPLAY_INFO(i915)->dbuf.size /
5115af5169dSMatt Roper hweight8(DISPLAY_INFO(i915)->dbuf.slice_mask);
51242a0d256SVille Syrjälä }
51342a0d256SVille Syrjälä
51442a0d256SVille Syrjälä static void
skl_ddb_entry_for_slices(struct drm_i915_private * i915,u8 slice_mask,struct skl_ddb_entry * ddb)51542a0d256SVille Syrjälä skl_ddb_entry_for_slices(struct drm_i915_private *i915, u8 slice_mask,
51642a0d256SVille Syrjälä struct skl_ddb_entry *ddb)
51742a0d256SVille Syrjälä {
51842a0d256SVille Syrjälä int slice_size = intel_dbuf_slice_size(i915);
51942a0d256SVille Syrjälä
52042a0d256SVille Syrjälä if (!slice_mask) {
52142a0d256SVille Syrjälä ddb->start = 0;
52242a0d256SVille Syrjälä ddb->end = 0;
52342a0d256SVille Syrjälä return;
52442a0d256SVille Syrjälä }
52542a0d256SVille Syrjälä
52642a0d256SVille Syrjälä ddb->start = (ffs(slice_mask) - 1) * slice_size;
52742a0d256SVille Syrjälä ddb->end = fls(slice_mask) * slice_size;
52842a0d256SVille Syrjälä
52942a0d256SVille Syrjälä WARN_ON(ddb->start >= ddb->end);
5305af5169dSMatt Roper WARN_ON(ddb->end > DISPLAY_INFO(i915)->dbuf.size);
53142a0d256SVille Syrjälä }
53242a0d256SVille Syrjälä
mbus_ddb_offset(struct drm_i915_private * i915,u8 slice_mask)53342a0d256SVille Syrjälä static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
53442a0d256SVille Syrjälä {
53542a0d256SVille Syrjälä struct skl_ddb_entry ddb;
53642a0d256SVille Syrjälä
53742a0d256SVille Syrjälä if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))
53842a0d256SVille Syrjälä slice_mask = BIT(DBUF_S1);
53942a0d256SVille Syrjälä else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
54042a0d256SVille Syrjälä slice_mask = BIT(DBUF_S3);
54142a0d256SVille Syrjälä
54242a0d256SVille Syrjälä skl_ddb_entry_for_slices(i915, slice_mask, &ddb);
54342a0d256SVille Syrjälä
54442a0d256SVille Syrjälä return ddb.start;
54542a0d256SVille Syrjälä }
54642a0d256SVille Syrjälä
skl_ddb_dbuf_slice_mask(struct drm_i915_private * i915,const struct skl_ddb_entry * entry)54742a0d256SVille Syrjälä u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
54842a0d256SVille Syrjälä const struct skl_ddb_entry *entry)
54942a0d256SVille Syrjälä {
55042a0d256SVille Syrjälä int slice_size = intel_dbuf_slice_size(i915);
55142a0d256SVille Syrjälä enum dbuf_slice start_slice, end_slice;
55242a0d256SVille Syrjälä u8 slice_mask = 0;
55342a0d256SVille Syrjälä
55442a0d256SVille Syrjälä if (!skl_ddb_entry_size(entry))
55542a0d256SVille Syrjälä return 0;
55642a0d256SVille Syrjälä
55742a0d256SVille Syrjälä start_slice = entry->start / slice_size;
55842a0d256SVille Syrjälä end_slice = (entry->end - 1) / slice_size;
55942a0d256SVille Syrjälä
56042a0d256SVille Syrjälä /*
56142a0d256SVille Syrjälä * Per plane DDB entry can in a really worst case be on multiple slices
56242a0d256SVille Syrjälä * but single entry is anyway contigious.
56342a0d256SVille Syrjälä */
56442a0d256SVille Syrjälä while (start_slice <= end_slice) {
56542a0d256SVille Syrjälä slice_mask |= BIT(start_slice);
56642a0d256SVille Syrjälä start_slice++;
56742a0d256SVille Syrjälä }
56842a0d256SVille Syrjälä
56942a0d256SVille Syrjälä return slice_mask;
57042a0d256SVille Syrjälä }
57142a0d256SVille Syrjälä
intel_crtc_ddb_weight(const struct intel_crtc_state * crtc_state)57242a0d256SVille Syrjälä static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state)
57342a0d256SVille Syrjälä {
57442a0d256SVille Syrjälä const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
57542a0d256SVille Syrjälä int hdisplay, vdisplay;
57642a0d256SVille Syrjälä
57742a0d256SVille Syrjälä if (!crtc_state->hw.active)
57842a0d256SVille Syrjälä return 0;
57942a0d256SVille Syrjälä
58042a0d256SVille Syrjälä /*
58142a0d256SVille Syrjälä * Watermark/ddb requirement highly depends upon width of the
58242a0d256SVille Syrjälä * framebuffer, So instead of allocating DDB equally among pipes
58342a0d256SVille Syrjälä * distribute DDB based on resolution/width of the display.
58442a0d256SVille Syrjälä */
58542a0d256SVille Syrjälä drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
58642a0d256SVille Syrjälä
58742a0d256SVille Syrjälä return hdisplay;
58842a0d256SVille Syrjälä }
58942a0d256SVille Syrjälä
intel_crtc_dbuf_weights(const struct intel_dbuf_state * dbuf_state,enum pipe for_pipe,unsigned int * weight_start,unsigned int * weight_end,unsigned int * weight_total)59042a0d256SVille Syrjälä static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state,
59142a0d256SVille Syrjälä enum pipe for_pipe,
59242a0d256SVille Syrjälä unsigned int *weight_start,
59342a0d256SVille Syrjälä unsigned int *weight_end,
59442a0d256SVille Syrjälä unsigned int *weight_total)
59542a0d256SVille Syrjälä {
59642a0d256SVille Syrjälä struct drm_i915_private *i915 =
59742a0d256SVille Syrjälä to_i915(dbuf_state->base.state->base.dev);
59842a0d256SVille Syrjälä enum pipe pipe;
59942a0d256SVille Syrjälä
60042a0d256SVille Syrjälä *weight_start = 0;
60142a0d256SVille Syrjälä *weight_end = 0;
60242a0d256SVille Syrjälä *weight_total = 0;
60342a0d256SVille Syrjälä
60442a0d256SVille Syrjälä for_each_pipe(i915, pipe) {
60542a0d256SVille Syrjälä int weight = dbuf_state->weight[pipe];
60642a0d256SVille Syrjälä
60742a0d256SVille Syrjälä /*
60842a0d256SVille Syrjälä * Do not account pipes using other slice sets
60942a0d256SVille Syrjälä * luckily as of current BSpec slice sets do not partially
61042a0d256SVille Syrjälä * intersect(pipes share either same one slice or same slice set
61142a0d256SVille Syrjälä * i.e no partial intersection), so it is enough to check for
61242a0d256SVille Syrjälä * equality for now.
61342a0d256SVille Syrjälä */
61442a0d256SVille Syrjälä if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe])
61542a0d256SVille Syrjälä continue;
61642a0d256SVille Syrjälä
61742a0d256SVille Syrjälä *weight_total += weight;
61842a0d256SVille Syrjälä if (pipe < for_pipe) {
61942a0d256SVille Syrjälä *weight_start += weight;
62042a0d256SVille Syrjälä *weight_end += weight;
62142a0d256SVille Syrjälä } else if (pipe == for_pipe) {
62242a0d256SVille Syrjälä *weight_end += weight;
62342a0d256SVille Syrjälä }
62442a0d256SVille Syrjälä }
62542a0d256SVille Syrjälä }
62642a0d256SVille Syrjälä
62742a0d256SVille Syrjälä static int
skl_crtc_allocate_ddb(struct intel_atomic_state * state,struct intel_crtc * crtc)62842a0d256SVille Syrjälä skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
62942a0d256SVille Syrjälä {
63042a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
63142a0d256SVille Syrjälä unsigned int weight_total, weight_start, weight_end;
63242a0d256SVille Syrjälä const struct intel_dbuf_state *old_dbuf_state =
63342a0d256SVille Syrjälä intel_atomic_get_old_dbuf_state(state);
63442a0d256SVille Syrjälä struct intel_dbuf_state *new_dbuf_state =
63542a0d256SVille Syrjälä intel_atomic_get_new_dbuf_state(state);
63642a0d256SVille Syrjälä struct intel_crtc_state *crtc_state;
63742a0d256SVille Syrjälä struct skl_ddb_entry ddb_slices;
63842a0d256SVille Syrjälä enum pipe pipe = crtc->pipe;
63942a0d256SVille Syrjälä unsigned int mbus_offset = 0;
64042a0d256SVille Syrjälä u32 ddb_range_size;
64142a0d256SVille Syrjälä u32 dbuf_slice_mask;
64242a0d256SVille Syrjälä u32 start, end;
64342a0d256SVille Syrjälä int ret;
64442a0d256SVille Syrjälä
64542a0d256SVille Syrjälä if (new_dbuf_state->weight[pipe] == 0) {
64642a0d256SVille Syrjälä skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0);
64742a0d256SVille Syrjälä goto out;
64842a0d256SVille Syrjälä }
64942a0d256SVille Syrjälä
65042a0d256SVille Syrjälä dbuf_slice_mask = new_dbuf_state->slices[pipe];
65142a0d256SVille Syrjälä
65242a0d256SVille Syrjälä skl_ddb_entry_for_slices(i915, dbuf_slice_mask, &ddb_slices);
65342a0d256SVille Syrjälä mbus_offset = mbus_ddb_offset(i915, dbuf_slice_mask);
65442a0d256SVille Syrjälä ddb_range_size = skl_ddb_entry_size(&ddb_slices);
65542a0d256SVille Syrjälä
65642a0d256SVille Syrjälä intel_crtc_dbuf_weights(new_dbuf_state, pipe,
65742a0d256SVille Syrjälä &weight_start, &weight_end, &weight_total);
65842a0d256SVille Syrjälä
65942a0d256SVille Syrjälä start = ddb_range_size * weight_start / weight_total;
66042a0d256SVille Syrjälä end = ddb_range_size * weight_end / weight_total;
66142a0d256SVille Syrjälä
66242a0d256SVille Syrjälä skl_ddb_entry_init(&new_dbuf_state->ddb[pipe],
66342a0d256SVille Syrjälä ddb_slices.start - mbus_offset + start,
66442a0d256SVille Syrjälä ddb_slices.start - mbus_offset + end);
66542a0d256SVille Syrjälä
66642a0d256SVille Syrjälä out:
66742a0d256SVille Syrjälä if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
66842a0d256SVille Syrjälä skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
66942a0d256SVille Syrjälä &new_dbuf_state->ddb[pipe]))
67042a0d256SVille Syrjälä return 0;
67142a0d256SVille Syrjälä
67242a0d256SVille Syrjälä ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
67342a0d256SVille Syrjälä if (ret)
67442a0d256SVille Syrjälä return ret;
67542a0d256SVille Syrjälä
67642a0d256SVille Syrjälä crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
67742a0d256SVille Syrjälä if (IS_ERR(crtc_state))
67842a0d256SVille Syrjälä return PTR_ERR(crtc_state);
67942a0d256SVille Syrjälä
68042a0d256SVille Syrjälä /*
68142a0d256SVille Syrjälä * Used for checking overlaps, so we need absolute
68242a0d256SVille Syrjälä * offsets instead of MBUS relative offsets.
68342a0d256SVille Syrjälä */
68442a0d256SVille Syrjälä crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;
68542a0d256SVille Syrjälä crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;
68642a0d256SVille Syrjälä
68742a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
68842a0d256SVille Syrjälä "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n",
68942a0d256SVille Syrjälä crtc->base.base.id, crtc->base.name,
69042a0d256SVille Syrjälä old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe],
69142a0d256SVille Syrjälä old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end,
69242a0d256SVille Syrjälä new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end,
69342a0d256SVille Syrjälä old_dbuf_state->active_pipes, new_dbuf_state->active_pipes);
69442a0d256SVille Syrjälä
69542a0d256SVille Syrjälä return 0;
69642a0d256SVille Syrjälä }
69742a0d256SVille Syrjälä
69842a0d256SVille Syrjälä static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
69942a0d256SVille Syrjälä int width, const struct drm_format_info *format,
70042a0d256SVille Syrjälä u64 modifier, unsigned int rotation,
70142a0d256SVille Syrjälä u32 plane_pixel_rate, struct skl_wm_params *wp,
70242a0d256SVille Syrjälä int color_plane);
70342a0d256SVille Syrjälä
70442a0d256SVille Syrjälä static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
70542a0d256SVille Syrjälä struct intel_plane *plane,
70642a0d256SVille Syrjälä int level,
70742a0d256SVille Syrjälä unsigned int latency,
70842a0d256SVille Syrjälä const struct skl_wm_params *wp,
70942a0d256SVille Syrjälä const struct skl_wm_level *result_prev,
71042a0d256SVille Syrjälä struct skl_wm_level *result /* out */);
71142a0d256SVille Syrjälä
skl_wm_latency(struct drm_i915_private * i915,int level,const struct skl_wm_params * wp)7126b931346SVille Syrjälä static unsigned int skl_wm_latency(struct drm_i915_private *i915, int level,
7136b931346SVille Syrjälä const struct skl_wm_params *wp)
7146b931346SVille Syrjälä {
7156b931346SVille Syrjälä unsigned int latency = i915->display.wm.skl_latency[level];
7166b931346SVille Syrjälä
7176b931346SVille Syrjälä if (latency == 0)
7186b931346SVille Syrjälä return 0;
7196b931346SVille Syrjälä
7206b931346SVille Syrjälä /*
7216b931346SVille Syrjälä * WaIncreaseLatencyIPCEnabled: kbl,cfl
7226b931346SVille Syrjälä * Display WA #1141: kbl,cfl
7236b931346SVille Syrjälä */
7246b931346SVille Syrjälä if ((IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) &&
7256b931346SVille Syrjälä skl_watermark_ipc_enabled(i915))
7266b931346SVille Syrjälä latency += 4;
7276b931346SVille Syrjälä
728636f973cSVille Syrjälä if (skl_needs_memory_bw_wa(i915) && wp && wp->x_tiled)
7296b931346SVille Syrjälä latency += 15;
7306b931346SVille Syrjälä
7316b931346SVille Syrjälä return latency;
7326b931346SVille Syrjälä }
7336b931346SVille Syrjälä
73442a0d256SVille Syrjälä static unsigned int
skl_cursor_allocation(const struct intel_crtc_state * crtc_state,int num_active)73542a0d256SVille Syrjälä skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
73642a0d256SVille Syrjälä int num_active)
73742a0d256SVille Syrjälä {
73842a0d256SVille Syrjälä struct intel_plane *plane = to_intel_plane(crtc_state->uapi.crtc->cursor);
73942a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
74042a0d256SVille Syrjälä struct skl_wm_level wm = {};
74142a0d256SVille Syrjälä int ret, min_ddb_alloc = 0;
74242a0d256SVille Syrjälä struct skl_wm_params wp;
7437ee6f99dSVille Syrjälä int level;
74442a0d256SVille Syrjälä
74542a0d256SVille Syrjälä ret = skl_compute_wm_params(crtc_state, 256,
74642a0d256SVille Syrjälä drm_format_info(DRM_FORMAT_ARGB8888),
74742a0d256SVille Syrjälä DRM_FORMAT_MOD_LINEAR,
74842a0d256SVille Syrjälä DRM_MODE_ROTATE_0,
74942a0d256SVille Syrjälä crtc_state->pixel_rate, &wp, 0);
75042a0d256SVille Syrjälä drm_WARN_ON(&i915->drm, ret);
75142a0d256SVille Syrjälä
7527ee6f99dSVille Syrjälä for (level = 0; level < i915->display.wm.num_levels; level++) {
7536b931346SVille Syrjälä unsigned int latency = skl_wm_latency(i915, level, &wp);
75442a0d256SVille Syrjälä
75542a0d256SVille Syrjälä skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
75642a0d256SVille Syrjälä if (wm.min_ddb_alloc == U16_MAX)
75742a0d256SVille Syrjälä break;
75842a0d256SVille Syrjälä
75942a0d256SVille Syrjälä min_ddb_alloc = wm.min_ddb_alloc;
76042a0d256SVille Syrjälä }
76142a0d256SVille Syrjälä
76242a0d256SVille Syrjälä return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
76342a0d256SVille Syrjälä }
76442a0d256SVille Syrjälä
skl_ddb_entry_init_from_hw(struct skl_ddb_entry * entry,u32 reg)76542a0d256SVille Syrjälä static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
76642a0d256SVille Syrjälä {
76742a0d256SVille Syrjälä skl_ddb_entry_init(entry,
76842a0d256SVille Syrjälä REG_FIELD_GET(PLANE_BUF_START_MASK, reg),
76942a0d256SVille Syrjälä REG_FIELD_GET(PLANE_BUF_END_MASK, reg));
77042a0d256SVille Syrjälä if (entry->end)
77142a0d256SVille Syrjälä entry->end++;
77242a0d256SVille Syrjälä }
77342a0d256SVille Syrjälä
77442a0d256SVille Syrjälä static void
skl_ddb_get_hw_plane_state(struct drm_i915_private * i915,const enum pipe pipe,const enum plane_id plane_id,struct skl_ddb_entry * ddb,struct skl_ddb_entry * ddb_y)77542a0d256SVille Syrjälä skl_ddb_get_hw_plane_state(struct drm_i915_private *i915,
77642a0d256SVille Syrjälä const enum pipe pipe,
77742a0d256SVille Syrjälä const enum plane_id plane_id,
77842a0d256SVille Syrjälä struct skl_ddb_entry *ddb,
77942a0d256SVille Syrjälä struct skl_ddb_entry *ddb_y)
78042a0d256SVille Syrjälä {
78142a0d256SVille Syrjälä u32 val;
78242a0d256SVille Syrjälä
78342a0d256SVille Syrjälä /* Cursor doesn't support NV12/planar, so no extra calculation needed */
78442a0d256SVille Syrjälä if (plane_id == PLANE_CURSOR) {
78500136429SJani Nikula val = intel_de_read(i915, CUR_BUF_CFG(pipe));
78642a0d256SVille Syrjälä skl_ddb_entry_init_from_hw(ddb, val);
78742a0d256SVille Syrjälä return;
78842a0d256SVille Syrjälä }
78942a0d256SVille Syrjälä
79000136429SJani Nikula val = intel_de_read(i915, PLANE_BUF_CFG(pipe, plane_id));
79142a0d256SVille Syrjälä skl_ddb_entry_init_from_hw(ddb, val);
79242a0d256SVille Syrjälä
79342a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 11)
79442a0d256SVille Syrjälä return;
79542a0d256SVille Syrjälä
79600136429SJani Nikula val = intel_de_read(i915, PLANE_NV12_BUF_CFG(pipe, plane_id));
79742a0d256SVille Syrjälä skl_ddb_entry_init_from_hw(ddb_y, val);
79842a0d256SVille Syrjälä }
79942a0d256SVille Syrjälä
skl_pipe_ddb_get_hw_state(struct intel_crtc * crtc,struct skl_ddb_entry * ddb,struct skl_ddb_entry * ddb_y)80042a0d256SVille Syrjälä static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
80142a0d256SVille Syrjälä struct skl_ddb_entry *ddb,
80242a0d256SVille Syrjälä struct skl_ddb_entry *ddb_y)
80342a0d256SVille Syrjälä {
80442a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
80542a0d256SVille Syrjälä enum intel_display_power_domain power_domain;
80642a0d256SVille Syrjälä enum pipe pipe = crtc->pipe;
80742a0d256SVille Syrjälä intel_wakeref_t wakeref;
80842a0d256SVille Syrjälä enum plane_id plane_id;
80942a0d256SVille Syrjälä
81042a0d256SVille Syrjälä power_domain = POWER_DOMAIN_PIPE(pipe);
81142a0d256SVille Syrjälä wakeref = intel_display_power_get_if_enabled(i915, power_domain);
81242a0d256SVille Syrjälä if (!wakeref)
81342a0d256SVille Syrjälä return;
81442a0d256SVille Syrjälä
81542a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id)
81642a0d256SVille Syrjälä skl_ddb_get_hw_plane_state(i915, pipe,
81742a0d256SVille Syrjälä plane_id,
81842a0d256SVille Syrjälä &ddb[plane_id],
81942a0d256SVille Syrjälä &ddb_y[plane_id]);
82042a0d256SVille Syrjälä
82142a0d256SVille Syrjälä intel_display_power_put(i915, power_domain, wakeref);
82242a0d256SVille Syrjälä }
82342a0d256SVille Syrjälä
82442a0d256SVille Syrjälä struct dbuf_slice_conf_entry {
82542a0d256SVille Syrjälä u8 active_pipes;
82642a0d256SVille Syrjälä u8 dbuf_mask[I915_MAX_PIPES];
82742a0d256SVille Syrjälä bool join_mbus;
82842a0d256SVille Syrjälä };
82942a0d256SVille Syrjälä
83042a0d256SVille Syrjälä /*
83142a0d256SVille Syrjälä * Table taken from Bspec 12716
83242a0d256SVille Syrjälä * Pipes do have some preferred DBuf slice affinity,
83342a0d256SVille Syrjälä * plus there are some hardcoded requirements on how
83442a0d256SVille Syrjälä * those should be distributed for multipipe scenarios.
83542a0d256SVille Syrjälä * For more DBuf slices algorithm can get even more messy
83642a0d256SVille Syrjälä * and less readable, so decided to use a table almost
83742a0d256SVille Syrjälä * as is from BSpec itself - that way it is at least easier
83842a0d256SVille Syrjälä * to compare, change and check.
83942a0d256SVille Syrjälä */
84042a0d256SVille Syrjälä static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] =
84142a0d256SVille Syrjälä /* Autogenerated with igt/tools/intel_dbuf_map tool: */
84242a0d256SVille Syrjälä {
84342a0d256SVille Syrjälä {
84442a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A),
84542a0d256SVille Syrjälä .dbuf_mask = {
84642a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
84742a0d256SVille Syrjälä },
84842a0d256SVille Syrjälä },
84942a0d256SVille Syrjälä {
85042a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B),
85142a0d256SVille Syrjälä .dbuf_mask = {
85242a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
85342a0d256SVille Syrjälä },
85442a0d256SVille Syrjälä },
85542a0d256SVille Syrjälä {
85642a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
85742a0d256SVille Syrjälä .dbuf_mask = {
85842a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
85942a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S2),
86042a0d256SVille Syrjälä },
86142a0d256SVille Syrjälä },
86242a0d256SVille Syrjälä {
86342a0d256SVille Syrjälä .active_pipes = BIT(PIPE_C),
86442a0d256SVille Syrjälä .dbuf_mask = {
86542a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
86642a0d256SVille Syrjälä },
86742a0d256SVille Syrjälä },
86842a0d256SVille Syrjälä {
86942a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
87042a0d256SVille Syrjälä .dbuf_mask = {
87142a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
87242a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
87342a0d256SVille Syrjälä },
87442a0d256SVille Syrjälä },
87542a0d256SVille Syrjälä {
87642a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
87742a0d256SVille Syrjälä .dbuf_mask = {
87842a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
87942a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
88042a0d256SVille Syrjälä },
88142a0d256SVille Syrjälä },
88242a0d256SVille Syrjälä {
88342a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
88442a0d256SVille Syrjälä .dbuf_mask = {
88542a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
88642a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
88742a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
88842a0d256SVille Syrjälä },
88942a0d256SVille Syrjälä },
89042a0d256SVille Syrjälä {}
89142a0d256SVille Syrjälä };
89242a0d256SVille Syrjälä
89342a0d256SVille Syrjälä /*
89442a0d256SVille Syrjälä * Table taken from Bspec 49255
89542a0d256SVille Syrjälä * Pipes do have some preferred DBuf slice affinity,
89642a0d256SVille Syrjälä * plus there are some hardcoded requirements on how
89742a0d256SVille Syrjälä * those should be distributed for multipipe scenarios.
89842a0d256SVille Syrjälä * For more DBuf slices algorithm can get even more messy
89942a0d256SVille Syrjälä * and less readable, so decided to use a table almost
90042a0d256SVille Syrjälä * as is from BSpec itself - that way it is at least easier
90142a0d256SVille Syrjälä * to compare, change and check.
90242a0d256SVille Syrjälä */
90342a0d256SVille Syrjälä static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
90442a0d256SVille Syrjälä /* Autogenerated with igt/tools/intel_dbuf_map tool: */
90542a0d256SVille Syrjälä {
90642a0d256SVille Syrjälä {
90742a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A),
90842a0d256SVille Syrjälä .dbuf_mask = {
90942a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
91042a0d256SVille Syrjälä },
91142a0d256SVille Syrjälä },
91242a0d256SVille Syrjälä {
91342a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B),
91442a0d256SVille Syrjälä .dbuf_mask = {
91542a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
91642a0d256SVille Syrjälä },
91742a0d256SVille Syrjälä },
91842a0d256SVille Syrjälä {
91942a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
92042a0d256SVille Syrjälä .dbuf_mask = {
92142a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S2),
92242a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
92342a0d256SVille Syrjälä },
92442a0d256SVille Syrjälä },
92542a0d256SVille Syrjälä {
92642a0d256SVille Syrjälä .active_pipes = BIT(PIPE_C),
92742a0d256SVille Syrjälä .dbuf_mask = {
92842a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1),
92942a0d256SVille Syrjälä },
93042a0d256SVille Syrjälä },
93142a0d256SVille Syrjälä {
93242a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
93342a0d256SVille Syrjälä .dbuf_mask = {
93442a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
93542a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
93642a0d256SVille Syrjälä },
93742a0d256SVille Syrjälä },
93842a0d256SVille Syrjälä {
93942a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
94042a0d256SVille Syrjälä .dbuf_mask = {
94142a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
94242a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
94342a0d256SVille Syrjälä },
94442a0d256SVille Syrjälä },
94542a0d256SVille Syrjälä {
94642a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
94742a0d256SVille Syrjälä .dbuf_mask = {
94842a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
94942a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
95042a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
95142a0d256SVille Syrjälä },
95242a0d256SVille Syrjälä },
95342a0d256SVille Syrjälä {
95442a0d256SVille Syrjälä .active_pipes = BIT(PIPE_D),
95542a0d256SVille Syrjälä .dbuf_mask = {
95642a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1),
95742a0d256SVille Syrjälä },
95842a0d256SVille Syrjälä },
95942a0d256SVille Syrjälä {
96042a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
96142a0d256SVille Syrjälä .dbuf_mask = {
96242a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
96342a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S2),
96442a0d256SVille Syrjälä },
96542a0d256SVille Syrjälä },
96642a0d256SVille Syrjälä {
96742a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
96842a0d256SVille Syrjälä .dbuf_mask = {
96942a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
97042a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S2),
97142a0d256SVille Syrjälä },
97242a0d256SVille Syrjälä },
97342a0d256SVille Syrjälä {
97442a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
97542a0d256SVille Syrjälä .dbuf_mask = {
97642a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
97742a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
97842a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S2),
97942a0d256SVille Syrjälä },
98042a0d256SVille Syrjälä },
98142a0d256SVille Syrjälä {
98242a0d256SVille Syrjälä .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
98342a0d256SVille Syrjälä .dbuf_mask = {
98442a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S1),
98542a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S2),
98642a0d256SVille Syrjälä },
98742a0d256SVille Syrjälä },
98842a0d256SVille Syrjälä {
98942a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
99042a0d256SVille Syrjälä .dbuf_mask = {
99142a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
99242a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
99342a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S2),
99442a0d256SVille Syrjälä },
99542a0d256SVille Syrjälä },
99642a0d256SVille Syrjälä {
99742a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
99842a0d256SVille Syrjälä .dbuf_mask = {
99942a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
100042a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
100142a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S2),
100242a0d256SVille Syrjälä },
100342a0d256SVille Syrjälä },
100442a0d256SVille Syrjälä {
100542a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
100642a0d256SVille Syrjälä .dbuf_mask = {
100742a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
100842a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1),
100942a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S2),
101042a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S2),
101142a0d256SVille Syrjälä },
101242a0d256SVille Syrjälä },
101342a0d256SVille Syrjälä {}
101442a0d256SVille Syrjälä };
101542a0d256SVille Syrjälä
101642a0d256SVille Syrjälä static const struct dbuf_slice_conf_entry dg2_allowed_dbufs[] = {
101742a0d256SVille Syrjälä {
101842a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A),
101942a0d256SVille Syrjälä .dbuf_mask = {
102042a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
102142a0d256SVille Syrjälä },
102242a0d256SVille Syrjälä },
102342a0d256SVille Syrjälä {
102442a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B),
102542a0d256SVille Syrjälä .dbuf_mask = {
102642a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
102742a0d256SVille Syrjälä },
102842a0d256SVille Syrjälä },
102942a0d256SVille Syrjälä {
103042a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
103142a0d256SVille Syrjälä .dbuf_mask = {
103242a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
103342a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S2),
103442a0d256SVille Syrjälä },
103542a0d256SVille Syrjälä },
103642a0d256SVille Syrjälä {
103742a0d256SVille Syrjälä .active_pipes = BIT(PIPE_C),
103842a0d256SVille Syrjälä .dbuf_mask = {
103942a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
104042a0d256SVille Syrjälä },
104142a0d256SVille Syrjälä },
104242a0d256SVille Syrjälä {
104342a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
104442a0d256SVille Syrjälä .dbuf_mask = {
104542a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
104642a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
104742a0d256SVille Syrjälä },
104842a0d256SVille Syrjälä },
104942a0d256SVille Syrjälä {
105042a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
105142a0d256SVille Syrjälä .dbuf_mask = {
105242a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
105342a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
105442a0d256SVille Syrjälä },
105542a0d256SVille Syrjälä },
105642a0d256SVille Syrjälä {
105742a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
105842a0d256SVille Syrjälä .dbuf_mask = {
105942a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
106042a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S2),
106142a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
106242a0d256SVille Syrjälä },
106342a0d256SVille Syrjälä },
106442a0d256SVille Syrjälä {
106542a0d256SVille Syrjälä .active_pipes = BIT(PIPE_D),
106642a0d256SVille Syrjälä .dbuf_mask = {
106742a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
106842a0d256SVille Syrjälä },
106942a0d256SVille Syrjälä },
107042a0d256SVille Syrjälä {
107142a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
107242a0d256SVille Syrjälä .dbuf_mask = {
107342a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
107442a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
107542a0d256SVille Syrjälä },
107642a0d256SVille Syrjälä },
107742a0d256SVille Syrjälä {
107842a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
107942a0d256SVille Syrjälä .dbuf_mask = {
108042a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
108142a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
108242a0d256SVille Syrjälä },
108342a0d256SVille Syrjälä },
108442a0d256SVille Syrjälä {
108542a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
108642a0d256SVille Syrjälä .dbuf_mask = {
108742a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
108842a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S2),
108942a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S3) | BIT(DBUF_S4),
109042a0d256SVille Syrjälä },
109142a0d256SVille Syrjälä },
109242a0d256SVille Syrjälä {
109342a0d256SVille Syrjälä .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
109442a0d256SVille Syrjälä .dbuf_mask = {
109542a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3),
109642a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S4),
109742a0d256SVille Syrjälä },
109842a0d256SVille Syrjälä },
109942a0d256SVille Syrjälä {
110042a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
110142a0d256SVille Syrjälä .dbuf_mask = {
110242a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
110342a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3),
110442a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S4),
110542a0d256SVille Syrjälä },
110642a0d256SVille Syrjälä },
110742a0d256SVille Syrjälä {
110842a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
110942a0d256SVille Syrjälä .dbuf_mask = {
111042a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
111142a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3),
111242a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S4),
111342a0d256SVille Syrjälä },
111442a0d256SVille Syrjälä },
111542a0d256SVille Syrjälä {
111642a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
111742a0d256SVille Syrjälä .dbuf_mask = {
111842a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1),
111942a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S2),
112042a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3),
112142a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S4),
112242a0d256SVille Syrjälä },
112342a0d256SVille Syrjälä },
112442a0d256SVille Syrjälä {}
112542a0d256SVille Syrjälä };
112642a0d256SVille Syrjälä
112742a0d256SVille Syrjälä static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
112842a0d256SVille Syrjälä /*
112942a0d256SVille Syrjälä * Keep the join_mbus cases first so check_mbus_joined()
113042a0d256SVille Syrjälä * will prefer them over the !join_mbus cases.
113142a0d256SVille Syrjälä */
113242a0d256SVille Syrjälä {
113342a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A),
113442a0d256SVille Syrjälä .dbuf_mask = {
113542a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
113642a0d256SVille Syrjälä },
113742a0d256SVille Syrjälä .join_mbus = true,
113842a0d256SVille Syrjälä },
113942a0d256SVille Syrjälä {
114042a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B),
114142a0d256SVille Syrjälä .dbuf_mask = {
114242a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
114342a0d256SVille Syrjälä },
114442a0d256SVille Syrjälä .join_mbus = true,
114542a0d256SVille Syrjälä },
114642a0d256SVille Syrjälä {
114742a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A),
114842a0d256SVille Syrjälä .dbuf_mask = {
114942a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
115042a0d256SVille Syrjälä },
115142a0d256SVille Syrjälä .join_mbus = false,
115242a0d256SVille Syrjälä },
115342a0d256SVille Syrjälä {
115442a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B),
115542a0d256SVille Syrjälä .dbuf_mask = {
115642a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
115742a0d256SVille Syrjälä },
115842a0d256SVille Syrjälä .join_mbus = false,
115942a0d256SVille Syrjälä },
116042a0d256SVille Syrjälä {
116142a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
116242a0d256SVille Syrjälä .dbuf_mask = {
116342a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
116442a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
116542a0d256SVille Syrjälä },
116642a0d256SVille Syrjälä },
116742a0d256SVille Syrjälä {
116842a0d256SVille Syrjälä .active_pipes = BIT(PIPE_C),
116942a0d256SVille Syrjälä .dbuf_mask = {
117042a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
117142a0d256SVille Syrjälä },
117242a0d256SVille Syrjälä },
117342a0d256SVille Syrjälä {
117442a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
117542a0d256SVille Syrjälä .dbuf_mask = {
117642a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
117742a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
117842a0d256SVille Syrjälä },
117942a0d256SVille Syrjälä },
118042a0d256SVille Syrjälä {
118142a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
118242a0d256SVille Syrjälä .dbuf_mask = {
118342a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
118442a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
118542a0d256SVille Syrjälä },
118642a0d256SVille Syrjälä },
118742a0d256SVille Syrjälä {
118842a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
118942a0d256SVille Syrjälä .dbuf_mask = {
119042a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
119142a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
119242a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
119342a0d256SVille Syrjälä },
119442a0d256SVille Syrjälä },
119542a0d256SVille Syrjälä {
119642a0d256SVille Syrjälä .active_pipes = BIT(PIPE_D),
119742a0d256SVille Syrjälä .dbuf_mask = {
119842a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
119942a0d256SVille Syrjälä },
120042a0d256SVille Syrjälä },
120142a0d256SVille Syrjälä {
120242a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
120342a0d256SVille Syrjälä .dbuf_mask = {
120442a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
120542a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
120642a0d256SVille Syrjälä },
120742a0d256SVille Syrjälä },
120842a0d256SVille Syrjälä {
120942a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
121042a0d256SVille Syrjälä .dbuf_mask = {
121142a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
121242a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
121342a0d256SVille Syrjälä },
121442a0d256SVille Syrjälä },
121542a0d256SVille Syrjälä {
121642a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
121742a0d256SVille Syrjälä .dbuf_mask = {
121842a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
121942a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
122042a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
122142a0d256SVille Syrjälä },
122242a0d256SVille Syrjälä },
122342a0d256SVille Syrjälä {
122442a0d256SVille Syrjälä .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
122542a0d256SVille Syrjälä .dbuf_mask = {
122642a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
122742a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
122842a0d256SVille Syrjälä },
122942a0d256SVille Syrjälä },
123042a0d256SVille Syrjälä {
123142a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
123242a0d256SVille Syrjälä .dbuf_mask = {
123342a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
123442a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
123542a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
123642a0d256SVille Syrjälä },
123742a0d256SVille Syrjälä },
123842a0d256SVille Syrjälä {
123942a0d256SVille Syrjälä .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
124042a0d256SVille Syrjälä .dbuf_mask = {
124142a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
124242a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
124342a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
124442a0d256SVille Syrjälä },
124542a0d256SVille Syrjälä },
124642a0d256SVille Syrjälä {
124742a0d256SVille Syrjälä .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
124842a0d256SVille Syrjälä .dbuf_mask = {
124942a0d256SVille Syrjälä [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
125042a0d256SVille Syrjälä [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
125142a0d256SVille Syrjälä [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
125242a0d256SVille Syrjälä [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
125342a0d256SVille Syrjälä },
125442a0d256SVille Syrjälä },
125542a0d256SVille Syrjälä {}
125642a0d256SVille Syrjälä
125742a0d256SVille Syrjälä };
125842a0d256SVille Syrjälä
check_mbus_joined(u8 active_pipes,const struct dbuf_slice_conf_entry * dbuf_slices)125942a0d256SVille Syrjälä static bool check_mbus_joined(u8 active_pipes,
126042a0d256SVille Syrjälä const struct dbuf_slice_conf_entry *dbuf_slices)
126142a0d256SVille Syrjälä {
126242a0d256SVille Syrjälä int i;
126342a0d256SVille Syrjälä
126442a0d256SVille Syrjälä for (i = 0; dbuf_slices[i].active_pipes != 0; i++) {
126542a0d256SVille Syrjälä if (dbuf_slices[i].active_pipes == active_pipes)
126642a0d256SVille Syrjälä return dbuf_slices[i].join_mbus;
126742a0d256SVille Syrjälä }
126842a0d256SVille Syrjälä return false;
126942a0d256SVille Syrjälä }
127042a0d256SVille Syrjälä
adlp_check_mbus_joined(u8 active_pipes)127142a0d256SVille Syrjälä static bool adlp_check_mbus_joined(u8 active_pipes)
127242a0d256SVille Syrjälä {
127342a0d256SVille Syrjälä return check_mbus_joined(active_pipes, adlp_allowed_dbufs);
127442a0d256SVille Syrjälä }
127542a0d256SVille Syrjälä
compute_dbuf_slices(enum pipe pipe,u8 active_pipes,bool join_mbus,const struct dbuf_slice_conf_entry * dbuf_slices)127642a0d256SVille Syrjälä static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus,
127742a0d256SVille Syrjälä const struct dbuf_slice_conf_entry *dbuf_slices)
127842a0d256SVille Syrjälä {
127942a0d256SVille Syrjälä int i;
128042a0d256SVille Syrjälä
128142a0d256SVille Syrjälä for (i = 0; dbuf_slices[i].active_pipes != 0; i++) {
128242a0d256SVille Syrjälä if (dbuf_slices[i].active_pipes == active_pipes &&
128342a0d256SVille Syrjälä dbuf_slices[i].join_mbus == join_mbus)
128442a0d256SVille Syrjälä return dbuf_slices[i].dbuf_mask[pipe];
128542a0d256SVille Syrjälä }
128642a0d256SVille Syrjälä return 0;
128742a0d256SVille Syrjälä }
128842a0d256SVille Syrjälä
128942a0d256SVille Syrjälä /*
129042a0d256SVille Syrjälä * This function finds an entry with same enabled pipe configuration and
129142a0d256SVille Syrjälä * returns correspondent DBuf slice mask as stated in BSpec for particular
129242a0d256SVille Syrjälä * platform.
129342a0d256SVille Syrjälä */
icl_compute_dbuf_slices(enum pipe pipe,u8 active_pipes,bool join_mbus)129442a0d256SVille Syrjälä static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
129542a0d256SVille Syrjälä {
129642a0d256SVille Syrjälä /*
129742a0d256SVille Syrjälä * FIXME: For ICL this is still a bit unclear as prev BSpec revision
129842a0d256SVille Syrjälä * required calculating "pipe ratio" in order to determine
129942a0d256SVille Syrjälä * if one or two slices can be used for single pipe configurations
130042a0d256SVille Syrjälä * as additional constraint to the existing table.
130142a0d256SVille Syrjälä * However based on recent info, it should be not "pipe ratio"
130242a0d256SVille Syrjälä * but rather ratio between pixel_rate and cdclk with additional
130342a0d256SVille Syrjälä * constants, so for now we are using only table until this is
130442a0d256SVille Syrjälä * clarified. Also this is the reason why crtc_state param is
130542a0d256SVille Syrjälä * still here - we will need it once those additional constraints
130642a0d256SVille Syrjälä * pop up.
130742a0d256SVille Syrjälä */
130842a0d256SVille Syrjälä return compute_dbuf_slices(pipe, active_pipes, join_mbus,
130942a0d256SVille Syrjälä icl_allowed_dbufs);
131042a0d256SVille Syrjälä }
131142a0d256SVille Syrjälä
tgl_compute_dbuf_slices(enum pipe pipe,u8 active_pipes,bool join_mbus)131242a0d256SVille Syrjälä static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
131342a0d256SVille Syrjälä {
131442a0d256SVille Syrjälä return compute_dbuf_slices(pipe, active_pipes, join_mbus,
131542a0d256SVille Syrjälä tgl_allowed_dbufs);
131642a0d256SVille Syrjälä }
131742a0d256SVille Syrjälä
adlp_compute_dbuf_slices(enum pipe pipe,u8 active_pipes,bool join_mbus)131842a0d256SVille Syrjälä static u8 adlp_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
131942a0d256SVille Syrjälä {
132042a0d256SVille Syrjälä return compute_dbuf_slices(pipe, active_pipes, join_mbus,
132142a0d256SVille Syrjälä adlp_allowed_dbufs);
132242a0d256SVille Syrjälä }
132342a0d256SVille Syrjälä
dg2_compute_dbuf_slices(enum pipe pipe,u8 active_pipes,bool join_mbus)132442a0d256SVille Syrjälä static u8 dg2_compute_dbuf_slices(enum pipe pipe, u8 active_pipes, bool join_mbus)
132542a0d256SVille Syrjälä {
132642a0d256SVille Syrjälä return compute_dbuf_slices(pipe, active_pipes, join_mbus,
132742a0d256SVille Syrjälä dg2_allowed_dbufs);
132842a0d256SVille Syrjälä }
132942a0d256SVille Syrjälä
skl_compute_dbuf_slices(struct intel_crtc * crtc,u8 active_pipes,bool join_mbus)133042a0d256SVille Syrjälä static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool join_mbus)
133142a0d256SVille Syrjälä {
133242a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
133342a0d256SVille Syrjälä enum pipe pipe = crtc->pipe;
133442a0d256SVille Syrjälä
133542a0d256SVille Syrjälä if (IS_DG2(i915))
133642a0d256SVille Syrjälä return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus);
133742a0d256SVille Syrjälä else if (DISPLAY_VER(i915) >= 13)
133842a0d256SVille Syrjälä return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus);
133942a0d256SVille Syrjälä else if (DISPLAY_VER(i915) == 12)
134042a0d256SVille Syrjälä return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus);
134142a0d256SVille Syrjälä else if (DISPLAY_VER(i915) == 11)
134242a0d256SVille Syrjälä return icl_compute_dbuf_slices(pipe, active_pipes, join_mbus);
134342a0d256SVille Syrjälä /*
134442a0d256SVille Syrjälä * For anything else just return one slice yet.
134542a0d256SVille Syrjälä * Should be extended for other platforms.
134642a0d256SVille Syrjälä */
134742a0d256SVille Syrjälä return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
134842a0d256SVille Syrjälä }
134942a0d256SVille Syrjälä
135042a0d256SVille Syrjälä static bool
use_minimal_wm0_only(const struct intel_crtc_state * crtc_state,struct intel_plane * plane)135142a0d256SVille Syrjälä use_minimal_wm0_only(const struct intel_crtc_state *crtc_state,
135242a0d256SVille Syrjälä struct intel_plane *plane)
135342a0d256SVille Syrjälä {
135442a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(plane->base.dev);
135542a0d256SVille Syrjälä
135642a0d256SVille Syrjälä return DISPLAY_VER(i915) >= 13 &&
135742a0d256SVille Syrjälä crtc_state->uapi.async_flip &&
135842a0d256SVille Syrjälä plane->async_flip;
135942a0d256SVille Syrjälä }
136042a0d256SVille Syrjälä
136142a0d256SVille Syrjälä static u64
skl_total_relative_data_rate(const struct intel_crtc_state * crtc_state)136242a0d256SVille Syrjälä skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
136342a0d256SVille Syrjälä {
136442a0d256SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
136542a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
136642a0d256SVille Syrjälä enum plane_id plane_id;
136742a0d256SVille Syrjälä u64 data_rate = 0;
136842a0d256SVille Syrjälä
136942a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
137042a0d256SVille Syrjälä if (plane_id == PLANE_CURSOR)
137142a0d256SVille Syrjälä continue;
137242a0d256SVille Syrjälä
137342a0d256SVille Syrjälä data_rate += crtc_state->rel_data_rate[plane_id];
137442a0d256SVille Syrjälä
137542a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 11)
137642a0d256SVille Syrjälä data_rate += crtc_state->rel_data_rate_y[plane_id];
137742a0d256SVille Syrjälä }
137842a0d256SVille Syrjälä
137942a0d256SVille Syrjälä return data_rate;
138042a0d256SVille Syrjälä }
138142a0d256SVille Syrjälä
138242a0d256SVille Syrjälä static const struct skl_wm_level *
skl_plane_wm_level(const struct skl_pipe_wm * pipe_wm,enum plane_id plane_id,int level)138342a0d256SVille Syrjälä skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
138442a0d256SVille Syrjälä enum plane_id plane_id,
138542a0d256SVille Syrjälä int level)
138642a0d256SVille Syrjälä {
138742a0d256SVille Syrjälä const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
138842a0d256SVille Syrjälä
138942a0d256SVille Syrjälä if (level == 0 && pipe_wm->use_sagv_wm)
139042a0d256SVille Syrjälä return &wm->sagv.wm0;
139142a0d256SVille Syrjälä
139242a0d256SVille Syrjälä return &wm->wm[level];
139342a0d256SVille Syrjälä }
139442a0d256SVille Syrjälä
139542a0d256SVille Syrjälä static const struct skl_wm_level *
skl_plane_trans_wm(const struct skl_pipe_wm * pipe_wm,enum plane_id plane_id)139642a0d256SVille Syrjälä skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
139742a0d256SVille Syrjälä enum plane_id plane_id)
139842a0d256SVille Syrjälä {
139942a0d256SVille Syrjälä const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
140042a0d256SVille Syrjälä
140142a0d256SVille Syrjälä if (pipe_wm->use_sagv_wm)
140242a0d256SVille Syrjälä return &wm->sagv.trans_wm;
140342a0d256SVille Syrjälä
140442a0d256SVille Syrjälä return &wm->trans_wm;
140542a0d256SVille Syrjälä }
140642a0d256SVille Syrjälä
140742a0d256SVille Syrjälä /*
140842a0d256SVille Syrjälä * We only disable the watermarks for each plane if
140942a0d256SVille Syrjälä * they exceed the ddb allocation of said plane. This
141042a0d256SVille Syrjälä * is done so that we don't end up touching cursor
141142a0d256SVille Syrjälä * watermarks needlessly when some other plane reduces
141242a0d256SVille Syrjälä * our max possible watermark level.
141342a0d256SVille Syrjälä *
141442a0d256SVille Syrjälä * Bspec has this to say about the PLANE_WM enable bit:
141542a0d256SVille Syrjälä * "All the watermarks at this level for all enabled
141642a0d256SVille Syrjälä * planes must be enabled before the level will be used."
141742a0d256SVille Syrjälä * So this is actually safe to do.
141842a0d256SVille Syrjälä */
141942a0d256SVille Syrjälä static void
skl_check_wm_level(struct skl_wm_level * wm,const struct skl_ddb_entry * ddb)142042a0d256SVille Syrjälä skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)
142142a0d256SVille Syrjälä {
142242a0d256SVille Syrjälä if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb))
142342a0d256SVille Syrjälä memset(wm, 0, sizeof(*wm));
142442a0d256SVille Syrjälä }
142542a0d256SVille Syrjälä
142642a0d256SVille Syrjälä static void
skl_check_nv12_wm_level(struct skl_wm_level * wm,struct skl_wm_level * uv_wm,const struct skl_ddb_entry * ddb_y,const struct skl_ddb_entry * ddb)142742a0d256SVille Syrjälä skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
142842a0d256SVille Syrjälä const struct skl_ddb_entry *ddb_y, const struct skl_ddb_entry *ddb)
142942a0d256SVille Syrjälä {
143042a0d256SVille Syrjälä if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb_y) ||
143142a0d256SVille Syrjälä uv_wm->min_ddb_alloc > skl_ddb_entry_size(ddb)) {
143242a0d256SVille Syrjälä memset(wm, 0, sizeof(*wm));
143342a0d256SVille Syrjälä memset(uv_wm, 0, sizeof(*uv_wm));
143442a0d256SVille Syrjälä }
143542a0d256SVille Syrjälä }
143642a0d256SVille Syrjälä
skl_need_wm_copy_wa(struct drm_i915_private * i915,int level,const struct skl_plane_wm * wm)14379fcbae04SStanislav Lisovskiy static bool skl_need_wm_copy_wa(struct drm_i915_private *i915, int level,
14389fcbae04SStanislav Lisovskiy const struct skl_plane_wm *wm)
143942a0d256SVille Syrjälä {
144042a0d256SVille Syrjälä /*
144142a0d256SVille Syrjälä * Wa_1408961008:icl, ehl
144242a0d256SVille Syrjälä * Wa_14012656716:tgl, adl
14439fcbae04SStanislav Lisovskiy * Wa_14017887344:icl
14449fcbae04SStanislav Lisovskiy * Wa_14017868169:adl, tgl
14459fcbae04SStanislav Lisovskiy * Due to some power saving optimizations, different subsystems
14469fcbae04SStanislav Lisovskiy * like PSR, might still use even disabled wm level registers,
14479fcbae04SStanislav Lisovskiy * for "reference", so lets keep at least the values sane.
14489fcbae04SStanislav Lisovskiy * Considering amount of WA requiring us to do similar things, was
14499fcbae04SStanislav Lisovskiy * decided to simply do it for all of the platforms, as those wm
14509fcbae04SStanislav Lisovskiy * levels are disabled, this isn't going to do harm anyway.
145142a0d256SVille Syrjälä */
14529fcbae04SStanislav Lisovskiy return level > 0 && !wm->wm[level].enable;
145342a0d256SVille Syrjälä }
145442a0d256SVille Syrjälä
145542a0d256SVille Syrjälä struct skl_plane_ddb_iter {
145642a0d256SVille Syrjälä u64 data_rate;
145742a0d256SVille Syrjälä u16 start, size;
145842a0d256SVille Syrjälä };
145942a0d256SVille Syrjälä
146042a0d256SVille Syrjälä static void
skl_allocate_plane_ddb(struct skl_plane_ddb_iter * iter,struct skl_ddb_entry * ddb,const struct skl_wm_level * wm,u64 data_rate)146142a0d256SVille Syrjälä skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
146242a0d256SVille Syrjälä struct skl_ddb_entry *ddb,
146342a0d256SVille Syrjälä const struct skl_wm_level *wm,
146442a0d256SVille Syrjälä u64 data_rate)
146542a0d256SVille Syrjälä {
146642a0d256SVille Syrjälä u16 size, extra = 0;
146742a0d256SVille Syrjälä
146842a0d256SVille Syrjälä if (data_rate) {
146942a0d256SVille Syrjälä extra = min_t(u16, iter->size,
147042a0d256SVille Syrjälä DIV64_U64_ROUND_UP(iter->size * data_rate,
147142a0d256SVille Syrjälä iter->data_rate));
147242a0d256SVille Syrjälä iter->size -= extra;
147342a0d256SVille Syrjälä iter->data_rate -= data_rate;
147442a0d256SVille Syrjälä }
147542a0d256SVille Syrjälä
147642a0d256SVille Syrjälä /*
147742a0d256SVille Syrjälä * Keep ddb entry of all disabled planes explicitly zeroed
147842a0d256SVille Syrjälä * to avoid skl_ddb_add_affected_planes() adding them to
147942a0d256SVille Syrjälä * the state when other planes change their allocations.
148042a0d256SVille Syrjälä */
148142a0d256SVille Syrjälä size = wm->min_ddb_alloc + extra;
148242a0d256SVille Syrjälä if (size)
148342a0d256SVille Syrjälä iter->start = skl_ddb_entry_init(ddb, iter->start,
148442a0d256SVille Syrjälä iter->start + size);
148542a0d256SVille Syrjälä }
148642a0d256SVille Syrjälä
148742a0d256SVille Syrjälä static int
skl_crtc_allocate_plane_ddb(struct intel_atomic_state * state,struct intel_crtc * crtc)148842a0d256SVille Syrjälä skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
148942a0d256SVille Syrjälä struct intel_crtc *crtc)
149042a0d256SVille Syrjälä {
149142a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
149242a0d256SVille Syrjälä struct intel_crtc_state *crtc_state =
149342a0d256SVille Syrjälä intel_atomic_get_new_crtc_state(state, crtc);
149442a0d256SVille Syrjälä const struct intel_dbuf_state *dbuf_state =
149542a0d256SVille Syrjälä intel_atomic_get_new_dbuf_state(state);
149642a0d256SVille Syrjälä const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
149742a0d256SVille Syrjälä int num_active = hweight8(dbuf_state->active_pipes);
149842a0d256SVille Syrjälä struct skl_plane_ddb_iter iter;
149942a0d256SVille Syrjälä enum plane_id plane_id;
150042a0d256SVille Syrjälä u16 cursor_size;
150142a0d256SVille Syrjälä u32 blocks;
150242a0d256SVille Syrjälä int level;
150342a0d256SVille Syrjälä
150442a0d256SVille Syrjälä /* Clear the partitioning for disabled planes. */
150542a0d256SVille Syrjälä memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb));
150642a0d256SVille Syrjälä memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
150742a0d256SVille Syrjälä
150842a0d256SVille Syrjälä if (!crtc_state->hw.active)
150942a0d256SVille Syrjälä return 0;
151042a0d256SVille Syrjälä
151142a0d256SVille Syrjälä iter.start = alloc->start;
151242a0d256SVille Syrjälä iter.size = skl_ddb_entry_size(alloc);
151342a0d256SVille Syrjälä if (iter.size == 0)
151442a0d256SVille Syrjälä return 0;
151542a0d256SVille Syrjälä
151642a0d256SVille Syrjälä /* Allocate fixed number of blocks for cursor. */
151742a0d256SVille Syrjälä cursor_size = skl_cursor_allocation(crtc_state, num_active);
151842a0d256SVille Syrjälä iter.size -= cursor_size;
151942a0d256SVille Syrjälä skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
152042a0d256SVille Syrjälä alloc->end - cursor_size, alloc->end);
152142a0d256SVille Syrjälä
152242a0d256SVille Syrjälä iter.data_rate = skl_total_relative_data_rate(crtc_state);
152342a0d256SVille Syrjälä
152442a0d256SVille Syrjälä /*
152542a0d256SVille Syrjälä * Find the highest watermark level for which we can satisfy the block
152642a0d256SVille Syrjälä * requirement of active planes.
152742a0d256SVille Syrjälä */
15287ee6f99dSVille Syrjälä for (level = i915->display.wm.num_levels - 1; level >= 0; level--) {
152942a0d256SVille Syrjälä blocks = 0;
153042a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
153142a0d256SVille Syrjälä const struct skl_plane_wm *wm =
153242a0d256SVille Syrjälä &crtc_state->wm.skl.optimal.planes[plane_id];
153342a0d256SVille Syrjälä
153442a0d256SVille Syrjälä if (plane_id == PLANE_CURSOR) {
153542a0d256SVille Syrjälä const struct skl_ddb_entry *ddb =
153642a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb[plane_id];
153742a0d256SVille Syrjälä
153842a0d256SVille Syrjälä if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) {
153942a0d256SVille Syrjälä drm_WARN_ON(&i915->drm,
154042a0d256SVille Syrjälä wm->wm[level].min_ddb_alloc != U16_MAX);
154142a0d256SVille Syrjälä blocks = U32_MAX;
154242a0d256SVille Syrjälä break;
154342a0d256SVille Syrjälä }
154442a0d256SVille Syrjälä continue;
154542a0d256SVille Syrjälä }
154642a0d256SVille Syrjälä
154742a0d256SVille Syrjälä blocks += wm->wm[level].min_ddb_alloc;
154842a0d256SVille Syrjälä blocks += wm->uv_wm[level].min_ddb_alloc;
154942a0d256SVille Syrjälä }
155042a0d256SVille Syrjälä
155142a0d256SVille Syrjälä if (blocks <= iter.size) {
155242a0d256SVille Syrjälä iter.size -= blocks;
155342a0d256SVille Syrjälä break;
155442a0d256SVille Syrjälä }
155542a0d256SVille Syrjälä }
155642a0d256SVille Syrjälä
155742a0d256SVille Syrjälä if (level < 0) {
155842a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
155942a0d256SVille Syrjälä "Requested display configuration exceeds system DDB limitations");
156042a0d256SVille Syrjälä drm_dbg_kms(&i915->drm, "minimum required %d/%d\n",
156142a0d256SVille Syrjälä blocks, iter.size);
156242a0d256SVille Syrjälä return -EINVAL;
156342a0d256SVille Syrjälä }
156442a0d256SVille Syrjälä
156542a0d256SVille Syrjälä /* avoid the WARN later when we don't allocate any extra DDB */
156642a0d256SVille Syrjälä if (iter.data_rate == 0)
156742a0d256SVille Syrjälä iter.size = 0;
156842a0d256SVille Syrjälä
156942a0d256SVille Syrjälä /*
157042a0d256SVille Syrjälä * Grant each plane the blocks it requires at the highest achievable
157142a0d256SVille Syrjälä * watermark level, plus an extra share of the leftover blocks
157242a0d256SVille Syrjälä * proportional to its relative data rate.
157342a0d256SVille Syrjälä */
157442a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
157542a0d256SVille Syrjälä struct skl_ddb_entry *ddb =
157642a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb[plane_id];
157742a0d256SVille Syrjälä struct skl_ddb_entry *ddb_y =
157842a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb_y[plane_id];
157942a0d256SVille Syrjälä const struct skl_plane_wm *wm =
158042a0d256SVille Syrjälä &crtc_state->wm.skl.optimal.planes[plane_id];
158142a0d256SVille Syrjälä
158242a0d256SVille Syrjälä if (plane_id == PLANE_CURSOR)
158342a0d256SVille Syrjälä continue;
158442a0d256SVille Syrjälä
158542a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 11 &&
158642a0d256SVille Syrjälä crtc_state->nv12_planes & BIT(plane_id)) {
158742a0d256SVille Syrjälä skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level],
158842a0d256SVille Syrjälä crtc_state->rel_data_rate_y[plane_id]);
158942a0d256SVille Syrjälä skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level],
159042a0d256SVille Syrjälä crtc_state->rel_data_rate[plane_id]);
159142a0d256SVille Syrjälä } else {
159242a0d256SVille Syrjälä skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level],
159342a0d256SVille Syrjälä crtc_state->rel_data_rate[plane_id]);
159442a0d256SVille Syrjälä }
159542a0d256SVille Syrjälä }
159642a0d256SVille Syrjälä drm_WARN_ON(&i915->drm, iter.size != 0 || iter.data_rate != 0);
159742a0d256SVille Syrjälä
159842a0d256SVille Syrjälä /*
159942a0d256SVille Syrjälä * When we calculated watermark values we didn't know how high
160042a0d256SVille Syrjälä * of a level we'd actually be able to hit, so we just marked
160142a0d256SVille Syrjälä * all levels as "enabled." Go back now and disable the ones
160242a0d256SVille Syrjälä * that aren't actually possible.
160342a0d256SVille Syrjälä */
16047ee6f99dSVille Syrjälä for (level++; level < i915->display.wm.num_levels; level++) {
160542a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
160642a0d256SVille Syrjälä const struct skl_ddb_entry *ddb =
160742a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb[plane_id];
160842a0d256SVille Syrjälä const struct skl_ddb_entry *ddb_y =
160942a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb_y[plane_id];
161042a0d256SVille Syrjälä struct skl_plane_wm *wm =
161142a0d256SVille Syrjälä &crtc_state->wm.skl.optimal.planes[plane_id];
161242a0d256SVille Syrjälä
161342a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 11 &&
161442a0d256SVille Syrjälä crtc_state->nv12_planes & BIT(plane_id))
161542a0d256SVille Syrjälä skl_check_nv12_wm_level(&wm->wm[level],
161642a0d256SVille Syrjälä &wm->uv_wm[level],
161742a0d256SVille Syrjälä ddb_y, ddb);
161842a0d256SVille Syrjälä else
161942a0d256SVille Syrjälä skl_check_wm_level(&wm->wm[level], ddb);
162042a0d256SVille Syrjälä
16219fcbae04SStanislav Lisovskiy if (skl_need_wm_copy_wa(i915, level, wm)) {
16229fcbae04SStanislav Lisovskiy wm->wm[level].blocks = wm->wm[level - 1].blocks;
16239fcbae04SStanislav Lisovskiy wm->wm[level].lines = wm->wm[level - 1].lines;
16249fcbae04SStanislav Lisovskiy wm->wm[level].ignore_lines = wm->wm[level - 1].ignore_lines;
162542a0d256SVille Syrjälä }
162642a0d256SVille Syrjälä }
162742a0d256SVille Syrjälä }
162842a0d256SVille Syrjälä
162942a0d256SVille Syrjälä /*
163042a0d256SVille Syrjälä * Go back and disable the transition and SAGV watermarks
163142a0d256SVille Syrjälä * if it turns out we don't have enough DDB blocks for them.
163242a0d256SVille Syrjälä */
163342a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
163442a0d256SVille Syrjälä const struct skl_ddb_entry *ddb =
163542a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb[plane_id];
163642a0d256SVille Syrjälä const struct skl_ddb_entry *ddb_y =
163742a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb_y[plane_id];
163842a0d256SVille Syrjälä struct skl_plane_wm *wm =
163942a0d256SVille Syrjälä &crtc_state->wm.skl.optimal.planes[plane_id];
164042a0d256SVille Syrjälä
164142a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 11 &&
164242a0d256SVille Syrjälä crtc_state->nv12_planes & BIT(plane_id)) {
164342a0d256SVille Syrjälä skl_check_wm_level(&wm->trans_wm, ddb_y);
164442a0d256SVille Syrjälä } else {
164542a0d256SVille Syrjälä WARN_ON(skl_ddb_entry_size(ddb_y));
164642a0d256SVille Syrjälä
164742a0d256SVille Syrjälä skl_check_wm_level(&wm->trans_wm, ddb);
164842a0d256SVille Syrjälä }
164942a0d256SVille Syrjälä
165042a0d256SVille Syrjälä skl_check_wm_level(&wm->sagv.wm0, ddb);
165142a0d256SVille Syrjälä skl_check_wm_level(&wm->sagv.trans_wm, ddb);
165242a0d256SVille Syrjälä }
165342a0d256SVille Syrjälä
165442a0d256SVille Syrjälä return 0;
165542a0d256SVille Syrjälä }
165642a0d256SVille Syrjälä
165742a0d256SVille Syrjälä /*
165842a0d256SVille Syrjälä * The max latency should be 257 (max the punit can code is 255 and we add 2us
165942a0d256SVille Syrjälä * for the read latency) and cpp should always be <= 8, so that
166042a0d256SVille Syrjälä * should allow pixel_rate up to ~2 GHz which seems sufficient since max
166142a0d256SVille Syrjälä * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
166242a0d256SVille Syrjälä */
166342a0d256SVille Syrjälä static uint_fixed_16_16_t
skl_wm_method1(const struct drm_i915_private * i915,u32 pixel_rate,u8 cpp,u32 latency,u32 dbuf_block_size)166442a0d256SVille Syrjälä skl_wm_method1(const struct drm_i915_private *i915, u32 pixel_rate,
166542a0d256SVille Syrjälä u8 cpp, u32 latency, u32 dbuf_block_size)
166642a0d256SVille Syrjälä {
166742a0d256SVille Syrjälä u32 wm_intermediate_val;
166842a0d256SVille Syrjälä uint_fixed_16_16_t ret;
166942a0d256SVille Syrjälä
167042a0d256SVille Syrjälä if (latency == 0)
167142a0d256SVille Syrjälä return FP_16_16_MAX;
167242a0d256SVille Syrjälä
167342a0d256SVille Syrjälä wm_intermediate_val = latency * pixel_rate * cpp;
167442a0d256SVille Syrjälä ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
167542a0d256SVille Syrjälä
167642a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 10)
167742a0d256SVille Syrjälä ret = add_fixed16_u32(ret, 1);
167842a0d256SVille Syrjälä
167942a0d256SVille Syrjälä return ret;
168042a0d256SVille Syrjälä }
168142a0d256SVille Syrjälä
168242a0d256SVille Syrjälä static uint_fixed_16_16_t
skl_wm_method2(u32 pixel_rate,u32 pipe_htotal,u32 latency,uint_fixed_16_16_t plane_blocks_per_line)168342a0d256SVille Syrjälä skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
168442a0d256SVille Syrjälä uint_fixed_16_16_t plane_blocks_per_line)
168542a0d256SVille Syrjälä {
168642a0d256SVille Syrjälä u32 wm_intermediate_val;
168742a0d256SVille Syrjälä uint_fixed_16_16_t ret;
168842a0d256SVille Syrjälä
168942a0d256SVille Syrjälä if (latency == 0)
169042a0d256SVille Syrjälä return FP_16_16_MAX;
169142a0d256SVille Syrjälä
169242a0d256SVille Syrjälä wm_intermediate_val = latency * pixel_rate;
169342a0d256SVille Syrjälä wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
169442a0d256SVille Syrjälä pipe_htotal * 1000);
169542a0d256SVille Syrjälä ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
169642a0d256SVille Syrjälä return ret;
169742a0d256SVille Syrjälä }
169842a0d256SVille Syrjälä
169942a0d256SVille Syrjälä static uint_fixed_16_16_t
intel_get_linetime_us(const struct intel_crtc_state * crtc_state)170042a0d256SVille Syrjälä intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
170142a0d256SVille Syrjälä {
170242a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
170342a0d256SVille Syrjälä u32 pixel_rate;
170442a0d256SVille Syrjälä u32 crtc_htotal;
170542a0d256SVille Syrjälä uint_fixed_16_16_t linetime_us;
170642a0d256SVille Syrjälä
170742a0d256SVille Syrjälä if (!crtc_state->hw.active)
170842a0d256SVille Syrjälä return u32_to_fixed16(0);
170942a0d256SVille Syrjälä
171042a0d256SVille Syrjälä pixel_rate = crtc_state->pixel_rate;
171142a0d256SVille Syrjälä
171242a0d256SVille Syrjälä if (drm_WARN_ON(&i915->drm, pixel_rate == 0))
171342a0d256SVille Syrjälä return u32_to_fixed16(0);
171442a0d256SVille Syrjälä
171542a0d256SVille Syrjälä crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
171642a0d256SVille Syrjälä linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
171742a0d256SVille Syrjälä
171842a0d256SVille Syrjälä return linetime_us;
171942a0d256SVille Syrjälä }
172042a0d256SVille Syrjälä
172142a0d256SVille Syrjälä static int
skl_compute_wm_params(const struct intel_crtc_state * crtc_state,int width,const struct drm_format_info * format,u64 modifier,unsigned int rotation,u32 plane_pixel_rate,struct skl_wm_params * wp,int color_plane)172242a0d256SVille Syrjälä skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
172342a0d256SVille Syrjälä int width, const struct drm_format_info *format,
172442a0d256SVille Syrjälä u64 modifier, unsigned int rotation,
172542a0d256SVille Syrjälä u32 plane_pixel_rate, struct skl_wm_params *wp,
172642a0d256SVille Syrjälä int color_plane)
172742a0d256SVille Syrjälä {
172842a0d256SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
172942a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
173042a0d256SVille Syrjälä u32 interm_pbpl;
173142a0d256SVille Syrjälä
173242a0d256SVille Syrjälä /* only planar format has two planes */
173342a0d256SVille Syrjälä if (color_plane == 1 &&
173442a0d256SVille Syrjälä !intel_format_info_is_yuv_semiplanar(format, modifier)) {
173542a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
173642a0d256SVille Syrjälä "Non planar format have single plane\n");
173742a0d256SVille Syrjälä return -EINVAL;
173842a0d256SVille Syrjälä }
173942a0d256SVille Syrjälä
174042a0d256SVille Syrjälä wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
1741d5c45330SVille Syrjälä wp->y_tiled = modifier != I915_FORMAT_MOD_X_TILED &&
1742d5c45330SVille Syrjälä intel_fb_is_tiled_modifier(modifier);
1743d5c45330SVille Syrjälä wp->rc_surface = intel_fb_is_ccs_modifier(modifier);
174442a0d256SVille Syrjälä wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
174542a0d256SVille Syrjälä
174642a0d256SVille Syrjälä wp->width = width;
174742a0d256SVille Syrjälä if (color_plane == 1 && wp->is_planar)
174842a0d256SVille Syrjälä wp->width /= 2;
174942a0d256SVille Syrjälä
175042a0d256SVille Syrjälä wp->cpp = format->cpp[color_plane];
175142a0d256SVille Syrjälä wp->plane_pixel_rate = plane_pixel_rate;
175242a0d256SVille Syrjälä
175342a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 11 &&
175442a0d256SVille Syrjälä modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
175542a0d256SVille Syrjälä wp->dbuf_block_size = 256;
175642a0d256SVille Syrjälä else
175742a0d256SVille Syrjälä wp->dbuf_block_size = 512;
175842a0d256SVille Syrjälä
175942a0d256SVille Syrjälä if (drm_rotation_90_or_270(rotation)) {
176042a0d256SVille Syrjälä switch (wp->cpp) {
176142a0d256SVille Syrjälä case 1:
176242a0d256SVille Syrjälä wp->y_min_scanlines = 16;
176342a0d256SVille Syrjälä break;
176442a0d256SVille Syrjälä case 2:
176542a0d256SVille Syrjälä wp->y_min_scanlines = 8;
176642a0d256SVille Syrjälä break;
176742a0d256SVille Syrjälä case 4:
176842a0d256SVille Syrjälä wp->y_min_scanlines = 4;
176942a0d256SVille Syrjälä break;
177042a0d256SVille Syrjälä default:
177142a0d256SVille Syrjälä MISSING_CASE(wp->cpp);
177242a0d256SVille Syrjälä return -EINVAL;
177342a0d256SVille Syrjälä }
177442a0d256SVille Syrjälä } else {
177542a0d256SVille Syrjälä wp->y_min_scanlines = 4;
177642a0d256SVille Syrjälä }
177742a0d256SVille Syrjälä
177842a0d256SVille Syrjälä if (skl_needs_memory_bw_wa(i915))
177942a0d256SVille Syrjälä wp->y_min_scanlines *= 2;
178042a0d256SVille Syrjälä
178142a0d256SVille Syrjälä wp->plane_bytes_per_line = wp->width * wp->cpp;
178242a0d256SVille Syrjälä if (wp->y_tiled) {
178342a0d256SVille Syrjälä interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
178442a0d256SVille Syrjälä wp->y_min_scanlines,
178542a0d256SVille Syrjälä wp->dbuf_block_size);
178642a0d256SVille Syrjälä
178742a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 10)
178842a0d256SVille Syrjälä interm_pbpl++;
178942a0d256SVille Syrjälä
179042a0d256SVille Syrjälä wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
179142a0d256SVille Syrjälä wp->y_min_scanlines);
179242a0d256SVille Syrjälä } else {
179342a0d256SVille Syrjälä interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
179442a0d256SVille Syrjälä wp->dbuf_block_size);
179542a0d256SVille Syrjälä
179642a0d256SVille Syrjälä if (!wp->x_tiled || DISPLAY_VER(i915) >= 10)
179742a0d256SVille Syrjälä interm_pbpl++;
179842a0d256SVille Syrjälä
179942a0d256SVille Syrjälä wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
180042a0d256SVille Syrjälä }
180142a0d256SVille Syrjälä
180242a0d256SVille Syrjälä wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
180342a0d256SVille Syrjälä wp->plane_blocks_per_line);
180442a0d256SVille Syrjälä
180542a0d256SVille Syrjälä wp->linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(crtc_state));
180642a0d256SVille Syrjälä
180742a0d256SVille Syrjälä return 0;
180842a0d256SVille Syrjälä }
180942a0d256SVille Syrjälä
181042a0d256SVille Syrjälä static int
skl_compute_plane_wm_params(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,struct skl_wm_params * wp,int color_plane)181142a0d256SVille Syrjälä skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
181242a0d256SVille Syrjälä const struct intel_plane_state *plane_state,
181342a0d256SVille Syrjälä struct skl_wm_params *wp, int color_plane)
181442a0d256SVille Syrjälä {
181542a0d256SVille Syrjälä const struct drm_framebuffer *fb = plane_state->hw.fb;
181642a0d256SVille Syrjälä int width;
181742a0d256SVille Syrjälä
181842a0d256SVille Syrjälä /*
181942a0d256SVille Syrjälä * Src coordinates are already rotated by 270 degrees for
182042a0d256SVille Syrjälä * the 90/270 degree plane rotation cases (to match the
182142a0d256SVille Syrjälä * GTT mapping), hence no need to account for rotation here.
182242a0d256SVille Syrjälä */
182342a0d256SVille Syrjälä width = drm_rect_width(&plane_state->uapi.src) >> 16;
182442a0d256SVille Syrjälä
182542a0d256SVille Syrjälä return skl_compute_wm_params(crtc_state, width,
182642a0d256SVille Syrjälä fb->format, fb->modifier,
182742a0d256SVille Syrjälä plane_state->hw.rotation,
182842a0d256SVille Syrjälä intel_plane_pixel_rate(crtc_state, plane_state),
182942a0d256SVille Syrjälä wp, color_plane);
183042a0d256SVille Syrjälä }
183142a0d256SVille Syrjälä
skl_wm_has_lines(struct drm_i915_private * i915,int level)183242a0d256SVille Syrjälä static bool skl_wm_has_lines(struct drm_i915_private *i915, int level)
183342a0d256SVille Syrjälä {
183442a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 10)
183542a0d256SVille Syrjälä return true;
183642a0d256SVille Syrjälä
183742a0d256SVille Syrjälä /* The number of lines are ignored for the level 0 watermark. */
183842a0d256SVille Syrjälä return level > 0;
183942a0d256SVille Syrjälä }
184042a0d256SVille Syrjälä
skl_wm_max_lines(struct drm_i915_private * i915)184142a0d256SVille Syrjälä static int skl_wm_max_lines(struct drm_i915_private *i915)
184242a0d256SVille Syrjälä {
184342a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 13)
184442a0d256SVille Syrjälä return 255;
184542a0d256SVille Syrjälä else
184642a0d256SVille Syrjälä return 31;
184742a0d256SVille Syrjälä }
184842a0d256SVille Syrjälä
skl_compute_plane_wm(const struct intel_crtc_state * crtc_state,struct intel_plane * plane,int level,unsigned int latency,const struct skl_wm_params * wp,const struct skl_wm_level * result_prev,struct skl_wm_level * result)184942a0d256SVille Syrjälä static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
185042a0d256SVille Syrjälä struct intel_plane *plane,
185142a0d256SVille Syrjälä int level,
185242a0d256SVille Syrjälä unsigned int latency,
185342a0d256SVille Syrjälä const struct skl_wm_params *wp,
185442a0d256SVille Syrjälä const struct skl_wm_level *result_prev,
185542a0d256SVille Syrjälä struct skl_wm_level *result /* out */)
185642a0d256SVille Syrjälä {
185742a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
185842a0d256SVille Syrjälä uint_fixed_16_16_t method1, method2;
185942a0d256SVille Syrjälä uint_fixed_16_16_t selected_result;
186042a0d256SVille Syrjälä u32 blocks, lines, min_ddb_alloc = 0;
186142a0d256SVille Syrjälä
186242a0d256SVille Syrjälä if (latency == 0 ||
186342a0d256SVille Syrjälä (use_minimal_wm0_only(crtc_state, plane) && level > 0)) {
186442a0d256SVille Syrjälä /* reject it */
186542a0d256SVille Syrjälä result->min_ddb_alloc = U16_MAX;
186642a0d256SVille Syrjälä return;
186742a0d256SVille Syrjälä }
186842a0d256SVille Syrjälä
186942a0d256SVille Syrjälä method1 = skl_wm_method1(i915, wp->plane_pixel_rate,
187042a0d256SVille Syrjälä wp->cpp, latency, wp->dbuf_block_size);
187142a0d256SVille Syrjälä method2 = skl_wm_method2(wp->plane_pixel_rate,
187242a0d256SVille Syrjälä crtc_state->hw.pipe_mode.crtc_htotal,
187342a0d256SVille Syrjälä latency,
187442a0d256SVille Syrjälä wp->plane_blocks_per_line);
187542a0d256SVille Syrjälä
187642a0d256SVille Syrjälä if (wp->y_tiled) {
187742a0d256SVille Syrjälä selected_result = max_fixed16(method2, wp->y_tile_minimum);
187842a0d256SVille Syrjälä } else {
187942a0d256SVille Syrjälä if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
188042a0d256SVille Syrjälä wp->dbuf_block_size < 1) &&
188142a0d256SVille Syrjälä (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
188242a0d256SVille Syrjälä selected_result = method2;
188342a0d256SVille Syrjälä } else if (latency >= wp->linetime_us) {
188442a0d256SVille Syrjälä if (DISPLAY_VER(i915) == 9)
188542a0d256SVille Syrjälä selected_result = min_fixed16(method1, method2);
188642a0d256SVille Syrjälä else
188742a0d256SVille Syrjälä selected_result = method2;
188842a0d256SVille Syrjälä } else {
188942a0d256SVille Syrjälä selected_result = method1;
189042a0d256SVille Syrjälä }
189142a0d256SVille Syrjälä }
189242a0d256SVille Syrjälä
189342a0d256SVille Syrjälä blocks = fixed16_to_u32_round_up(selected_result) + 1;
189442a0d256SVille Syrjälä /*
189542a0d256SVille Syrjälä * Lets have blocks at minimum equivalent to plane_blocks_per_line
189642a0d256SVille Syrjälä * as there will be at minimum one line for lines configuration. This
189742a0d256SVille Syrjälä * is a work around for FIFO underruns observed with resolutions like
189842a0d256SVille Syrjälä * 4k 60 Hz in single channel DRAM configurations.
189942a0d256SVille Syrjälä *
190042a0d256SVille Syrjälä * As per the Bspec 49325, if the ddb allocation can hold at least
190142a0d256SVille Syrjälä * one plane_blocks_per_line, we should have selected method2 in
190242a0d256SVille Syrjälä * the above logic. Assuming that modern versions have enough dbuf
190342a0d256SVille Syrjälä * and method2 guarantees blocks equivalent to at least 1 line,
190442a0d256SVille Syrjälä * select the blocks as plane_blocks_per_line.
190542a0d256SVille Syrjälä *
190642a0d256SVille Syrjälä * TODO: Revisit the logic when we have better understanding on DRAM
190742a0d256SVille Syrjälä * channels' impact on the level 0 memory latency and the relevant
190842a0d256SVille Syrjälä * wm calculations.
190942a0d256SVille Syrjälä */
191042a0d256SVille Syrjälä if (skl_wm_has_lines(i915, level))
191142a0d256SVille Syrjälä blocks = max(blocks,
191242a0d256SVille Syrjälä fixed16_to_u32_round_up(wp->plane_blocks_per_line));
191342a0d256SVille Syrjälä lines = div_round_up_fixed16(selected_result,
191442a0d256SVille Syrjälä wp->plane_blocks_per_line);
191542a0d256SVille Syrjälä
191642a0d256SVille Syrjälä if (DISPLAY_VER(i915) == 9) {
191742a0d256SVille Syrjälä /* Display WA #1125: skl,bxt,kbl */
191842a0d256SVille Syrjälä if (level == 0 && wp->rc_surface)
191942a0d256SVille Syrjälä blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
192042a0d256SVille Syrjälä
192142a0d256SVille Syrjälä /* Display WA #1126: skl,bxt,kbl */
192242a0d256SVille Syrjälä if (level >= 1 && level <= 7) {
192342a0d256SVille Syrjälä if (wp->y_tiled) {
192442a0d256SVille Syrjälä blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
192542a0d256SVille Syrjälä lines += wp->y_min_scanlines;
192642a0d256SVille Syrjälä } else {
192742a0d256SVille Syrjälä blocks++;
192842a0d256SVille Syrjälä }
192942a0d256SVille Syrjälä
193042a0d256SVille Syrjälä /*
193142a0d256SVille Syrjälä * Make sure result blocks for higher latency levels are
193242a0d256SVille Syrjälä * at least as high as level below the current level.
193342a0d256SVille Syrjälä * Assumption in DDB algorithm optimization for special
193442a0d256SVille Syrjälä * cases. Also covers Display WA #1125 for RC.
193542a0d256SVille Syrjälä */
193642a0d256SVille Syrjälä if (result_prev->blocks > blocks)
193742a0d256SVille Syrjälä blocks = result_prev->blocks;
193842a0d256SVille Syrjälä }
193942a0d256SVille Syrjälä }
194042a0d256SVille Syrjälä
194142a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 11) {
194242a0d256SVille Syrjälä if (wp->y_tiled) {
194342a0d256SVille Syrjälä int extra_lines;
194442a0d256SVille Syrjälä
194542a0d256SVille Syrjälä if (lines % wp->y_min_scanlines == 0)
194642a0d256SVille Syrjälä extra_lines = wp->y_min_scanlines;
194742a0d256SVille Syrjälä else
194842a0d256SVille Syrjälä extra_lines = wp->y_min_scanlines * 2 -
194942a0d256SVille Syrjälä lines % wp->y_min_scanlines;
195042a0d256SVille Syrjälä
195142a0d256SVille Syrjälä min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines,
195242a0d256SVille Syrjälä wp->plane_blocks_per_line);
195342a0d256SVille Syrjälä } else {
195442a0d256SVille Syrjälä min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10);
195542a0d256SVille Syrjälä }
195642a0d256SVille Syrjälä }
195742a0d256SVille Syrjälä
195842a0d256SVille Syrjälä if (!skl_wm_has_lines(i915, level))
195942a0d256SVille Syrjälä lines = 0;
196042a0d256SVille Syrjälä
196142a0d256SVille Syrjälä if (lines > skl_wm_max_lines(i915)) {
196242a0d256SVille Syrjälä /* reject it */
196342a0d256SVille Syrjälä result->min_ddb_alloc = U16_MAX;
196442a0d256SVille Syrjälä return;
196542a0d256SVille Syrjälä }
196642a0d256SVille Syrjälä
196742a0d256SVille Syrjälä /*
196842a0d256SVille Syrjälä * If lines is valid, assume we can use this watermark level
196942a0d256SVille Syrjälä * for now. We'll come back and disable it after we calculate the
197042a0d256SVille Syrjälä * DDB allocation if it turns out we don't actually have enough
197142a0d256SVille Syrjälä * blocks to satisfy it.
197242a0d256SVille Syrjälä */
197342a0d256SVille Syrjälä result->blocks = blocks;
197442a0d256SVille Syrjälä result->lines = lines;
197542a0d256SVille Syrjälä /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
197642a0d256SVille Syrjälä result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
197742a0d256SVille Syrjälä result->enable = true;
197842a0d256SVille Syrjälä
197942a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 12 && i915->display.sagv.block_time_us)
198042a0d256SVille Syrjälä result->can_sagv = latency >= i915->display.sagv.block_time_us;
198142a0d256SVille Syrjälä }
198242a0d256SVille Syrjälä
198342a0d256SVille Syrjälä static void
skl_compute_wm_levels(const struct intel_crtc_state * crtc_state,struct intel_plane * plane,const struct skl_wm_params * wm_params,struct skl_wm_level * levels)198442a0d256SVille Syrjälä skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
198542a0d256SVille Syrjälä struct intel_plane *plane,
198642a0d256SVille Syrjälä const struct skl_wm_params *wm_params,
198742a0d256SVille Syrjälä struct skl_wm_level *levels)
198842a0d256SVille Syrjälä {
198942a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
199042a0d256SVille Syrjälä struct skl_wm_level *result_prev = &levels[0];
19917ee6f99dSVille Syrjälä int level;
199242a0d256SVille Syrjälä
19937ee6f99dSVille Syrjälä for (level = 0; level < i915->display.wm.num_levels; level++) {
199442a0d256SVille Syrjälä struct skl_wm_level *result = &levels[level];
19956b931346SVille Syrjälä unsigned int latency = skl_wm_latency(i915, level, wm_params);
199642a0d256SVille Syrjälä
199742a0d256SVille Syrjälä skl_compute_plane_wm(crtc_state, plane, level, latency,
199842a0d256SVille Syrjälä wm_params, result_prev, result);
199942a0d256SVille Syrjälä
200042a0d256SVille Syrjälä result_prev = result;
200142a0d256SVille Syrjälä }
200242a0d256SVille Syrjälä }
200342a0d256SVille Syrjälä
tgl_compute_sagv_wm(const struct intel_crtc_state * crtc_state,struct intel_plane * plane,const struct skl_wm_params * wm_params,struct skl_plane_wm * plane_wm)200442a0d256SVille Syrjälä static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
200542a0d256SVille Syrjälä struct intel_plane *plane,
200642a0d256SVille Syrjälä const struct skl_wm_params *wm_params,
200742a0d256SVille Syrjälä struct skl_plane_wm *plane_wm)
200842a0d256SVille Syrjälä {
200942a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
201042a0d256SVille Syrjälä struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;
201142a0d256SVille Syrjälä struct skl_wm_level *levels = plane_wm->wm;
201242a0d256SVille Syrjälä unsigned int latency = 0;
201342a0d256SVille Syrjälä
201442a0d256SVille Syrjälä if (i915->display.sagv.block_time_us)
20156b931346SVille Syrjälä latency = i915->display.sagv.block_time_us +
20166b931346SVille Syrjälä skl_wm_latency(i915, 0, wm_params);
201742a0d256SVille Syrjälä
201842a0d256SVille Syrjälä skl_compute_plane_wm(crtc_state, plane, 0, latency,
201942a0d256SVille Syrjälä wm_params, &levels[0],
202042a0d256SVille Syrjälä sagv_wm);
202142a0d256SVille Syrjälä }
202242a0d256SVille Syrjälä
skl_compute_transition_wm(struct drm_i915_private * i915,struct skl_wm_level * trans_wm,const struct skl_wm_level * wm0,const struct skl_wm_params * wp)202342a0d256SVille Syrjälä static void skl_compute_transition_wm(struct drm_i915_private *i915,
202442a0d256SVille Syrjälä struct skl_wm_level *trans_wm,
202542a0d256SVille Syrjälä const struct skl_wm_level *wm0,
202642a0d256SVille Syrjälä const struct skl_wm_params *wp)
202742a0d256SVille Syrjälä {
202842a0d256SVille Syrjälä u16 trans_min, trans_amount, trans_y_tile_min;
202942a0d256SVille Syrjälä u16 wm0_blocks, trans_offset, blocks;
203042a0d256SVille Syrjälä
203142a0d256SVille Syrjälä /* Transition WM don't make any sense if ipc is disabled */
203223fbdb07SJani Nikula if (!skl_watermark_ipc_enabled(i915))
203342a0d256SVille Syrjälä return;
203442a0d256SVille Syrjälä
203542a0d256SVille Syrjälä /*
203642a0d256SVille Syrjälä * WaDisableTWM:skl,kbl,cfl,bxt
203742a0d256SVille Syrjälä * Transition WM are not recommended by HW team for GEN9
203842a0d256SVille Syrjälä */
203942a0d256SVille Syrjälä if (DISPLAY_VER(i915) == 9)
204042a0d256SVille Syrjälä return;
204142a0d256SVille Syrjälä
204242a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 11)
204342a0d256SVille Syrjälä trans_min = 4;
204442a0d256SVille Syrjälä else
204542a0d256SVille Syrjälä trans_min = 14;
204642a0d256SVille Syrjälä
204742a0d256SVille Syrjälä /* Display WA #1140: glk,cnl */
204842a0d256SVille Syrjälä if (DISPLAY_VER(i915) == 10)
204942a0d256SVille Syrjälä trans_amount = 0;
205042a0d256SVille Syrjälä else
205142a0d256SVille Syrjälä trans_amount = 10; /* This is configurable amount */
205242a0d256SVille Syrjälä
205342a0d256SVille Syrjälä trans_offset = trans_min + trans_amount;
205442a0d256SVille Syrjälä
205542a0d256SVille Syrjälä /*
205642a0d256SVille Syrjälä * The spec asks for Selected Result Blocks for wm0 (the real value),
205742a0d256SVille Syrjälä * not Result Blocks (the integer value). Pay attention to the capital
205842a0d256SVille Syrjälä * letters. The value wm_l0->blocks is actually Result Blocks, but
205942a0d256SVille Syrjälä * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
206042a0d256SVille Syrjälä * and since we later will have to get the ceiling of the sum in the
206142a0d256SVille Syrjälä * transition watermarks calculation, we can just pretend Selected
206242a0d256SVille Syrjälä * Result Blocks is Result Blocks minus 1 and it should work for the
206342a0d256SVille Syrjälä * current platforms.
206442a0d256SVille Syrjälä */
206542a0d256SVille Syrjälä wm0_blocks = wm0->blocks - 1;
206642a0d256SVille Syrjälä
206742a0d256SVille Syrjälä if (wp->y_tiled) {
206842a0d256SVille Syrjälä trans_y_tile_min =
206942a0d256SVille Syrjälä (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
207042a0d256SVille Syrjälä blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset;
207142a0d256SVille Syrjälä } else {
207242a0d256SVille Syrjälä blocks = wm0_blocks + trans_offset;
207342a0d256SVille Syrjälä }
207442a0d256SVille Syrjälä blocks++;
207542a0d256SVille Syrjälä
207642a0d256SVille Syrjälä /*
207742a0d256SVille Syrjälä * Just assume we can enable the transition watermark. After
207842a0d256SVille Syrjälä * computing the DDB we'll come back and disable it if that
207942a0d256SVille Syrjälä * assumption turns out to be false.
208042a0d256SVille Syrjälä */
208142a0d256SVille Syrjälä trans_wm->blocks = blocks;
208242a0d256SVille Syrjälä trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1);
208342a0d256SVille Syrjälä trans_wm->enable = true;
208442a0d256SVille Syrjälä }
208542a0d256SVille Syrjälä
skl_build_plane_wm_single(struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,struct intel_plane * plane,int color_plane)208642a0d256SVille Syrjälä static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
208742a0d256SVille Syrjälä const struct intel_plane_state *plane_state,
208842a0d256SVille Syrjälä struct intel_plane *plane, int color_plane)
208942a0d256SVille Syrjälä {
209042a0d256SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
209142a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
209242a0d256SVille Syrjälä struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
209342a0d256SVille Syrjälä struct skl_wm_params wm_params;
209442a0d256SVille Syrjälä int ret;
209542a0d256SVille Syrjälä
209642a0d256SVille Syrjälä ret = skl_compute_plane_wm_params(crtc_state, plane_state,
209742a0d256SVille Syrjälä &wm_params, color_plane);
209842a0d256SVille Syrjälä if (ret)
209942a0d256SVille Syrjälä return ret;
210042a0d256SVille Syrjälä
210142a0d256SVille Syrjälä skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->wm);
210242a0d256SVille Syrjälä
210342a0d256SVille Syrjälä skl_compute_transition_wm(i915, &wm->trans_wm,
210442a0d256SVille Syrjälä &wm->wm[0], &wm_params);
210542a0d256SVille Syrjälä
210642a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 12) {
210742a0d256SVille Syrjälä tgl_compute_sagv_wm(crtc_state, plane, &wm_params, wm);
210842a0d256SVille Syrjälä
210942a0d256SVille Syrjälä skl_compute_transition_wm(i915, &wm->sagv.trans_wm,
211042a0d256SVille Syrjälä &wm->sagv.wm0, &wm_params);
211142a0d256SVille Syrjälä }
211242a0d256SVille Syrjälä
211342a0d256SVille Syrjälä return 0;
211442a0d256SVille Syrjälä }
211542a0d256SVille Syrjälä
skl_build_plane_wm_uv(struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,struct intel_plane * plane)211642a0d256SVille Syrjälä static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
211742a0d256SVille Syrjälä const struct intel_plane_state *plane_state,
211842a0d256SVille Syrjälä struct intel_plane *plane)
211942a0d256SVille Syrjälä {
212042a0d256SVille Syrjälä struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];
212142a0d256SVille Syrjälä struct skl_wm_params wm_params;
212242a0d256SVille Syrjälä int ret;
212342a0d256SVille Syrjälä
212442a0d256SVille Syrjälä wm->is_planar = true;
212542a0d256SVille Syrjälä
212642a0d256SVille Syrjälä /* uv plane watermarks must also be validated for NV12/Planar */
212742a0d256SVille Syrjälä ret = skl_compute_plane_wm_params(crtc_state, plane_state,
212842a0d256SVille Syrjälä &wm_params, 1);
212942a0d256SVille Syrjälä if (ret)
213042a0d256SVille Syrjälä return ret;
213142a0d256SVille Syrjälä
213242a0d256SVille Syrjälä skl_compute_wm_levels(crtc_state, plane, &wm_params, wm->uv_wm);
213342a0d256SVille Syrjälä
213442a0d256SVille Syrjälä return 0;
213542a0d256SVille Syrjälä }
213642a0d256SVille Syrjälä
skl_build_plane_wm(struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)213742a0d256SVille Syrjälä static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
213842a0d256SVille Syrjälä const struct intel_plane_state *plane_state)
213942a0d256SVille Syrjälä {
214042a0d256SVille Syrjälä struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
214142a0d256SVille Syrjälä enum plane_id plane_id = plane->id;
214242a0d256SVille Syrjälä struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
214342a0d256SVille Syrjälä const struct drm_framebuffer *fb = plane_state->hw.fb;
214442a0d256SVille Syrjälä int ret;
214542a0d256SVille Syrjälä
214642a0d256SVille Syrjälä memset(wm, 0, sizeof(*wm));
214742a0d256SVille Syrjälä
214842a0d256SVille Syrjälä if (!intel_wm_plane_visible(crtc_state, plane_state))
214942a0d256SVille Syrjälä return 0;
215042a0d256SVille Syrjälä
215142a0d256SVille Syrjälä ret = skl_build_plane_wm_single(crtc_state, plane_state,
215242a0d256SVille Syrjälä plane, 0);
215342a0d256SVille Syrjälä if (ret)
215442a0d256SVille Syrjälä return ret;
215542a0d256SVille Syrjälä
215642a0d256SVille Syrjälä if (fb->format->is_yuv && fb->format->num_planes > 1) {
215742a0d256SVille Syrjälä ret = skl_build_plane_wm_uv(crtc_state, plane_state,
215842a0d256SVille Syrjälä plane);
215942a0d256SVille Syrjälä if (ret)
216042a0d256SVille Syrjälä return ret;
216142a0d256SVille Syrjälä }
216242a0d256SVille Syrjälä
216342a0d256SVille Syrjälä return 0;
216442a0d256SVille Syrjälä }
216542a0d256SVille Syrjälä
icl_build_plane_wm(struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)216642a0d256SVille Syrjälä static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
216742a0d256SVille Syrjälä const struct intel_plane_state *plane_state)
216842a0d256SVille Syrjälä {
216942a0d256SVille Syrjälä struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
217042a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(plane->base.dev);
217142a0d256SVille Syrjälä enum plane_id plane_id = plane->id;
217242a0d256SVille Syrjälä struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
217342a0d256SVille Syrjälä int ret;
217442a0d256SVille Syrjälä
217542a0d256SVille Syrjälä /* Watermarks calculated in master */
217642a0d256SVille Syrjälä if (plane_state->planar_slave)
217742a0d256SVille Syrjälä return 0;
217842a0d256SVille Syrjälä
217942a0d256SVille Syrjälä memset(wm, 0, sizeof(*wm));
218042a0d256SVille Syrjälä
218142a0d256SVille Syrjälä if (plane_state->planar_linked_plane) {
218242a0d256SVille Syrjälä const struct drm_framebuffer *fb = plane_state->hw.fb;
218342a0d256SVille Syrjälä
218442a0d256SVille Syrjälä drm_WARN_ON(&i915->drm,
218542a0d256SVille Syrjälä !intel_wm_plane_visible(crtc_state, plane_state));
218642a0d256SVille Syrjälä drm_WARN_ON(&i915->drm, !fb->format->is_yuv ||
218742a0d256SVille Syrjälä fb->format->num_planes == 1);
218842a0d256SVille Syrjälä
218942a0d256SVille Syrjälä ret = skl_build_plane_wm_single(crtc_state, plane_state,
219042a0d256SVille Syrjälä plane_state->planar_linked_plane, 0);
219142a0d256SVille Syrjälä if (ret)
219242a0d256SVille Syrjälä return ret;
219342a0d256SVille Syrjälä
219442a0d256SVille Syrjälä ret = skl_build_plane_wm_single(crtc_state, plane_state,
219542a0d256SVille Syrjälä plane, 1);
219642a0d256SVille Syrjälä if (ret)
219742a0d256SVille Syrjälä return ret;
219842a0d256SVille Syrjälä } else if (intel_wm_plane_visible(crtc_state, plane_state)) {
219942a0d256SVille Syrjälä ret = skl_build_plane_wm_single(crtc_state, plane_state,
220042a0d256SVille Syrjälä plane, 0);
220142a0d256SVille Syrjälä if (ret)
220242a0d256SVille Syrjälä return ret;
220342a0d256SVille Syrjälä }
220442a0d256SVille Syrjälä
220542a0d256SVille Syrjälä return 0;
220642a0d256SVille Syrjälä }
220742a0d256SVille Syrjälä
2208636f973cSVille Syrjälä static bool
skl_is_vblank_too_short(const struct intel_crtc_state * crtc_state,int wm0_lines,int latency)2209636f973cSVille Syrjälä skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
2210636f973cSVille Syrjälä int wm0_lines, int latency)
2211636f973cSVille Syrjälä {
2212636f973cSVille Syrjälä const struct drm_display_mode *adjusted_mode =
2213636f973cSVille Syrjälä &crtc_state->hw.adjusted_mode;
2214636f973cSVille Syrjälä
2215636f973cSVille Syrjälä /* FIXME missing scaler and DSC pre-fill time */
2216636f973cSVille Syrjälä return crtc_state->framestart_delay +
2217636f973cSVille Syrjälä intel_usecs_to_scanlines(adjusted_mode, latency) +
2218636f973cSVille Syrjälä wm0_lines >
2219636f973cSVille Syrjälä adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
2220636f973cSVille Syrjälä }
2221636f973cSVille Syrjälä
skl_max_wm0_lines(const struct intel_crtc_state * crtc_state)2222636f973cSVille Syrjälä static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
2223636f973cSVille Syrjälä {
2224636f973cSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2225636f973cSVille Syrjälä enum plane_id plane_id;
2226636f973cSVille Syrjälä int wm0_lines = 0;
2227636f973cSVille Syrjälä
2228636f973cSVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
2229636f973cSVille Syrjälä const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
2230636f973cSVille Syrjälä
2231636f973cSVille Syrjälä /* FIXME what about !skl_wm_has_lines() platforms? */
2232636f973cSVille Syrjälä wm0_lines = max_t(int, wm0_lines, wm->wm[0].lines);
2233636f973cSVille Syrjälä }
2234636f973cSVille Syrjälä
2235636f973cSVille Syrjälä return wm0_lines;
2236636f973cSVille Syrjälä }
2237636f973cSVille Syrjälä
skl_max_wm_level_for_vblank(struct intel_crtc_state * crtc_state,int wm0_lines)2238636f973cSVille Syrjälä static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
2239636f973cSVille Syrjälä int wm0_lines)
2240636f973cSVille Syrjälä {
2241636f973cSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2242636f973cSVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2243636f973cSVille Syrjälä int level;
2244636f973cSVille Syrjälä
2245636f973cSVille Syrjälä for (level = i915->display.wm.num_levels - 1; level >= 0; level--) {
2246636f973cSVille Syrjälä int latency;
2247636f973cSVille Syrjälä
2248636f973cSVille Syrjälä /* FIXME should we care about the latency w/a's? */
2249636f973cSVille Syrjälä latency = skl_wm_latency(i915, level, NULL);
2250636f973cSVille Syrjälä if (latency == 0)
2251636f973cSVille Syrjälä continue;
2252636f973cSVille Syrjälä
2253636f973cSVille Syrjälä /* FIXME is it correct to use 0 latency for wm0 here? */
2254636f973cSVille Syrjälä if (level == 0)
2255636f973cSVille Syrjälä latency = 0;
2256636f973cSVille Syrjälä
2257636f973cSVille Syrjälä if (!skl_is_vblank_too_short(crtc_state, wm0_lines, latency))
2258636f973cSVille Syrjälä return level;
2259636f973cSVille Syrjälä }
2260636f973cSVille Syrjälä
2261636f973cSVille Syrjälä return -EINVAL;
2262636f973cSVille Syrjälä }
2263636f973cSVille Syrjälä
skl_wm_check_vblank(struct intel_crtc_state * crtc_state)2264636f973cSVille Syrjälä static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
2265636f973cSVille Syrjälä {
2266636f973cSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2267636f973cSVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2268636f973cSVille Syrjälä int wm0_lines, level;
2269636f973cSVille Syrjälä
2270636f973cSVille Syrjälä if (!crtc_state->hw.active)
2271636f973cSVille Syrjälä return 0;
2272636f973cSVille Syrjälä
2273636f973cSVille Syrjälä wm0_lines = skl_max_wm0_lines(crtc_state);
2274636f973cSVille Syrjälä
2275636f973cSVille Syrjälä level = skl_max_wm_level_for_vblank(crtc_state, wm0_lines);
2276636f973cSVille Syrjälä if (level < 0)
2277636f973cSVille Syrjälä return level;
2278636f973cSVille Syrjälä
2279636f973cSVille Syrjälä /*
2280cdb015a6SJouni Högander * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
2281636f973cSVille Syrjälä * based on whether we're limited by the vblank duration.
2282cdb015a6SJouni Högander */
2283cdb015a6SJouni Högander crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
2284cdb015a6SJouni Högander
2285636f973cSVille Syrjälä for (level++; level < i915->display.wm.num_levels; level++) {
2286636f973cSVille Syrjälä enum plane_id plane_id;
2287636f973cSVille Syrjälä
2288636f973cSVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
2289636f973cSVille Syrjälä struct skl_plane_wm *wm =
2290636f973cSVille Syrjälä &crtc_state->wm.skl.optimal.planes[plane_id];
2291636f973cSVille Syrjälä
2292636f973cSVille Syrjälä /*
2293636f973cSVille Syrjälä * FIXME just clear enable or flag the entire
2294636f973cSVille Syrjälä * thing as bad via min_ddb_alloc=U16_MAX?
2295636f973cSVille Syrjälä */
2296636f973cSVille Syrjälä wm->wm[level].enable = false;
2297636f973cSVille Syrjälä wm->uv_wm[level].enable = false;
2298636f973cSVille Syrjälä }
2299636f973cSVille Syrjälä }
2300636f973cSVille Syrjälä
2301636f973cSVille Syrjälä if (DISPLAY_VER(i915) >= 12 &&
2302636f973cSVille Syrjälä i915->display.sagv.block_time_us &&
2303636f973cSVille Syrjälä skl_is_vblank_too_short(crtc_state, wm0_lines,
2304636f973cSVille Syrjälä i915->display.sagv.block_time_us)) {
2305636f973cSVille Syrjälä enum plane_id plane_id;
2306636f973cSVille Syrjälä
2307636f973cSVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
2308636f973cSVille Syrjälä struct skl_plane_wm *wm =
2309636f973cSVille Syrjälä &crtc_state->wm.skl.optimal.planes[plane_id];
2310636f973cSVille Syrjälä
2311636f973cSVille Syrjälä wm->sagv.wm0.enable = false;
2312636f973cSVille Syrjälä wm->sagv.trans_wm.enable = false;
2313636f973cSVille Syrjälä }
2314636f973cSVille Syrjälä }
2315636f973cSVille Syrjälä
2316636f973cSVille Syrjälä return 0;
2317636f973cSVille Syrjälä }
2318636f973cSVille Syrjälä
skl_build_pipe_wm(struct intel_atomic_state * state,struct intel_crtc * crtc)231942a0d256SVille Syrjälä static int skl_build_pipe_wm(struct intel_atomic_state *state,
232042a0d256SVille Syrjälä struct intel_crtc *crtc)
232142a0d256SVille Syrjälä {
232242a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
232342a0d256SVille Syrjälä struct intel_crtc_state *crtc_state =
232442a0d256SVille Syrjälä intel_atomic_get_new_crtc_state(state, crtc);
232542a0d256SVille Syrjälä const struct intel_plane_state *plane_state;
232642a0d256SVille Syrjälä struct intel_plane *plane;
232742a0d256SVille Syrjälä int ret, i;
232842a0d256SVille Syrjälä
232942a0d256SVille Syrjälä for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
233042a0d256SVille Syrjälä /*
233142a0d256SVille Syrjälä * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc
233242a0d256SVille Syrjälä * instead but we don't populate that correctly for NV12 Y
233342a0d256SVille Syrjälä * planes so for now hack this.
233442a0d256SVille Syrjälä */
233542a0d256SVille Syrjälä if (plane->pipe != crtc->pipe)
233642a0d256SVille Syrjälä continue;
233742a0d256SVille Syrjälä
233842a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 11)
233942a0d256SVille Syrjälä ret = icl_build_plane_wm(crtc_state, plane_state);
234042a0d256SVille Syrjälä else
234142a0d256SVille Syrjälä ret = skl_build_plane_wm(crtc_state, plane_state);
234242a0d256SVille Syrjälä if (ret)
234342a0d256SVille Syrjälä return ret;
234442a0d256SVille Syrjälä }
234542a0d256SVille Syrjälä
234642a0d256SVille Syrjälä crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;
234742a0d256SVille Syrjälä
2348636f973cSVille Syrjälä return skl_wm_check_vblank(crtc_state);
234942a0d256SVille Syrjälä }
235042a0d256SVille Syrjälä
skl_ddb_entry_write(struct drm_i915_private * i915,i915_reg_t reg,const struct skl_ddb_entry * entry)235142a0d256SVille Syrjälä static void skl_ddb_entry_write(struct drm_i915_private *i915,
235242a0d256SVille Syrjälä i915_reg_t reg,
235342a0d256SVille Syrjälä const struct skl_ddb_entry *entry)
235442a0d256SVille Syrjälä {
235542a0d256SVille Syrjälä if (entry->end)
235642a0d256SVille Syrjälä intel_de_write_fw(i915, reg,
235742a0d256SVille Syrjälä PLANE_BUF_END(entry->end - 1) |
235842a0d256SVille Syrjälä PLANE_BUF_START(entry->start));
235942a0d256SVille Syrjälä else
236042a0d256SVille Syrjälä intel_de_write_fw(i915, reg, 0);
236142a0d256SVille Syrjälä }
236242a0d256SVille Syrjälä
skl_write_wm_level(struct drm_i915_private * i915,i915_reg_t reg,const struct skl_wm_level * level)236342a0d256SVille Syrjälä static void skl_write_wm_level(struct drm_i915_private *i915,
236442a0d256SVille Syrjälä i915_reg_t reg,
236542a0d256SVille Syrjälä const struct skl_wm_level *level)
236642a0d256SVille Syrjälä {
236742a0d256SVille Syrjälä u32 val = 0;
236842a0d256SVille Syrjälä
236942a0d256SVille Syrjälä if (level->enable)
237042a0d256SVille Syrjälä val |= PLANE_WM_EN;
237142a0d256SVille Syrjälä if (level->ignore_lines)
237242a0d256SVille Syrjälä val |= PLANE_WM_IGNORE_LINES;
237342a0d256SVille Syrjälä val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
237442a0d256SVille Syrjälä val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
237542a0d256SVille Syrjälä
237642a0d256SVille Syrjälä intel_de_write_fw(i915, reg, val);
237742a0d256SVille Syrjälä }
237842a0d256SVille Syrjälä
skl_write_plane_wm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state)237942a0d256SVille Syrjälä void skl_write_plane_wm(struct intel_plane *plane,
238042a0d256SVille Syrjälä const struct intel_crtc_state *crtc_state)
238142a0d256SVille Syrjälä {
238242a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(plane->base.dev);
238342a0d256SVille Syrjälä enum plane_id plane_id = plane->id;
238442a0d256SVille Syrjälä enum pipe pipe = plane->pipe;
238542a0d256SVille Syrjälä const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
238642a0d256SVille Syrjälä const struct skl_ddb_entry *ddb =
238742a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb[plane_id];
238842a0d256SVille Syrjälä const struct skl_ddb_entry *ddb_y =
238942a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb_y[plane_id];
23907ee6f99dSVille Syrjälä int level;
239142a0d256SVille Syrjälä
23927ee6f99dSVille Syrjälä for (level = 0; level < i915->display.wm.num_levels; level++)
239342a0d256SVille Syrjälä skl_write_wm_level(i915, PLANE_WM(pipe, plane_id, level),
239442a0d256SVille Syrjälä skl_plane_wm_level(pipe_wm, plane_id, level));
239542a0d256SVille Syrjälä
239642a0d256SVille Syrjälä skl_write_wm_level(i915, PLANE_WM_TRANS(pipe, plane_id),
239742a0d256SVille Syrjälä skl_plane_trans_wm(pipe_wm, plane_id));
239842a0d256SVille Syrjälä
239942a0d256SVille Syrjälä if (HAS_HW_SAGV_WM(i915)) {
240042a0d256SVille Syrjälä const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
240142a0d256SVille Syrjälä
240242a0d256SVille Syrjälä skl_write_wm_level(i915, PLANE_WM_SAGV(pipe, plane_id),
240342a0d256SVille Syrjälä &wm->sagv.wm0);
240442a0d256SVille Syrjälä skl_write_wm_level(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
240542a0d256SVille Syrjälä &wm->sagv.trans_wm);
240642a0d256SVille Syrjälä }
240742a0d256SVille Syrjälä
240842a0d256SVille Syrjälä skl_ddb_entry_write(i915,
240942a0d256SVille Syrjälä PLANE_BUF_CFG(pipe, plane_id), ddb);
241042a0d256SVille Syrjälä
241142a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 11)
241242a0d256SVille Syrjälä skl_ddb_entry_write(i915,
241342a0d256SVille Syrjälä PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
241442a0d256SVille Syrjälä }
241542a0d256SVille Syrjälä
skl_write_cursor_wm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state)241642a0d256SVille Syrjälä void skl_write_cursor_wm(struct intel_plane *plane,
241742a0d256SVille Syrjälä const struct intel_crtc_state *crtc_state)
241842a0d256SVille Syrjälä {
241942a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(plane->base.dev);
242042a0d256SVille Syrjälä enum plane_id plane_id = plane->id;
242142a0d256SVille Syrjälä enum pipe pipe = plane->pipe;
242242a0d256SVille Syrjälä const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
242342a0d256SVille Syrjälä const struct skl_ddb_entry *ddb =
242442a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb[plane_id];
24257ee6f99dSVille Syrjälä int level;
242642a0d256SVille Syrjälä
24277ee6f99dSVille Syrjälä for (level = 0; level < i915->display.wm.num_levels; level++)
242842a0d256SVille Syrjälä skl_write_wm_level(i915, CUR_WM(pipe, level),
242942a0d256SVille Syrjälä skl_plane_wm_level(pipe_wm, plane_id, level));
243042a0d256SVille Syrjälä
243142a0d256SVille Syrjälä skl_write_wm_level(i915, CUR_WM_TRANS(pipe),
243242a0d256SVille Syrjälä skl_plane_trans_wm(pipe_wm, plane_id));
243342a0d256SVille Syrjälä
243442a0d256SVille Syrjälä if (HAS_HW_SAGV_WM(i915)) {
243542a0d256SVille Syrjälä const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
243642a0d256SVille Syrjälä
243742a0d256SVille Syrjälä skl_write_wm_level(i915, CUR_WM_SAGV(pipe),
243842a0d256SVille Syrjälä &wm->sagv.wm0);
243942a0d256SVille Syrjälä skl_write_wm_level(i915, CUR_WM_SAGV_TRANS(pipe),
244042a0d256SVille Syrjälä &wm->sagv.trans_wm);
244142a0d256SVille Syrjälä }
244242a0d256SVille Syrjälä
244342a0d256SVille Syrjälä skl_ddb_entry_write(i915, CUR_BUF_CFG(pipe), ddb);
244442a0d256SVille Syrjälä }
244542a0d256SVille Syrjälä
skl_wm_level_equals(const struct skl_wm_level * l1,const struct skl_wm_level * l2)244642a0d256SVille Syrjälä static bool skl_wm_level_equals(const struct skl_wm_level *l1,
244742a0d256SVille Syrjälä const struct skl_wm_level *l2)
244842a0d256SVille Syrjälä {
244942a0d256SVille Syrjälä return l1->enable == l2->enable &&
245042a0d256SVille Syrjälä l1->ignore_lines == l2->ignore_lines &&
245142a0d256SVille Syrjälä l1->lines == l2->lines &&
245242a0d256SVille Syrjälä l1->blocks == l2->blocks;
245342a0d256SVille Syrjälä }
245442a0d256SVille Syrjälä
skl_plane_wm_equals(struct drm_i915_private * i915,const struct skl_plane_wm * wm1,const struct skl_plane_wm * wm2)245542a0d256SVille Syrjälä static bool skl_plane_wm_equals(struct drm_i915_private *i915,
245642a0d256SVille Syrjälä const struct skl_plane_wm *wm1,
245742a0d256SVille Syrjälä const struct skl_plane_wm *wm2)
245842a0d256SVille Syrjälä {
24597ee6f99dSVille Syrjälä int level;
246042a0d256SVille Syrjälä
24617ee6f99dSVille Syrjälä for (level = 0; level < i915->display.wm.num_levels; level++) {
246242a0d256SVille Syrjälä /*
246342a0d256SVille Syrjälä * We don't check uv_wm as the hardware doesn't actually
246442a0d256SVille Syrjälä * use it. It only gets used for calculating the required
246542a0d256SVille Syrjälä * ddb allocation.
246642a0d256SVille Syrjälä */
246742a0d256SVille Syrjälä if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
246842a0d256SVille Syrjälä return false;
246942a0d256SVille Syrjälä }
247042a0d256SVille Syrjälä
247142a0d256SVille Syrjälä return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) &&
247242a0d256SVille Syrjälä skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0) &&
247342a0d256SVille Syrjälä skl_wm_level_equals(&wm1->sagv.trans_wm, &wm2->sagv.trans_wm);
247442a0d256SVille Syrjälä }
247542a0d256SVille Syrjälä
skl_ddb_entries_overlap(const struct skl_ddb_entry * a,const struct skl_ddb_entry * b)247642a0d256SVille Syrjälä static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
247742a0d256SVille Syrjälä const struct skl_ddb_entry *b)
247842a0d256SVille Syrjälä {
247942a0d256SVille Syrjälä return a->start < b->end && b->start < a->end;
248042a0d256SVille Syrjälä }
248142a0d256SVille Syrjälä
skl_ddb_entry_union(struct skl_ddb_entry * a,const struct skl_ddb_entry * b)248242a0d256SVille Syrjälä static void skl_ddb_entry_union(struct skl_ddb_entry *a,
248342a0d256SVille Syrjälä const struct skl_ddb_entry *b)
248442a0d256SVille Syrjälä {
248542a0d256SVille Syrjälä if (a->end && b->end) {
248642a0d256SVille Syrjälä a->start = min(a->start, b->start);
248742a0d256SVille Syrjälä a->end = max(a->end, b->end);
248842a0d256SVille Syrjälä } else if (b->end) {
248942a0d256SVille Syrjälä a->start = b->start;
249042a0d256SVille Syrjälä a->end = b->end;
249142a0d256SVille Syrjälä }
249242a0d256SVille Syrjälä }
249342a0d256SVille Syrjälä
skl_ddb_allocation_overlaps(const struct skl_ddb_entry * ddb,const struct skl_ddb_entry * entries,int num_entries,int ignore_idx)249442a0d256SVille Syrjälä bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
249542a0d256SVille Syrjälä const struct skl_ddb_entry *entries,
249642a0d256SVille Syrjälä int num_entries, int ignore_idx)
249742a0d256SVille Syrjälä {
249842a0d256SVille Syrjälä int i;
249942a0d256SVille Syrjälä
250042a0d256SVille Syrjälä for (i = 0; i < num_entries; i++) {
250142a0d256SVille Syrjälä if (i != ignore_idx &&
250242a0d256SVille Syrjälä skl_ddb_entries_overlap(ddb, &entries[i]))
250342a0d256SVille Syrjälä return true;
250442a0d256SVille Syrjälä }
250542a0d256SVille Syrjälä
250642a0d256SVille Syrjälä return false;
250742a0d256SVille Syrjälä }
250842a0d256SVille Syrjälä
250942a0d256SVille Syrjälä static int
skl_ddb_add_affected_planes(const struct intel_crtc_state * old_crtc_state,struct intel_crtc_state * new_crtc_state)251042a0d256SVille Syrjälä skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
251142a0d256SVille Syrjälä struct intel_crtc_state *new_crtc_state)
251242a0d256SVille Syrjälä {
251342a0d256SVille Syrjälä struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
251442a0d256SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
251542a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
251642a0d256SVille Syrjälä struct intel_plane *plane;
251742a0d256SVille Syrjälä
251842a0d256SVille Syrjälä for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
251942a0d256SVille Syrjälä struct intel_plane_state *plane_state;
252042a0d256SVille Syrjälä enum plane_id plane_id = plane->id;
252142a0d256SVille Syrjälä
252242a0d256SVille Syrjälä if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id],
252342a0d256SVille Syrjälä &new_crtc_state->wm.skl.plane_ddb[plane_id]) &&
252442a0d256SVille Syrjälä skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
252542a0d256SVille Syrjälä &new_crtc_state->wm.skl.plane_ddb_y[plane_id]))
252642a0d256SVille Syrjälä continue;
252742a0d256SVille Syrjälä
252842a0d256SVille Syrjälä plane_state = intel_atomic_get_plane_state(state, plane);
252942a0d256SVille Syrjälä if (IS_ERR(plane_state))
253042a0d256SVille Syrjälä return PTR_ERR(plane_state);
253142a0d256SVille Syrjälä
253242a0d256SVille Syrjälä new_crtc_state->update_planes |= BIT(plane_id);
25339d691c19SAndrzej Hajda new_crtc_state->async_flip_planes = 0;
25349d691c19SAndrzej Hajda new_crtc_state->do_async_flip = false;
253542a0d256SVille Syrjälä }
253642a0d256SVille Syrjälä
253742a0d256SVille Syrjälä return 0;
253842a0d256SVille Syrjälä }
253942a0d256SVille Syrjälä
intel_dbuf_enabled_slices(const struct intel_dbuf_state * dbuf_state)254042a0d256SVille Syrjälä static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state)
254142a0d256SVille Syrjälä {
254242a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(dbuf_state->base.state->base.dev);
254342a0d256SVille Syrjälä u8 enabled_slices;
254442a0d256SVille Syrjälä enum pipe pipe;
254542a0d256SVille Syrjälä
254642a0d256SVille Syrjälä /*
254742a0d256SVille Syrjälä * FIXME: For now we always enable slice S1 as per
254842a0d256SVille Syrjälä * the Bspec display initialization sequence.
254942a0d256SVille Syrjälä */
255042a0d256SVille Syrjälä enabled_slices = BIT(DBUF_S1);
255142a0d256SVille Syrjälä
255242a0d256SVille Syrjälä for_each_pipe(i915, pipe)
255342a0d256SVille Syrjälä enabled_slices |= dbuf_state->slices[pipe];
255442a0d256SVille Syrjälä
255542a0d256SVille Syrjälä return enabled_slices;
255642a0d256SVille Syrjälä }
255742a0d256SVille Syrjälä
255842a0d256SVille Syrjälä static int
skl_compute_ddb(struct intel_atomic_state * state)255942a0d256SVille Syrjälä skl_compute_ddb(struct intel_atomic_state *state)
256042a0d256SVille Syrjälä {
256142a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
256242a0d256SVille Syrjälä const struct intel_dbuf_state *old_dbuf_state;
256342a0d256SVille Syrjälä struct intel_dbuf_state *new_dbuf_state = NULL;
256442a0d256SVille Syrjälä const struct intel_crtc_state *old_crtc_state;
256542a0d256SVille Syrjälä struct intel_crtc_state *new_crtc_state;
256642a0d256SVille Syrjälä struct intel_crtc *crtc;
256742a0d256SVille Syrjälä int ret, i;
256842a0d256SVille Syrjälä
256942a0d256SVille Syrjälä for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
257042a0d256SVille Syrjälä new_dbuf_state = intel_atomic_get_dbuf_state(state);
257142a0d256SVille Syrjälä if (IS_ERR(new_dbuf_state))
257242a0d256SVille Syrjälä return PTR_ERR(new_dbuf_state);
257342a0d256SVille Syrjälä
257442a0d256SVille Syrjälä old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
257542a0d256SVille Syrjälä break;
257642a0d256SVille Syrjälä }
257742a0d256SVille Syrjälä
257842a0d256SVille Syrjälä if (!new_dbuf_state)
257942a0d256SVille Syrjälä return 0;
258042a0d256SVille Syrjälä
258142a0d256SVille Syrjälä new_dbuf_state->active_pipes =
258242a0d256SVille Syrjälä intel_calc_active_pipes(state, old_dbuf_state->active_pipes);
258342a0d256SVille Syrjälä
258442a0d256SVille Syrjälä if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) {
258542a0d256SVille Syrjälä ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
258642a0d256SVille Syrjälä if (ret)
258742a0d256SVille Syrjälä return ret;
258842a0d256SVille Syrjälä }
258942a0d256SVille Syrjälä
259042a0d256SVille Syrjälä if (HAS_MBUS_JOINING(i915))
259142a0d256SVille Syrjälä new_dbuf_state->joined_mbus =
259242a0d256SVille Syrjälä adlp_check_mbus_joined(new_dbuf_state->active_pipes);
259342a0d256SVille Syrjälä
259442a0d256SVille Syrjälä for_each_intel_crtc(&i915->drm, crtc) {
259542a0d256SVille Syrjälä enum pipe pipe = crtc->pipe;
259642a0d256SVille Syrjälä
259742a0d256SVille Syrjälä new_dbuf_state->slices[pipe] =
259842a0d256SVille Syrjälä skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes,
259942a0d256SVille Syrjälä new_dbuf_state->joined_mbus);
260042a0d256SVille Syrjälä
260142a0d256SVille Syrjälä if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe])
260242a0d256SVille Syrjälä continue;
260342a0d256SVille Syrjälä
260442a0d256SVille Syrjälä ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
260542a0d256SVille Syrjälä if (ret)
260642a0d256SVille Syrjälä return ret;
260742a0d256SVille Syrjälä }
260842a0d256SVille Syrjälä
260942a0d256SVille Syrjälä new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state);
261042a0d256SVille Syrjälä
261142a0d256SVille Syrjälä if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices ||
261242a0d256SVille Syrjälä old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
261342a0d256SVille Syrjälä ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
261442a0d256SVille Syrjälä if (ret)
261542a0d256SVille Syrjälä return ret;
261642a0d256SVille Syrjälä
261742a0d256SVille Syrjälä if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
261842a0d256SVille Syrjälä /* TODO: Implement vblank synchronized MBUS joining changes */
26190c316114SVille Syrjälä ret = intel_modeset_all_pipes(state, "MBUS joining change");
262042a0d256SVille Syrjälä if (ret)
262142a0d256SVille Syrjälä return ret;
262242a0d256SVille Syrjälä }
262342a0d256SVille Syrjälä
262442a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
262542a0d256SVille Syrjälä "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
262642a0d256SVille Syrjälä old_dbuf_state->enabled_slices,
262742a0d256SVille Syrjälä new_dbuf_state->enabled_slices,
26285af5169dSMatt Roper DISPLAY_INFO(i915)->dbuf.slice_mask,
262942a0d256SVille Syrjälä str_yes_no(old_dbuf_state->joined_mbus),
263042a0d256SVille Syrjälä str_yes_no(new_dbuf_state->joined_mbus));
263142a0d256SVille Syrjälä }
263242a0d256SVille Syrjälä
263342a0d256SVille Syrjälä for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
263442a0d256SVille Syrjälä enum pipe pipe = crtc->pipe;
263542a0d256SVille Syrjälä
263642a0d256SVille Syrjälä new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state);
263742a0d256SVille Syrjälä
263842a0d256SVille Syrjälä if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe])
263942a0d256SVille Syrjälä continue;
264042a0d256SVille Syrjälä
264142a0d256SVille Syrjälä ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
264242a0d256SVille Syrjälä if (ret)
264342a0d256SVille Syrjälä return ret;
264442a0d256SVille Syrjälä }
264542a0d256SVille Syrjälä
264642a0d256SVille Syrjälä for_each_intel_crtc(&i915->drm, crtc) {
264742a0d256SVille Syrjälä ret = skl_crtc_allocate_ddb(state, crtc);
264842a0d256SVille Syrjälä if (ret)
264942a0d256SVille Syrjälä return ret;
265042a0d256SVille Syrjälä }
265142a0d256SVille Syrjälä
265242a0d256SVille Syrjälä for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
265342a0d256SVille Syrjälä new_crtc_state, i) {
265442a0d256SVille Syrjälä ret = skl_crtc_allocate_plane_ddb(state, crtc);
265542a0d256SVille Syrjälä if (ret)
265642a0d256SVille Syrjälä return ret;
265742a0d256SVille Syrjälä
265842a0d256SVille Syrjälä ret = skl_ddb_add_affected_planes(old_crtc_state,
265942a0d256SVille Syrjälä new_crtc_state);
266042a0d256SVille Syrjälä if (ret)
266142a0d256SVille Syrjälä return ret;
266242a0d256SVille Syrjälä }
266342a0d256SVille Syrjälä
266442a0d256SVille Syrjälä return 0;
266542a0d256SVille Syrjälä }
266642a0d256SVille Syrjälä
enast(bool enable)266742a0d256SVille Syrjälä static char enast(bool enable)
266842a0d256SVille Syrjälä {
266942a0d256SVille Syrjälä return enable ? '*' : ' ';
267042a0d256SVille Syrjälä }
267142a0d256SVille Syrjälä
267242a0d256SVille Syrjälä static void
skl_print_wm_changes(struct intel_atomic_state * state)267342a0d256SVille Syrjälä skl_print_wm_changes(struct intel_atomic_state *state)
267442a0d256SVille Syrjälä {
267542a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
267642a0d256SVille Syrjälä const struct intel_crtc_state *old_crtc_state;
267742a0d256SVille Syrjälä const struct intel_crtc_state *new_crtc_state;
267842a0d256SVille Syrjälä struct intel_plane *plane;
267942a0d256SVille Syrjälä struct intel_crtc *crtc;
268042a0d256SVille Syrjälä int i;
268142a0d256SVille Syrjälä
268242a0d256SVille Syrjälä if (!drm_debug_enabled(DRM_UT_KMS))
268342a0d256SVille Syrjälä return;
268442a0d256SVille Syrjälä
268542a0d256SVille Syrjälä for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
268642a0d256SVille Syrjälä new_crtc_state, i) {
268742a0d256SVille Syrjälä const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm;
268842a0d256SVille Syrjälä
268942a0d256SVille Syrjälä old_pipe_wm = &old_crtc_state->wm.skl.optimal;
269042a0d256SVille Syrjälä new_pipe_wm = &new_crtc_state->wm.skl.optimal;
269142a0d256SVille Syrjälä
269242a0d256SVille Syrjälä for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
269342a0d256SVille Syrjälä enum plane_id plane_id = plane->id;
269442a0d256SVille Syrjälä const struct skl_ddb_entry *old, *new;
269542a0d256SVille Syrjälä
269642a0d256SVille Syrjälä old = &old_crtc_state->wm.skl.plane_ddb[plane_id];
269742a0d256SVille Syrjälä new = &new_crtc_state->wm.skl.plane_ddb[plane_id];
269842a0d256SVille Syrjälä
269942a0d256SVille Syrjälä if (skl_ddb_entry_equal(old, new))
270042a0d256SVille Syrjälä continue;
270142a0d256SVille Syrjälä
270242a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
270342a0d256SVille Syrjälä "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
270442a0d256SVille Syrjälä plane->base.base.id, plane->base.name,
270542a0d256SVille Syrjälä old->start, old->end, new->start, new->end,
270642a0d256SVille Syrjälä skl_ddb_entry_size(old), skl_ddb_entry_size(new));
270742a0d256SVille Syrjälä }
270842a0d256SVille Syrjälä
270942a0d256SVille Syrjälä for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
271042a0d256SVille Syrjälä enum plane_id plane_id = plane->id;
271142a0d256SVille Syrjälä const struct skl_plane_wm *old_wm, *new_wm;
271242a0d256SVille Syrjälä
271342a0d256SVille Syrjälä old_wm = &old_pipe_wm->planes[plane_id];
271442a0d256SVille Syrjälä new_wm = &new_pipe_wm->planes[plane_id];
271542a0d256SVille Syrjälä
271642a0d256SVille Syrjälä if (skl_plane_wm_equals(i915, old_wm, new_wm))
271742a0d256SVille Syrjälä continue;
271842a0d256SVille Syrjälä
271942a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
272042a0d256SVille Syrjälä "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
272142a0d256SVille Syrjälä " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
272242a0d256SVille Syrjälä plane->base.base.id, plane->base.name,
272342a0d256SVille Syrjälä enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
272442a0d256SVille Syrjälä enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable),
272542a0d256SVille Syrjälä enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable),
272642a0d256SVille Syrjälä enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable),
272742a0d256SVille Syrjälä enast(old_wm->trans_wm.enable),
272842a0d256SVille Syrjälä enast(old_wm->sagv.wm0.enable),
272942a0d256SVille Syrjälä enast(old_wm->sagv.trans_wm.enable),
273042a0d256SVille Syrjälä enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable),
273142a0d256SVille Syrjälä enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable),
273242a0d256SVille Syrjälä enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable),
273342a0d256SVille Syrjälä enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable),
273442a0d256SVille Syrjälä enast(new_wm->trans_wm.enable),
273542a0d256SVille Syrjälä enast(new_wm->sagv.wm0.enable),
273642a0d256SVille Syrjälä enast(new_wm->sagv.trans_wm.enable));
273742a0d256SVille Syrjälä
273842a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
273942a0d256SVille Syrjälä "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
274042a0d256SVille Syrjälä " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
274142a0d256SVille Syrjälä plane->base.base.id, plane->base.name,
274242a0d256SVille Syrjälä enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
274342a0d256SVille Syrjälä enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines,
274442a0d256SVille Syrjälä enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines,
274542a0d256SVille Syrjälä enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines,
274642a0d256SVille Syrjälä enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines,
274742a0d256SVille Syrjälä enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines,
274842a0d256SVille Syrjälä enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines,
274942a0d256SVille Syrjälä enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines,
275042a0d256SVille Syrjälä enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines,
275142a0d256SVille Syrjälä enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines,
275242a0d256SVille Syrjälä enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines,
275342a0d256SVille Syrjälä enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines,
275442a0d256SVille Syrjälä enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines,
275542a0d256SVille Syrjälä enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines,
275642a0d256SVille Syrjälä enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines,
275742a0d256SVille Syrjälä enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines,
275842a0d256SVille Syrjälä enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines,
275942a0d256SVille Syrjälä enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines,
276042a0d256SVille Syrjälä enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines,
276142a0d256SVille Syrjälä enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines,
276242a0d256SVille Syrjälä enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines,
276342a0d256SVille Syrjälä enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
276442a0d256SVille Syrjälä
276542a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
276642a0d256SVille Syrjälä "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
276742a0d256SVille Syrjälä " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
276842a0d256SVille Syrjälä plane->base.base.id, plane->base.name,
276942a0d256SVille Syrjälä old_wm->wm[0].blocks, old_wm->wm[1].blocks,
277042a0d256SVille Syrjälä old_wm->wm[2].blocks, old_wm->wm[3].blocks,
277142a0d256SVille Syrjälä old_wm->wm[4].blocks, old_wm->wm[5].blocks,
277242a0d256SVille Syrjälä old_wm->wm[6].blocks, old_wm->wm[7].blocks,
277342a0d256SVille Syrjälä old_wm->trans_wm.blocks,
277442a0d256SVille Syrjälä old_wm->sagv.wm0.blocks,
277542a0d256SVille Syrjälä old_wm->sagv.trans_wm.blocks,
277642a0d256SVille Syrjälä new_wm->wm[0].blocks, new_wm->wm[1].blocks,
277742a0d256SVille Syrjälä new_wm->wm[2].blocks, new_wm->wm[3].blocks,
277842a0d256SVille Syrjälä new_wm->wm[4].blocks, new_wm->wm[5].blocks,
277942a0d256SVille Syrjälä new_wm->wm[6].blocks, new_wm->wm[7].blocks,
278042a0d256SVille Syrjälä new_wm->trans_wm.blocks,
278142a0d256SVille Syrjälä new_wm->sagv.wm0.blocks,
278242a0d256SVille Syrjälä new_wm->sagv.trans_wm.blocks);
278342a0d256SVille Syrjälä
278442a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
278542a0d256SVille Syrjälä "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
278642a0d256SVille Syrjälä " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
278742a0d256SVille Syrjälä plane->base.base.id, plane->base.name,
278842a0d256SVille Syrjälä old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
278942a0d256SVille Syrjälä old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
279042a0d256SVille Syrjälä old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
279142a0d256SVille Syrjälä old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
279242a0d256SVille Syrjälä old_wm->trans_wm.min_ddb_alloc,
279342a0d256SVille Syrjälä old_wm->sagv.wm0.min_ddb_alloc,
279442a0d256SVille Syrjälä old_wm->sagv.trans_wm.min_ddb_alloc,
279542a0d256SVille Syrjälä new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
279642a0d256SVille Syrjälä new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
279742a0d256SVille Syrjälä new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
279842a0d256SVille Syrjälä new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
279942a0d256SVille Syrjälä new_wm->trans_wm.min_ddb_alloc,
280042a0d256SVille Syrjälä new_wm->sagv.wm0.min_ddb_alloc,
280142a0d256SVille Syrjälä new_wm->sagv.trans_wm.min_ddb_alloc);
280242a0d256SVille Syrjälä }
280342a0d256SVille Syrjälä }
280442a0d256SVille Syrjälä }
280542a0d256SVille Syrjälä
skl_plane_selected_wm_equals(struct intel_plane * plane,const struct skl_pipe_wm * old_pipe_wm,const struct skl_pipe_wm * new_pipe_wm)280642a0d256SVille Syrjälä static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
280742a0d256SVille Syrjälä const struct skl_pipe_wm *old_pipe_wm,
280842a0d256SVille Syrjälä const struct skl_pipe_wm *new_pipe_wm)
280942a0d256SVille Syrjälä {
281042a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(plane->base.dev);
28117ee6f99dSVille Syrjälä int level;
281242a0d256SVille Syrjälä
28137ee6f99dSVille Syrjälä for (level = 0; level < i915->display.wm.num_levels; level++) {
281442a0d256SVille Syrjälä /*
281542a0d256SVille Syrjälä * We don't check uv_wm as the hardware doesn't actually
281642a0d256SVille Syrjälä * use it. It only gets used for calculating the required
281742a0d256SVille Syrjälä * ddb allocation.
281842a0d256SVille Syrjälä */
281942a0d256SVille Syrjälä if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level),
282042a0d256SVille Syrjälä skl_plane_wm_level(new_pipe_wm, plane->id, level)))
282142a0d256SVille Syrjälä return false;
282242a0d256SVille Syrjälä }
282342a0d256SVille Syrjälä
282442a0d256SVille Syrjälä if (HAS_HW_SAGV_WM(i915)) {
282542a0d256SVille Syrjälä const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];
282642a0d256SVille Syrjälä const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];
282742a0d256SVille Syrjälä
282842a0d256SVille Syrjälä if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) ||
282942a0d256SVille Syrjälä !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm))
283042a0d256SVille Syrjälä return false;
283142a0d256SVille Syrjälä }
283242a0d256SVille Syrjälä
283342a0d256SVille Syrjälä return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id),
283442a0d256SVille Syrjälä skl_plane_trans_wm(new_pipe_wm, plane->id));
283542a0d256SVille Syrjälä }
283642a0d256SVille Syrjälä
283742a0d256SVille Syrjälä /*
283842a0d256SVille Syrjälä * To make sure the cursor watermark registers are always consistent
283942a0d256SVille Syrjälä * with our computed state the following scenario needs special
284042a0d256SVille Syrjälä * treatment:
284142a0d256SVille Syrjälä *
284242a0d256SVille Syrjälä * 1. enable cursor
284342a0d256SVille Syrjälä * 2. move cursor entirely offscreen
284442a0d256SVille Syrjälä * 3. disable cursor
284542a0d256SVille Syrjälä *
284642a0d256SVille Syrjälä * Step 2. does call .disable_plane() but does not zero the watermarks
284742a0d256SVille Syrjälä * (since we consider an offscreen cursor still active for the purposes
284842a0d256SVille Syrjälä * of watermarks). Step 3. would not normally call .disable_plane()
284942a0d256SVille Syrjälä * because the actual plane visibility isn't changing, and we don't
285042a0d256SVille Syrjälä * deallocate the cursor ddb until the pipe gets disabled. So we must
285142a0d256SVille Syrjälä * force step 3. to call .disable_plane() to update the watermark
285242a0d256SVille Syrjälä * registers properly.
285342a0d256SVille Syrjälä *
285442a0d256SVille Syrjälä * Other planes do not suffer from this issues as their watermarks are
285542a0d256SVille Syrjälä * calculated based on the actual plane visibility. The only time this
285642a0d256SVille Syrjälä * can trigger for the other planes is during the initial readout as the
285742a0d256SVille Syrjälä * default value of the watermarks registers is not zero.
285842a0d256SVille Syrjälä */
skl_wm_add_affected_planes(struct intel_atomic_state * state,struct intel_crtc * crtc)285942a0d256SVille Syrjälä static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
286042a0d256SVille Syrjälä struct intel_crtc *crtc)
286142a0d256SVille Syrjälä {
286242a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
286342a0d256SVille Syrjälä const struct intel_crtc_state *old_crtc_state =
286442a0d256SVille Syrjälä intel_atomic_get_old_crtc_state(state, crtc);
286542a0d256SVille Syrjälä struct intel_crtc_state *new_crtc_state =
286642a0d256SVille Syrjälä intel_atomic_get_new_crtc_state(state, crtc);
286742a0d256SVille Syrjälä struct intel_plane *plane;
286842a0d256SVille Syrjälä
286942a0d256SVille Syrjälä for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
287042a0d256SVille Syrjälä struct intel_plane_state *plane_state;
287142a0d256SVille Syrjälä enum plane_id plane_id = plane->id;
287242a0d256SVille Syrjälä
287342a0d256SVille Syrjälä /*
287442a0d256SVille Syrjälä * Force a full wm update for every plane on modeset.
287542a0d256SVille Syrjälä * Required because the reset value of the wm registers
287642a0d256SVille Syrjälä * is non-zero, whereas we want all disabled planes to
287742a0d256SVille Syrjälä * have zero watermarks. So if we turn off the relevant
287842a0d256SVille Syrjälä * power well the hardware state will go out of sync
287942a0d256SVille Syrjälä * with the software state.
288042a0d256SVille Syrjälä */
2881882ecff7SVille Syrjälä if (!intel_crtc_needs_modeset(new_crtc_state) &&
288242a0d256SVille Syrjälä skl_plane_selected_wm_equals(plane,
288342a0d256SVille Syrjälä &old_crtc_state->wm.skl.optimal,
288442a0d256SVille Syrjälä &new_crtc_state->wm.skl.optimal))
288542a0d256SVille Syrjälä continue;
288642a0d256SVille Syrjälä
288742a0d256SVille Syrjälä plane_state = intel_atomic_get_plane_state(state, plane);
288842a0d256SVille Syrjälä if (IS_ERR(plane_state))
288942a0d256SVille Syrjälä return PTR_ERR(plane_state);
289042a0d256SVille Syrjälä
289142a0d256SVille Syrjälä new_crtc_state->update_planes |= BIT(plane_id);
28929d691c19SAndrzej Hajda new_crtc_state->async_flip_planes = 0;
28939d691c19SAndrzej Hajda new_crtc_state->do_async_flip = false;
289442a0d256SVille Syrjälä }
289542a0d256SVille Syrjälä
289642a0d256SVille Syrjälä return 0;
289742a0d256SVille Syrjälä }
289842a0d256SVille Syrjälä
289942a0d256SVille Syrjälä static int
skl_compute_wm(struct intel_atomic_state * state)290042a0d256SVille Syrjälä skl_compute_wm(struct intel_atomic_state *state)
290142a0d256SVille Syrjälä {
290242a0d256SVille Syrjälä struct intel_crtc *crtc;
2903*84f9c3c7SJani Nikula struct intel_crtc_state __maybe_unused *new_crtc_state;
290442a0d256SVille Syrjälä int ret, i;
290542a0d256SVille Syrjälä
290642a0d256SVille Syrjälä for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
290742a0d256SVille Syrjälä ret = skl_build_pipe_wm(state, crtc);
290842a0d256SVille Syrjälä if (ret)
290942a0d256SVille Syrjälä return ret;
291042a0d256SVille Syrjälä }
291142a0d256SVille Syrjälä
291242a0d256SVille Syrjälä ret = skl_compute_ddb(state);
291342a0d256SVille Syrjälä if (ret)
291442a0d256SVille Syrjälä return ret;
291542a0d256SVille Syrjälä
291642a0d256SVille Syrjälä ret = intel_compute_sagv_mask(state);
291742a0d256SVille Syrjälä if (ret)
291842a0d256SVille Syrjälä return ret;
291942a0d256SVille Syrjälä
292042a0d256SVille Syrjälä /*
292142a0d256SVille Syrjälä * skl_compute_ddb() will have adjusted the final watermarks
292242a0d256SVille Syrjälä * based on how much ddb is available. Now we can actually
292342a0d256SVille Syrjälä * check if the final watermarks changed.
292442a0d256SVille Syrjälä */
292542a0d256SVille Syrjälä for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
292642a0d256SVille Syrjälä ret = skl_wm_add_affected_planes(state, crtc);
292742a0d256SVille Syrjälä if (ret)
292842a0d256SVille Syrjälä return ret;
292942a0d256SVille Syrjälä }
293042a0d256SVille Syrjälä
293142a0d256SVille Syrjälä skl_print_wm_changes(state);
293242a0d256SVille Syrjälä
293342a0d256SVille Syrjälä return 0;
293442a0d256SVille Syrjälä }
293542a0d256SVille Syrjälä
skl_wm_level_from_reg_val(u32 val,struct skl_wm_level * level)293642a0d256SVille Syrjälä static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
293742a0d256SVille Syrjälä {
293842a0d256SVille Syrjälä level->enable = val & PLANE_WM_EN;
293942a0d256SVille Syrjälä level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
294042a0d256SVille Syrjälä level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val);
294142a0d256SVille Syrjälä level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
294242a0d256SVille Syrjälä }
294342a0d256SVille Syrjälä
skl_pipe_wm_get_hw_state(struct intel_crtc * crtc,struct skl_pipe_wm * out)294442a0d256SVille Syrjälä static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
294542a0d256SVille Syrjälä struct skl_pipe_wm *out)
294642a0d256SVille Syrjälä {
294742a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
294842a0d256SVille Syrjälä enum pipe pipe = crtc->pipe;
294942a0d256SVille Syrjälä enum plane_id plane_id;
29507ee6f99dSVille Syrjälä int level;
295142a0d256SVille Syrjälä u32 val;
295242a0d256SVille Syrjälä
295342a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
295442a0d256SVille Syrjälä struct skl_plane_wm *wm = &out->planes[plane_id];
295542a0d256SVille Syrjälä
29567ee6f99dSVille Syrjälä for (level = 0; level < i915->display.wm.num_levels; level++) {
295742a0d256SVille Syrjälä if (plane_id != PLANE_CURSOR)
295800136429SJani Nikula val = intel_de_read(i915, PLANE_WM(pipe, plane_id, level));
295942a0d256SVille Syrjälä else
296000136429SJani Nikula val = intel_de_read(i915, CUR_WM(pipe, level));
296142a0d256SVille Syrjälä
296242a0d256SVille Syrjälä skl_wm_level_from_reg_val(val, &wm->wm[level]);
296342a0d256SVille Syrjälä }
296442a0d256SVille Syrjälä
296542a0d256SVille Syrjälä if (plane_id != PLANE_CURSOR)
296600136429SJani Nikula val = intel_de_read(i915, PLANE_WM_TRANS(pipe, plane_id));
296742a0d256SVille Syrjälä else
296800136429SJani Nikula val = intel_de_read(i915, CUR_WM_TRANS(pipe));
296942a0d256SVille Syrjälä
297042a0d256SVille Syrjälä skl_wm_level_from_reg_val(val, &wm->trans_wm);
297142a0d256SVille Syrjälä
297242a0d256SVille Syrjälä if (HAS_HW_SAGV_WM(i915)) {
297342a0d256SVille Syrjälä if (plane_id != PLANE_CURSOR)
297400136429SJani Nikula val = intel_de_read(i915, PLANE_WM_SAGV(pipe, plane_id));
297542a0d256SVille Syrjälä else
297600136429SJani Nikula val = intel_de_read(i915, CUR_WM_SAGV(pipe));
297742a0d256SVille Syrjälä
297842a0d256SVille Syrjälä skl_wm_level_from_reg_val(val, &wm->sagv.wm0);
297942a0d256SVille Syrjälä
298042a0d256SVille Syrjälä if (plane_id != PLANE_CURSOR)
298100136429SJani Nikula val = intel_de_read(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id));
298242a0d256SVille Syrjälä else
298300136429SJani Nikula val = intel_de_read(i915, CUR_WM_SAGV_TRANS(pipe));
298442a0d256SVille Syrjälä
298542a0d256SVille Syrjälä skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm);
298642a0d256SVille Syrjälä } else if (DISPLAY_VER(i915) >= 12) {
298742a0d256SVille Syrjälä wm->sagv.wm0 = wm->wm[0];
298842a0d256SVille Syrjälä wm->sagv.trans_wm = wm->trans_wm;
298942a0d256SVille Syrjälä }
299042a0d256SVille Syrjälä }
299142a0d256SVille Syrjälä }
299242a0d256SVille Syrjälä
skl_wm_get_hw_state(struct drm_i915_private * i915)29930e7a16f9SJani Nikula static void skl_wm_get_hw_state(struct drm_i915_private *i915)
299442a0d256SVille Syrjälä {
299542a0d256SVille Syrjälä struct intel_dbuf_state *dbuf_state =
299642a0d256SVille Syrjälä to_intel_dbuf_state(i915->display.dbuf.obj.state);
299742a0d256SVille Syrjälä struct intel_crtc *crtc;
299842a0d256SVille Syrjälä
299942a0d256SVille Syrjälä if (HAS_MBUS_JOINING(i915))
300042a0d256SVille Syrjälä dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
300142a0d256SVille Syrjälä
300242a0d256SVille Syrjälä for_each_intel_crtc(&i915->drm, crtc) {
300342a0d256SVille Syrjälä struct intel_crtc_state *crtc_state =
300442a0d256SVille Syrjälä to_intel_crtc_state(crtc->base.state);
300542a0d256SVille Syrjälä enum pipe pipe = crtc->pipe;
300642a0d256SVille Syrjälä unsigned int mbus_offset;
300742a0d256SVille Syrjälä enum plane_id plane_id;
300842a0d256SVille Syrjälä u8 slices;
300942a0d256SVille Syrjälä
301042a0d256SVille Syrjälä memset(&crtc_state->wm.skl.optimal, 0,
301142a0d256SVille Syrjälä sizeof(crtc_state->wm.skl.optimal));
301242a0d256SVille Syrjälä if (crtc_state->hw.active)
301342a0d256SVille Syrjälä skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
301442a0d256SVille Syrjälä crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
301542a0d256SVille Syrjälä
301642a0d256SVille Syrjälä memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
301742a0d256SVille Syrjälä
301842a0d256SVille Syrjälä for_each_plane_id_on_crtc(crtc, plane_id) {
301942a0d256SVille Syrjälä struct skl_ddb_entry *ddb =
302042a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb[plane_id];
302142a0d256SVille Syrjälä struct skl_ddb_entry *ddb_y =
302242a0d256SVille Syrjälä &crtc_state->wm.skl.plane_ddb_y[plane_id];
302342a0d256SVille Syrjälä
302442a0d256SVille Syrjälä if (!crtc_state->hw.active)
302542a0d256SVille Syrjälä continue;
302642a0d256SVille Syrjälä
302742a0d256SVille Syrjälä skl_ddb_get_hw_plane_state(i915, crtc->pipe,
302842a0d256SVille Syrjälä plane_id, ddb, ddb_y);
302942a0d256SVille Syrjälä
303042a0d256SVille Syrjälä skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb);
303142a0d256SVille Syrjälä skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
303242a0d256SVille Syrjälä }
303342a0d256SVille Syrjälä
303442a0d256SVille Syrjälä dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
303542a0d256SVille Syrjälä
303642a0d256SVille Syrjälä /*
303742a0d256SVille Syrjälä * Used for checking overlaps, so we need absolute
303842a0d256SVille Syrjälä * offsets instead of MBUS relative offsets.
303942a0d256SVille Syrjälä */
304042a0d256SVille Syrjälä slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes,
304142a0d256SVille Syrjälä dbuf_state->joined_mbus);
304242a0d256SVille Syrjälä mbus_offset = mbus_ddb_offset(i915, slices);
304342a0d256SVille Syrjälä crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
304442a0d256SVille Syrjälä crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
304542a0d256SVille Syrjälä
304642a0d256SVille Syrjälä /* The slices actually used by the planes on the pipe */
304742a0d256SVille Syrjälä dbuf_state->slices[pipe] =
304842a0d256SVille Syrjälä skl_ddb_dbuf_slice_mask(i915, &crtc_state->wm.skl.ddb);
304942a0d256SVille Syrjälä
305042a0d256SVille Syrjälä drm_dbg_kms(&i915->drm,
305142a0d256SVille Syrjälä "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
305242a0d256SVille Syrjälä crtc->base.base.id, crtc->base.name,
305342a0d256SVille Syrjälä dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,
305442a0d256SVille Syrjälä dbuf_state->ddb[pipe].end, dbuf_state->active_pipes,
305542a0d256SVille Syrjälä str_yes_no(dbuf_state->joined_mbus));
305642a0d256SVille Syrjälä }
305742a0d256SVille Syrjälä
305842a0d256SVille Syrjälä dbuf_state->enabled_slices = i915->display.dbuf.enabled_slices;
305942a0d256SVille Syrjälä }
306042a0d256SVille Syrjälä
skl_dbuf_is_misconfigured(struct drm_i915_private * i915)306142a0d256SVille Syrjälä static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915)
306242a0d256SVille Syrjälä {
306342a0d256SVille Syrjälä const struct intel_dbuf_state *dbuf_state =
306442a0d256SVille Syrjälä to_intel_dbuf_state(i915->display.dbuf.obj.state);
306542a0d256SVille Syrjälä struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
306642a0d256SVille Syrjälä struct intel_crtc *crtc;
306742a0d256SVille Syrjälä
306842a0d256SVille Syrjälä for_each_intel_crtc(&i915->drm, crtc) {
306942a0d256SVille Syrjälä const struct intel_crtc_state *crtc_state =
307042a0d256SVille Syrjälä to_intel_crtc_state(crtc->base.state);
307142a0d256SVille Syrjälä
307242a0d256SVille Syrjälä entries[crtc->pipe] = crtc_state->wm.skl.ddb;
307342a0d256SVille Syrjälä }
307442a0d256SVille Syrjälä
307542a0d256SVille Syrjälä for_each_intel_crtc(&i915->drm, crtc) {
307642a0d256SVille Syrjälä const struct intel_crtc_state *crtc_state =
307742a0d256SVille Syrjälä to_intel_crtc_state(crtc->base.state);
307842a0d256SVille Syrjälä u8 slices;
307942a0d256SVille Syrjälä
308042a0d256SVille Syrjälä slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes,
308142a0d256SVille Syrjälä dbuf_state->joined_mbus);
308242a0d256SVille Syrjälä if (dbuf_state->slices[crtc->pipe] & ~slices)
308342a0d256SVille Syrjälä return true;
308442a0d256SVille Syrjälä
308542a0d256SVille Syrjälä if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries,
308642a0d256SVille Syrjälä I915_MAX_PIPES, crtc->pipe))
308742a0d256SVille Syrjälä return true;
308842a0d256SVille Syrjälä }
308942a0d256SVille Syrjälä
309042a0d256SVille Syrjälä return false;
309142a0d256SVille Syrjälä }
309242a0d256SVille Syrjälä
skl_wm_sanitize(struct drm_i915_private * i915)30930e7a16f9SJani Nikula static void skl_wm_sanitize(struct drm_i915_private *i915)
309442a0d256SVille Syrjälä {
309542a0d256SVille Syrjälä struct intel_crtc *crtc;
309642a0d256SVille Syrjälä
309742a0d256SVille Syrjälä /*
309842a0d256SVille Syrjälä * On TGL/RKL (at least) the BIOS likes to assign the planes
309942a0d256SVille Syrjälä * to the wrong DBUF slices. This will cause an infinite loop
310042a0d256SVille Syrjälä * in skl_commit_modeset_enables() as it can't find a way to
310142a0d256SVille Syrjälä * transition between the old bogus DBUF layout to the new
310242a0d256SVille Syrjälä * proper DBUF layout without DBUF allocation overlaps between
310342a0d256SVille Syrjälä * the planes (which cannot be allowed or else the hardware
310442a0d256SVille Syrjälä * may hang). If we detect a bogus DBUF layout just turn off
310542a0d256SVille Syrjälä * all the planes so that skl_commit_modeset_enables() can
310642a0d256SVille Syrjälä * simply ignore them.
310742a0d256SVille Syrjälä */
310842a0d256SVille Syrjälä if (!skl_dbuf_is_misconfigured(i915))
310942a0d256SVille Syrjälä return;
311042a0d256SVille Syrjälä
311142a0d256SVille Syrjälä drm_dbg_kms(&i915->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n");
311242a0d256SVille Syrjälä
311342a0d256SVille Syrjälä for_each_intel_crtc(&i915->drm, crtc) {
311442a0d256SVille Syrjälä struct intel_plane *plane = to_intel_plane(crtc->base.primary);
311542a0d256SVille Syrjälä const struct intel_plane_state *plane_state =
311642a0d256SVille Syrjälä to_intel_plane_state(plane->base.state);
311742a0d256SVille Syrjälä struct intel_crtc_state *crtc_state =
311842a0d256SVille Syrjälä to_intel_crtc_state(crtc->base.state);
311942a0d256SVille Syrjälä
312042a0d256SVille Syrjälä if (plane_state->uapi.visible)
312142a0d256SVille Syrjälä intel_plane_disable_noatomic(crtc, plane);
312242a0d256SVille Syrjälä
312342a0d256SVille Syrjälä drm_WARN_ON(&i915->drm, crtc_state->active_planes != 0);
312442a0d256SVille Syrjälä
312542a0d256SVille Syrjälä memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));
312642a0d256SVille Syrjälä }
312742a0d256SVille Syrjälä }
312842a0d256SVille Syrjälä
skl_wm_get_hw_state_and_sanitize(struct drm_i915_private * i915)31290e7a16f9SJani Nikula static void skl_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915)
31300e7a16f9SJani Nikula {
31310e7a16f9SJani Nikula skl_wm_get_hw_state(i915);
31320e7a16f9SJani Nikula skl_wm_sanitize(i915);
31330e7a16f9SJani Nikula }
31340e7a16f9SJani Nikula
intel_wm_state_verify(struct intel_crtc * crtc,struct intel_crtc_state * new_crtc_state)313542a0d256SVille Syrjälä void intel_wm_state_verify(struct intel_crtc *crtc,
313642a0d256SVille Syrjälä struct intel_crtc_state *new_crtc_state)
313742a0d256SVille Syrjälä {
313842a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(crtc->base.dev);
313942a0d256SVille Syrjälä struct skl_hw_state {
314042a0d256SVille Syrjälä struct skl_ddb_entry ddb[I915_MAX_PLANES];
314142a0d256SVille Syrjälä struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
314242a0d256SVille Syrjälä struct skl_pipe_wm wm;
314342a0d256SVille Syrjälä } *hw;
314442a0d256SVille Syrjälä const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
314542a0d256SVille Syrjälä struct intel_plane *plane;
314642a0d256SVille Syrjälä u8 hw_enabled_slices;
31477ee6f99dSVille Syrjälä int level;
314842a0d256SVille Syrjälä
314942a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 9 || !new_crtc_state->hw.active)
315042a0d256SVille Syrjälä return;
315142a0d256SVille Syrjälä
315242a0d256SVille Syrjälä hw = kzalloc(sizeof(*hw), GFP_KERNEL);
315342a0d256SVille Syrjälä if (!hw)
315442a0d256SVille Syrjälä return;
315542a0d256SVille Syrjälä
315642a0d256SVille Syrjälä skl_pipe_wm_get_hw_state(crtc, &hw->wm);
315742a0d256SVille Syrjälä
315842a0d256SVille Syrjälä skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
315942a0d256SVille Syrjälä
316042a0d256SVille Syrjälä hw_enabled_slices = intel_enabled_dbuf_slices_mask(i915);
316142a0d256SVille Syrjälä
316242a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 11 &&
316342a0d256SVille Syrjälä hw_enabled_slices != i915->display.dbuf.enabled_slices)
316442a0d256SVille Syrjälä drm_err(&i915->drm,
316542a0d256SVille Syrjälä "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
316642a0d256SVille Syrjälä i915->display.dbuf.enabled_slices,
316742a0d256SVille Syrjälä hw_enabled_slices);
316842a0d256SVille Syrjälä
316942a0d256SVille Syrjälä for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
317042a0d256SVille Syrjälä const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
317142a0d256SVille Syrjälä const struct skl_wm_level *hw_wm_level, *sw_wm_level;
317242a0d256SVille Syrjälä
317342a0d256SVille Syrjälä /* Watermarks */
31747ee6f99dSVille Syrjälä for (level = 0; level < i915->display.wm.num_levels; level++) {
317542a0d256SVille Syrjälä hw_wm_level = &hw->wm.planes[plane->id].wm[level];
317642a0d256SVille Syrjälä sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
317742a0d256SVille Syrjälä
317842a0d256SVille Syrjälä if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
317942a0d256SVille Syrjälä continue;
318042a0d256SVille Syrjälä
318142a0d256SVille Syrjälä drm_err(&i915->drm,
318242a0d256SVille Syrjälä "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
318342a0d256SVille Syrjälä plane->base.base.id, plane->base.name, level,
318442a0d256SVille Syrjälä sw_wm_level->enable,
318542a0d256SVille Syrjälä sw_wm_level->blocks,
318642a0d256SVille Syrjälä sw_wm_level->lines,
318742a0d256SVille Syrjälä hw_wm_level->enable,
318842a0d256SVille Syrjälä hw_wm_level->blocks,
318942a0d256SVille Syrjälä hw_wm_level->lines);
319042a0d256SVille Syrjälä }
319142a0d256SVille Syrjälä
319242a0d256SVille Syrjälä hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
319342a0d256SVille Syrjälä sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
319442a0d256SVille Syrjälä
319542a0d256SVille Syrjälä if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
319642a0d256SVille Syrjälä drm_err(&i915->drm,
319742a0d256SVille Syrjälä "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
319842a0d256SVille Syrjälä plane->base.base.id, plane->base.name,
319942a0d256SVille Syrjälä sw_wm_level->enable,
320042a0d256SVille Syrjälä sw_wm_level->blocks,
320142a0d256SVille Syrjälä sw_wm_level->lines,
320242a0d256SVille Syrjälä hw_wm_level->enable,
320342a0d256SVille Syrjälä hw_wm_level->blocks,
320442a0d256SVille Syrjälä hw_wm_level->lines);
320542a0d256SVille Syrjälä }
320642a0d256SVille Syrjälä
320742a0d256SVille Syrjälä hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
320842a0d256SVille Syrjälä sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
320942a0d256SVille Syrjälä
321042a0d256SVille Syrjälä if (HAS_HW_SAGV_WM(i915) &&
321142a0d256SVille Syrjälä !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
321242a0d256SVille Syrjälä drm_err(&i915->drm,
321342a0d256SVille Syrjälä "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
321442a0d256SVille Syrjälä plane->base.base.id, plane->base.name,
321542a0d256SVille Syrjälä sw_wm_level->enable,
321642a0d256SVille Syrjälä sw_wm_level->blocks,
321742a0d256SVille Syrjälä sw_wm_level->lines,
321842a0d256SVille Syrjälä hw_wm_level->enable,
321942a0d256SVille Syrjälä hw_wm_level->blocks,
322042a0d256SVille Syrjälä hw_wm_level->lines);
322142a0d256SVille Syrjälä }
322242a0d256SVille Syrjälä
322342a0d256SVille Syrjälä hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
322442a0d256SVille Syrjälä sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
322542a0d256SVille Syrjälä
322642a0d256SVille Syrjälä if (HAS_HW_SAGV_WM(i915) &&
322742a0d256SVille Syrjälä !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
322842a0d256SVille Syrjälä drm_err(&i915->drm,
322942a0d256SVille Syrjälä "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
323042a0d256SVille Syrjälä plane->base.base.id, plane->base.name,
323142a0d256SVille Syrjälä sw_wm_level->enable,
323242a0d256SVille Syrjälä sw_wm_level->blocks,
323342a0d256SVille Syrjälä sw_wm_level->lines,
323442a0d256SVille Syrjälä hw_wm_level->enable,
323542a0d256SVille Syrjälä hw_wm_level->blocks,
323642a0d256SVille Syrjälä hw_wm_level->lines);
323742a0d256SVille Syrjälä }
323842a0d256SVille Syrjälä
323942a0d256SVille Syrjälä /* DDB */
324042a0d256SVille Syrjälä hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
324142a0d256SVille Syrjälä sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
324242a0d256SVille Syrjälä
324342a0d256SVille Syrjälä if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
324442a0d256SVille Syrjälä drm_err(&i915->drm,
324542a0d256SVille Syrjälä "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
324642a0d256SVille Syrjälä plane->base.base.id, plane->base.name,
324742a0d256SVille Syrjälä sw_ddb_entry->start, sw_ddb_entry->end,
324842a0d256SVille Syrjälä hw_ddb_entry->start, hw_ddb_entry->end);
324942a0d256SVille Syrjälä }
325042a0d256SVille Syrjälä }
325142a0d256SVille Syrjälä
325242a0d256SVille Syrjälä kfree(hw);
325342a0d256SVille Syrjälä }
325442a0d256SVille Syrjälä
skl_watermark_ipc_enabled(struct drm_i915_private * i915)325523fbdb07SJani Nikula bool skl_watermark_ipc_enabled(struct drm_i915_private *i915)
325623fbdb07SJani Nikula {
325770296670SJani Nikula return i915->display.wm.ipc_enabled;
325823fbdb07SJani Nikula }
325923fbdb07SJani Nikula
skl_watermark_ipc_update(struct drm_i915_private * i915)326023fbdb07SJani Nikula void skl_watermark_ipc_update(struct drm_i915_private *i915)
326142a0d256SVille Syrjälä {
326242a0d256SVille Syrjälä if (!HAS_IPC(i915))
326342a0d256SVille Syrjälä return;
326442a0d256SVille Syrjälä
326500136429SJani Nikula intel_de_rmw(i915, DISP_ARB_CTL2, DISP_IPC_ENABLE,
3266c73cdd12SJani Nikula skl_watermark_ipc_enabled(i915) ? DISP_IPC_ENABLE : 0);
326742a0d256SVille Syrjälä }
326842a0d256SVille Syrjälä
skl_watermark_ipc_can_enable(struct drm_i915_private * i915)326923fbdb07SJani Nikula static bool skl_watermark_ipc_can_enable(struct drm_i915_private *i915)
327042a0d256SVille Syrjälä {
327142a0d256SVille Syrjälä /* Display WA #0477 WaDisableIPC: skl */
327242a0d256SVille Syrjälä if (IS_SKYLAKE(i915))
327342a0d256SVille Syrjälä return false;
327442a0d256SVille Syrjälä
327542a0d256SVille Syrjälä /* Display WA #1141: SKL:all KBL:all CFL */
327642a0d256SVille Syrjälä if (IS_KABYLAKE(i915) ||
327742a0d256SVille Syrjälä IS_COFFEELAKE(i915) ||
327842a0d256SVille Syrjälä IS_COMETLAKE(i915))
327942a0d256SVille Syrjälä return i915->dram_info.symmetric_memory;
328042a0d256SVille Syrjälä
328142a0d256SVille Syrjälä return true;
328242a0d256SVille Syrjälä }
328342a0d256SVille Syrjälä
skl_watermark_ipc_init(struct drm_i915_private * i915)328423fbdb07SJani Nikula void skl_watermark_ipc_init(struct drm_i915_private *i915)
328542a0d256SVille Syrjälä {
328642a0d256SVille Syrjälä if (!HAS_IPC(i915))
328742a0d256SVille Syrjälä return;
328842a0d256SVille Syrjälä
328970296670SJani Nikula i915->display.wm.ipc_enabled = skl_watermark_ipc_can_enable(i915);
329042a0d256SVille Syrjälä
329123fbdb07SJani Nikula skl_watermark_ipc_update(i915);
329242a0d256SVille Syrjälä }
329342a0d256SVille Syrjälä
329442a0d256SVille Syrjälä static void
adjust_wm_latency(struct drm_i915_private * i915,u16 wm[],int num_levels,int read_latency)329542a0d256SVille Syrjälä adjust_wm_latency(struct drm_i915_private *i915,
32967ee6f99dSVille Syrjälä u16 wm[], int num_levels, int read_latency)
329742a0d256SVille Syrjälä {
329842a0d256SVille Syrjälä bool wm_lv_0_adjust_needed = i915->dram_info.wm_lv_0_adjust_needed;
329942a0d256SVille Syrjälä int i, level;
330042a0d256SVille Syrjälä
330142a0d256SVille Syrjälä /*
330242a0d256SVille Syrjälä * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
330342a0d256SVille Syrjälä * need to be disabled. We make sure to sanitize the values out
330442a0d256SVille Syrjälä * of the punit to satisfy this requirement.
330542a0d256SVille Syrjälä */
33067ee6f99dSVille Syrjälä for (level = 1; level < num_levels; level++) {
330742a0d256SVille Syrjälä if (wm[level] == 0) {
33087ee6f99dSVille Syrjälä for (i = level + 1; i < num_levels; i++)
330942a0d256SVille Syrjälä wm[i] = 0;
331042a0d256SVille Syrjälä
33117ee6f99dSVille Syrjälä num_levels = level;
331242a0d256SVille Syrjälä break;
331342a0d256SVille Syrjälä }
331442a0d256SVille Syrjälä }
331542a0d256SVille Syrjälä
331642a0d256SVille Syrjälä /*
331742a0d256SVille Syrjälä * WaWmMemoryReadLatency
331842a0d256SVille Syrjälä *
331942a0d256SVille Syrjälä * punit doesn't take into account the read latency so we need
332042a0d256SVille Syrjälä * to add proper adjustement to each valid level we retrieve
332142a0d256SVille Syrjälä * from the punit when level 0 response data is 0us.
332242a0d256SVille Syrjälä */
332342a0d256SVille Syrjälä if (wm[0] == 0) {
33247ee6f99dSVille Syrjälä for (level = 0; level < num_levels; level++)
332542a0d256SVille Syrjälä wm[level] += read_latency;
332642a0d256SVille Syrjälä }
332742a0d256SVille Syrjälä
332842a0d256SVille Syrjälä /*
332942a0d256SVille Syrjälä * WA Level-0 adjustment for 16GB DIMMs: SKL+
333042a0d256SVille Syrjälä * If we could not get dimm info enable this WA to prevent from
333142a0d256SVille Syrjälä * any underrun. If not able to get Dimm info assume 16GB dimm
333242a0d256SVille Syrjälä * to avoid any underrun.
333342a0d256SVille Syrjälä */
333442a0d256SVille Syrjälä if (wm_lv_0_adjust_needed)
333542a0d256SVille Syrjälä wm[0] += 1;
333642a0d256SVille Syrjälä }
333742a0d256SVille Syrjälä
mtl_read_wm_latency(struct drm_i915_private * i915,u16 wm[])333842a0d256SVille Syrjälä static void mtl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
333942a0d256SVille Syrjälä {
33407ee6f99dSVille Syrjälä int num_levels = i915->display.wm.num_levels;
334142a0d256SVille Syrjälä u32 val;
334242a0d256SVille Syrjälä
334300136429SJani Nikula val = intel_de_read(i915, MTL_LATENCY_LP0_LP1);
334442a0d256SVille Syrjälä wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
334542a0d256SVille Syrjälä wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
334642a0d256SVille Syrjälä
334700136429SJani Nikula val = intel_de_read(i915, MTL_LATENCY_LP2_LP3);
334842a0d256SVille Syrjälä wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
334942a0d256SVille Syrjälä wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
335042a0d256SVille Syrjälä
335100136429SJani Nikula val = intel_de_read(i915, MTL_LATENCY_LP4_LP5);
335242a0d256SVille Syrjälä wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
335342a0d256SVille Syrjälä wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
335442a0d256SVille Syrjälä
33557ee6f99dSVille Syrjälä adjust_wm_latency(i915, wm, num_levels, 6);
335642a0d256SVille Syrjälä }
335742a0d256SVille Syrjälä
skl_read_wm_latency(struct drm_i915_private * i915,u16 wm[])335842a0d256SVille Syrjälä static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
335942a0d256SVille Syrjälä {
33607ee6f99dSVille Syrjälä int num_levels = i915->display.wm.num_levels;
336142a0d256SVille Syrjälä int read_latency = DISPLAY_VER(i915) >= 12 ? 3 : 2;
336242a0d256SVille Syrjälä int mult = IS_DG2(i915) ? 2 : 1;
336342a0d256SVille Syrjälä u32 val;
336442a0d256SVille Syrjälä int ret;
336542a0d256SVille Syrjälä
336642a0d256SVille Syrjälä /* read the first set of memory latencies[0:3] */
336742a0d256SVille Syrjälä val = 0; /* data0 to be programmed to 0 for first set */
336842a0d256SVille Syrjälä ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
336942a0d256SVille Syrjälä if (ret) {
337042a0d256SVille Syrjälä drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret);
337142a0d256SVille Syrjälä return;
337242a0d256SVille Syrjälä }
337342a0d256SVille Syrjälä
33743fecf93cSVille Syrjälä wm[0] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;
33753fecf93cSVille Syrjälä wm[1] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;
33763fecf93cSVille Syrjälä wm[2] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;
33773fecf93cSVille Syrjälä wm[3] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;
337842a0d256SVille Syrjälä
337942a0d256SVille Syrjälä /* read the second set of memory latencies[4:7] */
338042a0d256SVille Syrjälä val = 1; /* data0 to be programmed to 1 for second set */
338142a0d256SVille Syrjälä ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
338242a0d256SVille Syrjälä if (ret) {
338342a0d256SVille Syrjälä drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret);
338442a0d256SVille Syrjälä return;
338542a0d256SVille Syrjälä }
338642a0d256SVille Syrjälä
33873fecf93cSVille Syrjälä wm[4] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_0_4_MASK, val) * mult;
33883fecf93cSVille Syrjälä wm[5] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_1_5_MASK, val) * mult;
33893fecf93cSVille Syrjälä wm[6] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_2_6_MASK, val) * mult;
33903fecf93cSVille Syrjälä wm[7] = REG_FIELD_GET(GEN9_MEM_LATENCY_LEVEL_3_7_MASK, val) * mult;
339142a0d256SVille Syrjälä
33927ee6f99dSVille Syrjälä adjust_wm_latency(i915, wm, num_levels, read_latency);
339342a0d256SVille Syrjälä }
339442a0d256SVille Syrjälä
skl_setup_wm_latency(struct drm_i915_private * i915)339542a0d256SVille Syrjälä static void skl_setup_wm_latency(struct drm_i915_private *i915)
339642a0d256SVille Syrjälä {
3397064b3eeeSVille Syrjälä if (HAS_HW_SAGV_WM(i915))
33987ee6f99dSVille Syrjälä i915->display.wm.num_levels = 6;
3399064b3eeeSVille Syrjälä else
34007ee6f99dSVille Syrjälä i915->display.wm.num_levels = 8;
3401064b3eeeSVille Syrjälä
340242a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 14)
340342a0d256SVille Syrjälä mtl_read_wm_latency(i915, i915->display.wm.skl_latency);
340442a0d256SVille Syrjälä else
340542a0d256SVille Syrjälä skl_read_wm_latency(i915, i915->display.wm.skl_latency);
340642a0d256SVille Syrjälä
340742a0d256SVille Syrjälä intel_print_wm_latency(i915, "Gen9 Plane", i915->display.wm.skl_latency);
340842a0d256SVille Syrjälä }
340942a0d256SVille Syrjälä
341042a0d256SVille Syrjälä static const struct intel_wm_funcs skl_wm_funcs = {
341142a0d256SVille Syrjälä .compute_global_watermarks = skl_compute_wm,
34120e7a16f9SJani Nikula .get_hw_state = skl_wm_get_hw_state_and_sanitize,
341342a0d256SVille Syrjälä };
341442a0d256SVille Syrjälä
skl_wm_init(struct drm_i915_private * i915)341542a0d256SVille Syrjälä void skl_wm_init(struct drm_i915_private *i915)
341642a0d256SVille Syrjälä {
341742a0d256SVille Syrjälä intel_sagv_init(i915);
341842a0d256SVille Syrjälä
341942a0d256SVille Syrjälä skl_setup_wm_latency(i915);
342042a0d256SVille Syrjälä
342142a0d256SVille Syrjälä i915->display.funcs.wm = &skl_wm_funcs;
342242a0d256SVille Syrjälä }
342342a0d256SVille Syrjälä
intel_dbuf_duplicate_state(struct intel_global_obj * obj)342442a0d256SVille Syrjälä static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
342542a0d256SVille Syrjälä {
342642a0d256SVille Syrjälä struct intel_dbuf_state *dbuf_state;
342742a0d256SVille Syrjälä
342842a0d256SVille Syrjälä dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL);
342942a0d256SVille Syrjälä if (!dbuf_state)
343042a0d256SVille Syrjälä return NULL;
343142a0d256SVille Syrjälä
343242a0d256SVille Syrjälä return &dbuf_state->base;
343342a0d256SVille Syrjälä }
343442a0d256SVille Syrjälä
intel_dbuf_destroy_state(struct intel_global_obj * obj,struct intel_global_state * state)343542a0d256SVille Syrjälä static void intel_dbuf_destroy_state(struct intel_global_obj *obj,
343642a0d256SVille Syrjälä struct intel_global_state *state)
343742a0d256SVille Syrjälä {
343842a0d256SVille Syrjälä kfree(state);
343942a0d256SVille Syrjälä }
344042a0d256SVille Syrjälä
344142a0d256SVille Syrjälä static const struct intel_global_state_funcs intel_dbuf_funcs = {
344242a0d256SVille Syrjälä .atomic_duplicate_state = intel_dbuf_duplicate_state,
344342a0d256SVille Syrjälä .atomic_destroy_state = intel_dbuf_destroy_state,
344442a0d256SVille Syrjälä };
344542a0d256SVille Syrjälä
344642a0d256SVille Syrjälä struct intel_dbuf_state *
intel_atomic_get_dbuf_state(struct intel_atomic_state * state)344742a0d256SVille Syrjälä intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
344842a0d256SVille Syrjälä {
344942a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
345042a0d256SVille Syrjälä struct intel_global_state *dbuf_state;
345142a0d256SVille Syrjälä
345242a0d256SVille Syrjälä dbuf_state = intel_atomic_get_global_obj_state(state, &i915->display.dbuf.obj);
345342a0d256SVille Syrjälä if (IS_ERR(dbuf_state))
345442a0d256SVille Syrjälä return ERR_CAST(dbuf_state);
345542a0d256SVille Syrjälä
345642a0d256SVille Syrjälä return to_intel_dbuf_state(dbuf_state);
345742a0d256SVille Syrjälä }
345842a0d256SVille Syrjälä
intel_dbuf_init(struct drm_i915_private * i915)345942a0d256SVille Syrjälä int intel_dbuf_init(struct drm_i915_private *i915)
346042a0d256SVille Syrjälä {
346142a0d256SVille Syrjälä struct intel_dbuf_state *dbuf_state;
346242a0d256SVille Syrjälä
346342a0d256SVille Syrjälä dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL);
346442a0d256SVille Syrjälä if (!dbuf_state)
346542a0d256SVille Syrjälä return -ENOMEM;
346642a0d256SVille Syrjälä
346742a0d256SVille Syrjälä intel_atomic_global_obj_init(i915, &i915->display.dbuf.obj,
346842a0d256SVille Syrjälä &dbuf_state->base, &intel_dbuf_funcs);
346942a0d256SVille Syrjälä
347042a0d256SVille Syrjälä return 0;
347142a0d256SVille Syrjälä }
347242a0d256SVille Syrjälä
347342a0d256SVille Syrjälä /*
347442a0d256SVille Syrjälä * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
347542a0d256SVille Syrjälä * update the request state of all DBUS slices.
347642a0d256SVille Syrjälä */
update_mbus_pre_enable(struct intel_atomic_state * state)347742a0d256SVille Syrjälä static void update_mbus_pre_enable(struct intel_atomic_state *state)
347842a0d256SVille Syrjälä {
347942a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
348042a0d256SVille Syrjälä u32 mbus_ctl, dbuf_min_tracker_val;
348142a0d256SVille Syrjälä enum dbuf_slice slice;
348242a0d256SVille Syrjälä const struct intel_dbuf_state *dbuf_state =
348342a0d256SVille Syrjälä intel_atomic_get_new_dbuf_state(state);
348442a0d256SVille Syrjälä
348542a0d256SVille Syrjälä if (!HAS_MBUS_JOINING(i915))
348642a0d256SVille Syrjälä return;
348742a0d256SVille Syrjälä
348842a0d256SVille Syrjälä /*
348942a0d256SVille Syrjälä * TODO: Implement vblank synchronized MBUS joining changes.
349042a0d256SVille Syrjälä * Must be properly coordinated with dbuf reprogramming.
349142a0d256SVille Syrjälä */
349242a0d256SVille Syrjälä if (dbuf_state->joined_mbus) {
349342a0d256SVille Syrjälä mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
349442a0d256SVille Syrjälä MBUS_JOIN_PIPE_SELECT_NONE;
349542a0d256SVille Syrjälä dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
349642a0d256SVille Syrjälä } else {
349742a0d256SVille Syrjälä mbus_ctl = MBUS_HASHING_MODE_2x2 |
349842a0d256SVille Syrjälä MBUS_JOIN_PIPE_SELECT_NONE;
349942a0d256SVille Syrjälä dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
350042a0d256SVille Syrjälä }
350142a0d256SVille Syrjälä
350242a0d256SVille Syrjälä intel_de_rmw(i915, MBUS_CTL,
350342a0d256SVille Syrjälä MBUS_HASHING_MODE_MASK | MBUS_JOIN |
350442a0d256SVille Syrjälä MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
350542a0d256SVille Syrjälä
350642a0d256SVille Syrjälä for_each_dbuf_slice(i915, slice)
350742a0d256SVille Syrjälä intel_de_rmw(i915, DBUF_CTL_S(slice),
350842a0d256SVille Syrjälä DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
350942a0d256SVille Syrjälä dbuf_min_tracker_val);
351042a0d256SVille Syrjälä }
351142a0d256SVille Syrjälä
intel_dbuf_pre_plane_update(struct intel_atomic_state * state)351242a0d256SVille Syrjälä void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
351342a0d256SVille Syrjälä {
351442a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
351542a0d256SVille Syrjälä const struct intel_dbuf_state *new_dbuf_state =
351642a0d256SVille Syrjälä intel_atomic_get_new_dbuf_state(state);
351742a0d256SVille Syrjälä const struct intel_dbuf_state *old_dbuf_state =
351842a0d256SVille Syrjälä intel_atomic_get_old_dbuf_state(state);
351942a0d256SVille Syrjälä
352042a0d256SVille Syrjälä if (!new_dbuf_state ||
352142a0d256SVille Syrjälä (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
352242a0d256SVille Syrjälä new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
352342a0d256SVille Syrjälä return;
352442a0d256SVille Syrjälä
352542a0d256SVille Syrjälä WARN_ON(!new_dbuf_state->base.changed);
352642a0d256SVille Syrjälä
352742a0d256SVille Syrjälä update_mbus_pre_enable(state);
352842a0d256SVille Syrjälä gen9_dbuf_slices_update(i915,
352942a0d256SVille Syrjälä old_dbuf_state->enabled_slices |
353042a0d256SVille Syrjälä new_dbuf_state->enabled_slices);
353142a0d256SVille Syrjälä }
353242a0d256SVille Syrjälä
intel_dbuf_post_plane_update(struct intel_atomic_state * state)353342a0d256SVille Syrjälä void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
353442a0d256SVille Syrjälä {
353542a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
353642a0d256SVille Syrjälä const struct intel_dbuf_state *new_dbuf_state =
353742a0d256SVille Syrjälä intel_atomic_get_new_dbuf_state(state);
353842a0d256SVille Syrjälä const struct intel_dbuf_state *old_dbuf_state =
353942a0d256SVille Syrjälä intel_atomic_get_old_dbuf_state(state);
354042a0d256SVille Syrjälä
354142a0d256SVille Syrjälä if (!new_dbuf_state ||
354242a0d256SVille Syrjälä (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
354342a0d256SVille Syrjälä new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
354442a0d256SVille Syrjälä return;
354542a0d256SVille Syrjälä
354642a0d256SVille Syrjälä WARN_ON(!new_dbuf_state->base.changed);
354742a0d256SVille Syrjälä
354842a0d256SVille Syrjälä gen9_dbuf_slices_update(i915,
354942a0d256SVille Syrjälä new_dbuf_state->enabled_slices);
355042a0d256SVille Syrjälä }
355142a0d256SVille Syrjälä
xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe,u8 active_pipes)3552851d635aSRadhakrishna Sripada static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
3553851d635aSRadhakrishna Sripada {
3554851d635aSRadhakrishna Sripada switch (pipe) {
3555851d635aSRadhakrishna Sripada case PIPE_A:
3556851d635aSRadhakrishna Sripada return !(active_pipes & BIT(PIPE_D));
3557851d635aSRadhakrishna Sripada case PIPE_D:
3558851d635aSRadhakrishna Sripada return !(active_pipes & BIT(PIPE_A));
3559851d635aSRadhakrishna Sripada case PIPE_B:
3560851d635aSRadhakrishna Sripada return !(active_pipes & BIT(PIPE_C));
3561851d635aSRadhakrishna Sripada case PIPE_C:
3562851d635aSRadhakrishna Sripada return !(active_pipes & BIT(PIPE_B));
3563851d635aSRadhakrishna Sripada default: /* to suppress compiler warning */
3564851d635aSRadhakrishna Sripada MISSING_CASE(pipe);
3565851d635aSRadhakrishna Sripada break;
3566851d635aSRadhakrishna Sripada }
3567851d635aSRadhakrishna Sripada
3568851d635aSRadhakrishna Sripada return false;
3569851d635aSRadhakrishna Sripada }
3570851d635aSRadhakrishna Sripada
intel_mbus_dbox_update(struct intel_atomic_state * state)357142a0d256SVille Syrjälä void intel_mbus_dbox_update(struct intel_atomic_state *state)
357242a0d256SVille Syrjälä {
357342a0d256SVille Syrjälä struct drm_i915_private *i915 = to_i915(state->base.dev);
357442a0d256SVille Syrjälä const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
357542a0d256SVille Syrjälä const struct intel_crtc_state *new_crtc_state;
357642a0d256SVille Syrjälä const struct intel_crtc *crtc;
357742a0d256SVille Syrjälä u32 val = 0;
357842a0d256SVille Syrjälä int i;
357942a0d256SVille Syrjälä
358042a0d256SVille Syrjälä if (DISPLAY_VER(i915) < 11)
358142a0d256SVille Syrjälä return;
358242a0d256SVille Syrjälä
358342a0d256SVille Syrjälä new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
358442a0d256SVille Syrjälä old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
358542a0d256SVille Syrjälä if (!new_dbuf_state ||
358642a0d256SVille Syrjälä (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
358742a0d256SVille Syrjälä new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
358842a0d256SVille Syrjälä return;
358942a0d256SVille Syrjälä
3590851d635aSRadhakrishna Sripada if (DISPLAY_VER(i915) >= 14)
3591851d635aSRadhakrishna Sripada val |= MBUS_DBOX_I_CREDIT(2);
3592851d635aSRadhakrishna Sripada
359342a0d256SVille Syrjälä if (DISPLAY_VER(i915) >= 12) {
359442a0d256SVille Syrjälä val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
359542a0d256SVille Syrjälä val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
359642a0d256SVille Syrjälä val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
359742a0d256SVille Syrjälä }
359842a0d256SVille Syrjälä
3599851d635aSRadhakrishna Sripada if (DISPLAY_VER(i915) >= 14)
3600851d635aSRadhakrishna Sripada val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
3601851d635aSRadhakrishna Sripada MBUS_DBOX_A_CREDIT(8);
3602851d635aSRadhakrishna Sripada else if (IS_ALDERLAKE_P(i915))
360342a0d256SVille Syrjälä /* Wa_22010947358:adl-p */
360442a0d256SVille Syrjälä val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
360542a0d256SVille Syrjälä MBUS_DBOX_A_CREDIT(4);
360642a0d256SVille Syrjälä else
360742a0d256SVille Syrjälä val |= MBUS_DBOX_A_CREDIT(2);
360842a0d256SVille Syrjälä
3609851d635aSRadhakrishna Sripada if (DISPLAY_VER(i915) >= 14) {
3610851d635aSRadhakrishna Sripada val |= MBUS_DBOX_B_CREDIT(0xA);
3611851d635aSRadhakrishna Sripada } else if (IS_ALDERLAKE_P(i915)) {
361242a0d256SVille Syrjälä val |= MBUS_DBOX_BW_CREDIT(2);
361342a0d256SVille Syrjälä val |= MBUS_DBOX_B_CREDIT(8);
361442a0d256SVille Syrjälä } else if (DISPLAY_VER(i915) >= 12) {
361542a0d256SVille Syrjälä val |= MBUS_DBOX_BW_CREDIT(2);
361642a0d256SVille Syrjälä val |= MBUS_DBOX_B_CREDIT(12);
361742a0d256SVille Syrjälä } else {
361842a0d256SVille Syrjälä val |= MBUS_DBOX_BW_CREDIT(1);
361942a0d256SVille Syrjälä val |= MBUS_DBOX_B_CREDIT(8);
362042a0d256SVille Syrjälä }
362142a0d256SVille Syrjälä
362242a0d256SVille Syrjälä for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
3623851d635aSRadhakrishna Sripada u32 pipe_val = val;
3624851d635aSRadhakrishna Sripada
3625851d635aSRadhakrishna Sripada if (!new_crtc_state->hw.active)
362642a0d256SVille Syrjälä continue;
362742a0d256SVille Syrjälä
3628851d635aSRadhakrishna Sripada if (DISPLAY_VER(i915) >= 14) {
3629851d635aSRadhakrishna Sripada if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
3630851d635aSRadhakrishna Sripada new_dbuf_state->active_pipes))
3631851d635aSRadhakrishna Sripada pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
3632851d635aSRadhakrishna Sripada else
3633851d635aSRadhakrishna Sripada pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
3634851d635aSRadhakrishna Sripada }
3635851d635aSRadhakrishna Sripada
3636851d635aSRadhakrishna Sripada intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
363742a0d256SVille Syrjälä }
363842a0d256SVille Syrjälä }
3639dde01ed5SJani Nikula
skl_watermark_ipc_status_show(struct seq_file * m,void * data)3640dde01ed5SJani Nikula static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
3641dde01ed5SJani Nikula {
3642dde01ed5SJani Nikula struct drm_i915_private *i915 = m->private;
3643dde01ed5SJani Nikula
3644dde01ed5SJani Nikula seq_printf(m, "Isochronous Priority Control: %s\n",
3645dde01ed5SJani Nikula str_yes_no(skl_watermark_ipc_enabled(i915)));
3646dde01ed5SJani Nikula return 0;
3647dde01ed5SJani Nikula }
3648dde01ed5SJani Nikula
skl_watermark_ipc_status_open(struct inode * inode,struct file * file)3649dde01ed5SJani Nikula static int skl_watermark_ipc_status_open(struct inode *inode, struct file *file)
3650dde01ed5SJani Nikula {
3651dde01ed5SJani Nikula struct drm_i915_private *i915 = inode->i_private;
3652dde01ed5SJani Nikula
3653dde01ed5SJani Nikula return single_open(file, skl_watermark_ipc_status_show, i915);
3654dde01ed5SJani Nikula }
3655dde01ed5SJani Nikula
skl_watermark_ipc_status_write(struct file * file,const char __user * ubuf,size_t len,loff_t * offp)3656dde01ed5SJani Nikula static ssize_t skl_watermark_ipc_status_write(struct file *file,
3657dde01ed5SJani Nikula const char __user *ubuf,
3658dde01ed5SJani Nikula size_t len, loff_t *offp)
3659dde01ed5SJani Nikula {
3660dde01ed5SJani Nikula struct seq_file *m = file->private_data;
3661dde01ed5SJani Nikula struct drm_i915_private *i915 = m->private;
3662dde01ed5SJani Nikula intel_wakeref_t wakeref;
3663dde01ed5SJani Nikula bool enable;
3664dde01ed5SJani Nikula int ret;
3665dde01ed5SJani Nikula
3666dde01ed5SJani Nikula ret = kstrtobool_from_user(ubuf, len, &enable);
3667dde01ed5SJani Nikula if (ret < 0)
3668dde01ed5SJani Nikula return ret;
3669dde01ed5SJani Nikula
3670dde01ed5SJani Nikula with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
3671dde01ed5SJani Nikula if (!skl_watermark_ipc_enabled(i915) && enable)
3672dde01ed5SJani Nikula drm_info(&i915->drm,
3673dde01ed5SJani Nikula "Enabling IPC: WM will be proper only after next commit\n");
367470296670SJani Nikula i915->display.wm.ipc_enabled = enable;
3675dde01ed5SJani Nikula skl_watermark_ipc_update(i915);
3676dde01ed5SJani Nikula }
3677dde01ed5SJani Nikula
3678dde01ed5SJani Nikula return len;
3679dde01ed5SJani Nikula }
3680dde01ed5SJani Nikula
3681dde01ed5SJani Nikula static const struct file_operations skl_watermark_ipc_status_fops = {
3682dde01ed5SJani Nikula .owner = THIS_MODULE,
3683dde01ed5SJani Nikula .open = skl_watermark_ipc_status_open,
3684dde01ed5SJani Nikula .read = seq_read,
3685dde01ed5SJani Nikula .llseek = seq_lseek,
3686dde01ed5SJani Nikula .release = single_release,
3687dde01ed5SJani Nikula .write = skl_watermark_ipc_status_write
3688dde01ed5SJani Nikula };
3689dde01ed5SJani Nikula
intel_sagv_status_show(struct seq_file * m,void * unused)369014f25bd0SVille Syrjälä static int intel_sagv_status_show(struct seq_file *m, void *unused)
369114f25bd0SVille Syrjälä {
369214f25bd0SVille Syrjälä struct drm_i915_private *i915 = m->private;
369314f25bd0SVille Syrjälä static const char * const sagv_status[] = {
369414f25bd0SVille Syrjälä [I915_SAGV_UNKNOWN] = "unknown",
369514f25bd0SVille Syrjälä [I915_SAGV_DISABLED] = "disabled",
369614f25bd0SVille Syrjälä [I915_SAGV_ENABLED] = "enabled",
369714f25bd0SVille Syrjälä [I915_SAGV_NOT_CONTROLLED] = "not controlled",
369814f25bd0SVille Syrjälä };
369914f25bd0SVille Syrjälä
370014f25bd0SVille Syrjälä seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(i915)));
3701419e505dSVille Syrjälä seq_printf(m, "SAGV modparam: %s\n", str_enabled_disabled(i915->params.enable_sagv));
370214f25bd0SVille Syrjälä seq_printf(m, "SAGV status: %s\n", sagv_status[i915->display.sagv.status]);
370314f25bd0SVille Syrjälä seq_printf(m, "SAGV block time: %d usec\n", i915->display.sagv.block_time_us);
370414f25bd0SVille Syrjälä
370514f25bd0SVille Syrjälä return 0;
370614f25bd0SVille Syrjälä }
370714f25bd0SVille Syrjälä
370814f25bd0SVille Syrjälä DEFINE_SHOW_ATTRIBUTE(intel_sagv_status);
370914f25bd0SVille Syrjälä
skl_watermark_debugfs_register(struct drm_i915_private * i915)371014f25bd0SVille Syrjälä void skl_watermark_debugfs_register(struct drm_i915_private *i915)
3711dde01ed5SJani Nikula {
3712dde01ed5SJani Nikula struct drm_minor *minor = i915->drm.primary;
3713dde01ed5SJani Nikula
371414f25bd0SVille Syrjälä if (HAS_IPC(i915))
3715dde01ed5SJani Nikula debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915,
3716dde01ed5SJani Nikula &skl_watermark_ipc_status_fops);
371714f25bd0SVille Syrjälä
371814f25bd0SVille Syrjälä if (HAS_SAGV(i915))
371914f25bd0SVille Syrjälä debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, i915,
372014f25bd0SVille Syrjälä &intel_sagv_status_fops);
3721dde01ed5SJani Nikula }
3722