19f31d106STina Zhang /*
29f31d106STina Zhang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
39f31d106STina Zhang *
49f31d106STina Zhang * Permission is hereby granted, free of charge, to any person obtaining a
59f31d106STina Zhang * copy of this software and associated documentation files (the "Software"),
69f31d106STina Zhang * to deal in the Software without restriction, including without limitation
79f31d106STina Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
89f31d106STina Zhang * and/or sell copies of the Software, and to permit persons to whom the
99f31d106STina Zhang * Software is furnished to do so, subject to the following conditions:
109f31d106STina Zhang *
119f31d106STina Zhang * The above copyright notice and this permission notice (including the next
129f31d106STina Zhang * paragraph) shall be included in all copies or substantial portions of the
139f31d106STina Zhang * Software.
149f31d106STina Zhang *
159f31d106STina Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
169f31d106STina Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
179f31d106STina Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
189f31d106STina Zhang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
199f31d106STina Zhang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
209f31d106STina Zhang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
219f31d106STina Zhang * SOFTWARE.
229f31d106STina Zhang *
239f31d106STina Zhang * Authors:
249f31d106STina Zhang * Kevin Tian <kevin.tian@intel.com>
259f31d106STina Zhang *
269f31d106STina Zhang * Contributors:
279f31d106STina Zhang * Bing Niu <bing.niu@intel.com>
289f31d106STina Zhang * Xu Han <xu.han@intel.com>
299f31d106STina Zhang * Ping Gao <ping.a.gao@intel.com>
309f31d106STina Zhang * Xiaoguang Chen <xiaoguang.chen@intel.com>
319f31d106STina Zhang * Yang Liu <yang2.liu@intel.com>
329f31d106STina Zhang * Tina Zhang <tina.zhang@intel.com>
339f31d106STina Zhang *
349f31d106STina Zhang */
359f31d106STina Zhang
369f31d106STina Zhang #include <uapi/drm/drm_fourcc.h>
379f31d106STina Zhang #include "i915_drv.h"
389f31d106STina Zhang #include "gvt.h"
391c6ccad8STina Zhang #include "i915_pvinfo.h"
40*ce2fce25SMatt Roper #include "i915_reg.h"
419f31d106STina Zhang
429f31d106STina Zhang #define PRIMARY_FORMAT_NUM 16
439f31d106STina Zhang struct pixel_format {
449f31d106STina Zhang int drm_format; /* Pixel format in DRM definition */
459f31d106STina Zhang int bpp; /* Bits per pixel, 0 indicates invalid */
46b17639c7SRikard Falkeborn const char *desc; /* The description */
479f31d106STina Zhang };
489f31d106STina Zhang
49b17639c7SRikard Falkeborn static const struct pixel_format bdw_pixel_formats[] = {
509f31d106STina Zhang {DRM_FORMAT_C8, 8, "8-bit Indexed"},
519f31d106STina Zhang {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
529f31d106STina Zhang {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
539f31d106STina Zhang {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
549f31d106STina Zhang
559f31d106STina Zhang {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
569f31d106STina Zhang {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
579f31d106STina Zhang
589f31d106STina Zhang /* non-supported format has bpp default to 0 */
599f31d106STina Zhang {0, 0, NULL},
609f31d106STina Zhang };
619f31d106STina Zhang
62b17639c7SRikard Falkeborn static const struct pixel_format skl_pixel_formats[] = {
639f31d106STina Zhang {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
649f31d106STina Zhang {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
659f31d106STina Zhang {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
669f31d106STina Zhang {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
679f31d106STina Zhang
689f31d106STina Zhang {DRM_FORMAT_C8, 8, "8-bit Indexed"},
699f31d106STina Zhang {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
709f31d106STina Zhang {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
719f31d106STina Zhang {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
729f31d106STina Zhang
739f31d106STina Zhang {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
749f31d106STina Zhang {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
759f31d106STina Zhang {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
769f31d106STina Zhang {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
779f31d106STina Zhang
789f31d106STina Zhang /* non-supported format has bpp default to 0 */
799f31d106STina Zhang {0, 0, NULL},
809f31d106STina Zhang };
819f31d106STina Zhang
bdw_format_to_drm(int format)829f31d106STina Zhang static int bdw_format_to_drm(int format)
839f31d106STina Zhang {
849f31d106STina Zhang int bdw_pixel_formats_index = 6;
859f31d106STina Zhang
869f31d106STina Zhang switch (format) {
87428cb15dSVille Syrjälä case DISP_FORMAT_8BPP:
889f31d106STina Zhang bdw_pixel_formats_index = 0;
899f31d106STina Zhang break;
90428cb15dSVille Syrjälä case DISP_FORMAT_BGRX565:
919f31d106STina Zhang bdw_pixel_formats_index = 1;
929f31d106STina Zhang break;
93428cb15dSVille Syrjälä case DISP_FORMAT_BGRX888:
949f31d106STina Zhang bdw_pixel_formats_index = 2;
959f31d106STina Zhang break;
96428cb15dSVille Syrjälä case DISP_FORMAT_RGBX101010:
979f31d106STina Zhang bdw_pixel_formats_index = 3;
989f31d106STina Zhang break;
99428cb15dSVille Syrjälä case DISP_FORMAT_BGRX101010:
1009f31d106STina Zhang bdw_pixel_formats_index = 4;
1019f31d106STina Zhang break;
102428cb15dSVille Syrjälä case DISP_FORMAT_RGBX888:
1039f31d106STina Zhang bdw_pixel_formats_index = 5;
1049f31d106STina Zhang break;
1059f31d106STina Zhang
1069f31d106STina Zhang default:
1079f31d106STina Zhang break;
1089f31d106STina Zhang }
1099f31d106STina Zhang
1109f31d106STina Zhang return bdw_pixel_formats_index;
1119f31d106STina Zhang }
1129f31d106STina Zhang
skl_format_to_drm(int format,bool rgb_order,bool alpha,int yuv_order)1139f31d106STina Zhang static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
1149f31d106STina Zhang int yuv_order)
1159f31d106STina Zhang {
1169f31d106STina Zhang int skl_pixel_formats_index = 12;
1179f31d106STina Zhang
1189f31d106STina Zhang switch (format) {
1199f31d106STina Zhang case PLANE_CTL_FORMAT_INDEXED:
1209f31d106STina Zhang skl_pixel_formats_index = 4;
1219f31d106STina Zhang break;
1229f31d106STina Zhang case PLANE_CTL_FORMAT_RGB_565:
1239f31d106STina Zhang skl_pixel_formats_index = 5;
1249f31d106STina Zhang break;
1259f31d106STina Zhang case PLANE_CTL_FORMAT_XRGB_8888:
1269f31d106STina Zhang if (rgb_order)
1279f31d106STina Zhang skl_pixel_formats_index = alpha ? 6 : 7;
1289f31d106STina Zhang else
1299f31d106STina Zhang skl_pixel_formats_index = alpha ? 8 : 9;
1309f31d106STina Zhang break;
1319f31d106STina Zhang case PLANE_CTL_FORMAT_XRGB_2101010:
1329f31d106STina Zhang skl_pixel_formats_index = rgb_order ? 10 : 11;
1339f31d106STina Zhang break;
1349f31d106STina Zhang case PLANE_CTL_FORMAT_YUV422:
1359f31d106STina Zhang skl_pixel_formats_index = yuv_order >> 16;
1369f31d106STina Zhang if (skl_pixel_formats_index > 3)
1379f31d106STina Zhang return -EINVAL;
1389f31d106STina Zhang break;
1399f31d106STina Zhang
1409f31d106STina Zhang default:
1419f31d106STina Zhang break;
1429f31d106STina Zhang }
1439f31d106STina Zhang
1449f31d106STina Zhang return skl_pixel_formats_index;
1459f31d106STina Zhang }
1469f31d106STina Zhang
intel_vgpu_get_stride(struct intel_vgpu * vgpu,int pipe,u32 tiled,int stride_mask,int bpp)1479f31d106STina Zhang static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
1489f31d106STina Zhang u32 tiled, int stride_mask, int bpp)
1499f31d106STina Zhang {
150a61ac1e7SChris Wilson struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1519f31d106STina Zhang
15290551a12SZhenyu Wang u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
1539f31d106STina Zhang u32 stride = stride_reg;
1549f31d106STina Zhang
155d8d12312SLucas De Marchi if (GRAPHICS_VER(dev_priv) >= 9) {
1569f31d106STina Zhang switch (tiled) {
1579f31d106STina Zhang case PLANE_CTL_TILED_LINEAR:
1589f31d106STina Zhang stride = stride_reg * 64;
1599f31d106STina Zhang break;
1609f31d106STina Zhang case PLANE_CTL_TILED_X:
1619f31d106STina Zhang stride = stride_reg * 512;
1629f31d106STina Zhang break;
1639f31d106STina Zhang case PLANE_CTL_TILED_Y:
1649f31d106STina Zhang stride = stride_reg * 128;
1659f31d106STina Zhang break;
1669f31d106STina Zhang case PLANE_CTL_TILED_YF:
1679f31d106STina Zhang if (bpp == 8)
1689f31d106STina Zhang stride = stride_reg * 64;
1699f31d106STina Zhang else if (bpp == 16 || bpp == 32 || bpp == 64)
1709f31d106STina Zhang stride = stride_reg * 128;
1719f31d106STina Zhang else
1729f31d106STina Zhang gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
1739f31d106STina Zhang break;
1749f31d106STina Zhang default:
1759f31d106STina Zhang gvt_dbg_core("skl: unsupported tile format:%x\n",
1769f31d106STina Zhang tiled);
1779f31d106STina Zhang }
1789f31d106STina Zhang }
1799f31d106STina Zhang
1809f31d106STina Zhang return stride;
1819f31d106STina Zhang }
1829f31d106STina Zhang
get_active_pipe(struct intel_vgpu * vgpu)1839f31d106STina Zhang static int get_active_pipe(struct intel_vgpu *vgpu)
1849f31d106STina Zhang {
1859f31d106STina Zhang int i;
1869f31d106STina Zhang
1879f31d106STina Zhang for (i = 0; i < I915_MAX_PIPES; i++)
1889f31d106STina Zhang if (pipe_is_enabled(vgpu, i))
1899f31d106STina Zhang break;
1909f31d106STina Zhang
1919f31d106STina Zhang return i;
1929f31d106STina Zhang }
1939f31d106STina Zhang
1949f31d106STina Zhang /**
1959f31d106STina Zhang * intel_vgpu_decode_primary_plane - Decode primary plane
1969f31d106STina Zhang * @vgpu: input vgpu
1979f31d106STina Zhang * @plane: primary plane to save decoded info
1989f31d106STina Zhang * This function is called for decoding plane
1999f31d106STina Zhang *
2009f31d106STina Zhang * Returns:
2019f31d106STina Zhang * 0 on success, non-zero if failed.
2029f31d106STina Zhang */
intel_vgpu_decode_primary_plane(struct intel_vgpu * vgpu,struct intel_vgpu_primary_plane_format * plane)2039f31d106STina Zhang int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
2049f31d106STina Zhang struct intel_vgpu_primary_plane_format *plane)
2059f31d106STina Zhang {
206a61ac1e7SChris Wilson struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
2079f31d106STina Zhang u32 val, fmt;
2089f31d106STina Zhang int pipe;
2099f31d106STina Zhang
2109f31d106STina Zhang pipe = get_active_pipe(vgpu);
2119f31d106STina Zhang if (pipe >= I915_MAX_PIPES)
2129f31d106STina Zhang return -ENODEV;
2139f31d106STina Zhang
21490551a12SZhenyu Wang val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
215428cb15dSVille Syrjälä plane->enabled = !!(val & DISP_ENABLE);
2169f31d106STina Zhang if (!plane->enabled)
2179f31d106STina Zhang return -ENODEV;
2189f31d106STina Zhang
219d8d12312SLucas De Marchi if (GRAPHICS_VER(dev_priv) >= 9) {
220b244ffa1SZhenyu Wang plane->tiled = val & PLANE_CTL_TILED_MASK;
2219f31d106STina Zhang fmt = skl_format_to_drm(
22212d7d858SVille Syrjälä val & PLANE_CTL_FORMAT_MASK_SKL,
2239f31d106STina Zhang val & PLANE_CTL_ORDER_RGBX,
2249f31d106STina Zhang val & PLANE_CTL_ALPHA_MASK,
2259f31d106STina Zhang val & PLANE_CTL_YUV422_ORDER_MASK);
226461bd622SGustavo A. R. Silva
227461bd622SGustavo A. R. Silva if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
228461bd622SGustavo A. R. Silva gvt_vgpu_err("Out-of-bounds pixel format index\n");
229461bd622SGustavo A. R. Silva return -EINVAL;
230461bd622SGustavo A. R. Silva }
231461bd622SGustavo A. R. Silva
2329f31d106STina Zhang plane->bpp = skl_pixel_formats[fmt].bpp;
2339f31d106STina Zhang plane->drm_format = skl_pixel_formats[fmt].drm_format;
2349f31d106STina Zhang } else {
235428cb15dSVille Syrjälä plane->tiled = val & DISP_TILED;
236428cb15dSVille Syrjälä fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK);
2379f31d106STina Zhang plane->bpp = bdw_pixel_formats[fmt].bpp;
2389f31d106STina Zhang plane->drm_format = bdw_pixel_formats[fmt].drm_format;
2399f31d106STina Zhang }
2409f31d106STina Zhang
2419f31d106STina Zhang if (!plane->bpp) {
2429f31d106STina Zhang gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
2439f31d106STina Zhang return -EINVAL;
2449f31d106STina Zhang }
2459f31d106STina Zhang
2469f31d106STina Zhang plane->hw_format = fmt;
2479f31d106STina Zhang
24890551a12SZhenyu Wang plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
249c2514409SXiong Zhang if (!vgpu_gmadr_is_valid(vgpu, plane->base))
2509f31d106STina Zhang return -EINVAL;
2519f31d106STina Zhang
2529f31d106STina Zhang plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
2539f31d106STina Zhang if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
254a733390fSXiong Zhang gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
255a733390fSXiong Zhang plane->base);
2569f31d106STina Zhang return -EINVAL;
2579f31d106STina Zhang }
2589f31d106STina Zhang
259b244ffa1SZhenyu Wang plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
260d8d12312SLucas De Marchi (GRAPHICS_VER(dev_priv) >= 9) ?
2614a136d59STina Zhang (_PRI_PLANE_STRIDE_MASK >> 6) :
2629f31d106STina Zhang _PRI_PLANE_STRIDE_MASK, plane->bpp);
2639f31d106STina Zhang
26490551a12SZhenyu Wang plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
2659f31d106STina Zhang _PIPE_H_SRCSZ_SHIFT;
2669f31d106STina Zhang plane->width += 1;
26790551a12SZhenyu Wang plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
2689f31d106STina Zhang _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
2699f31d106STina Zhang plane->height += 1; /* raw height is one minus the real value */
2709f31d106STina Zhang
27190551a12SZhenyu Wang val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
2729f31d106STina Zhang plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
2739f31d106STina Zhang _PRI_PLANE_X_OFF_SHIFT;
2749f31d106STina Zhang plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
2759f31d106STina Zhang _PRI_PLANE_Y_OFF_SHIFT;
2769f31d106STina Zhang
2779f31d106STina Zhang return 0;
2789f31d106STina Zhang }
2799f31d106STina Zhang
2809f31d106STina Zhang #define CURSOR_FORMAT_NUM (1 << 6)
2819f31d106STina Zhang struct cursor_mode_format {
2829f31d106STina Zhang int drm_format; /* Pixel format in DRM definition */
2839f31d106STina Zhang u8 bpp; /* Bits per pixel; 0 indicates invalid */
2849f31d106STina Zhang u32 width; /* In pixel */
2859f31d106STina Zhang u32 height; /* In lines */
286b17639c7SRikard Falkeborn const char *desc; /* The description */
2879f31d106STina Zhang };
2889f31d106STina Zhang
289b17639c7SRikard Falkeborn static const struct cursor_mode_format cursor_pixel_formats[] = {
2909f31d106STina Zhang {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
2919f31d106STina Zhang {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
2929f31d106STina Zhang {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
2939f31d106STina Zhang {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
2949f31d106STina Zhang
2959f31d106STina Zhang /* non-supported format has bpp default to 0 */
2969f31d106STina Zhang {0, 0, 0, 0, NULL},
2979f31d106STina Zhang };
2989f31d106STina Zhang
cursor_mode_to_drm(int mode)2999f31d106STina Zhang static int cursor_mode_to_drm(int mode)
3009f31d106STina Zhang {
3019f31d106STina Zhang int cursor_pixel_formats_index = 4;
3029f31d106STina Zhang
3039f31d106STina Zhang switch (mode) {
304b99b9ec1SVille Syrjälä case MCURSOR_MODE_128_ARGB_AX:
3059f31d106STina Zhang cursor_pixel_formats_index = 0;
3069f31d106STina Zhang break;
307b99b9ec1SVille Syrjälä case MCURSOR_MODE_256_ARGB_AX:
3089f31d106STina Zhang cursor_pixel_formats_index = 1;
3099f31d106STina Zhang break;
310b99b9ec1SVille Syrjälä case MCURSOR_MODE_64_ARGB_AX:
3119f31d106STina Zhang cursor_pixel_formats_index = 2;
3129f31d106STina Zhang break;
313b99b9ec1SVille Syrjälä case MCURSOR_MODE_64_32B_AX:
3149f31d106STina Zhang cursor_pixel_formats_index = 3;
3159f31d106STina Zhang break;
3169f31d106STina Zhang
3179f31d106STina Zhang default:
3189f31d106STina Zhang break;
3199f31d106STina Zhang }
3209f31d106STina Zhang
3219f31d106STina Zhang return cursor_pixel_formats_index;
3229f31d106STina Zhang }
3239f31d106STina Zhang
3249f31d106STina Zhang /**
3259f31d106STina Zhang * intel_vgpu_decode_cursor_plane - Decode sprite plane
3269f31d106STina Zhang * @vgpu: input vgpu
3279f31d106STina Zhang * @plane: cursor plane to save decoded info
3289f31d106STina Zhang * This function is called for decoding plane
3299f31d106STina Zhang *
3309f31d106STina Zhang * Returns:
3319f31d106STina Zhang * 0 on success, non-zero if failed.
3329f31d106STina Zhang */
intel_vgpu_decode_cursor_plane(struct intel_vgpu * vgpu,struct intel_vgpu_cursor_plane_format * plane)3339f31d106STina Zhang int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
3349f31d106STina Zhang struct intel_vgpu_cursor_plane_format *plane)
3359f31d106STina Zhang {
336a61ac1e7SChris Wilson struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
3379f31d106STina Zhang u32 val, mode, index;
3389f31d106STina Zhang u32 alpha_plane, alpha_force;
3399f31d106STina Zhang int pipe;
3409f31d106STina Zhang
3419f31d106STina Zhang pipe = get_active_pipe(vgpu);
3429f31d106STina Zhang if (pipe >= I915_MAX_PIPES)
3439f31d106STina Zhang return -ENODEV;
3449f31d106STina Zhang
34590551a12SZhenyu Wang val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
346348abd4cSVille Syrjälä mode = val & MCURSOR_MODE_MASK;
347b99b9ec1SVille Syrjälä plane->enabled = (mode != MCURSOR_MODE_DISABLE);
3489f31d106STina Zhang if (!plane->enabled)
3499f31d106STina Zhang return -ENODEV;
3509f31d106STina Zhang
3519f31d106STina Zhang index = cursor_mode_to_drm(mode);
3529f31d106STina Zhang
3539f31d106STina Zhang if (!cursor_pixel_formats[index].bpp) {
3549f31d106STina Zhang gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
3559f31d106STina Zhang return -EINVAL;
3569f31d106STina Zhang }
3579f31d106STina Zhang plane->mode = mode;
3589f31d106STina Zhang plane->bpp = cursor_pixel_formats[index].bpp;
3599f31d106STina Zhang plane->drm_format = cursor_pixel_formats[index].drm_format;
3609f31d106STina Zhang plane->width = cursor_pixel_formats[index].width;
3619f31d106STina Zhang plane->height = cursor_pixel_formats[index].height;
3629f31d106STina Zhang
3639f31d106STina Zhang alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
3649f31d106STina Zhang _CURSOR_ALPHA_PLANE_SHIFT;
3659f31d106STina Zhang alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
3669f31d106STina Zhang _CURSOR_ALPHA_FORCE_SHIFT;
3679f31d106STina Zhang if (alpha_plane || alpha_force)
3689f31d106STina Zhang gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
3699f31d106STina Zhang alpha_plane, alpha_force);
3709f31d106STina Zhang
37190551a12SZhenyu Wang plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
372c2514409SXiong Zhang if (!vgpu_gmadr_is_valid(vgpu, plane->base))
3739f31d106STina Zhang return -EINVAL;
3749f31d106STina Zhang
3759f31d106STina Zhang plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
3769f31d106STina Zhang if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
377a733390fSXiong Zhang gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n",
378a733390fSXiong Zhang plane->base);
3799f31d106STina Zhang return -EINVAL;
3809f31d106STina Zhang }
3819f31d106STina Zhang
38290551a12SZhenyu Wang val = vgpu_vreg_t(vgpu, CURPOS(pipe));
3839f31d106STina Zhang plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
3849f31d106STina Zhang plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
3859f31d106STina Zhang plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
3869f31d106STina Zhang plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
3879f31d106STina Zhang
3881c6ccad8STina Zhang plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot));
3891c6ccad8STina Zhang plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot));
3909f31d106STina Zhang return 0;
3919f31d106STina Zhang }
3929f31d106STina Zhang
3939f31d106STina Zhang #define SPRITE_FORMAT_NUM (1 << 3)
3949f31d106STina Zhang
395b17639c7SRikard Falkeborn static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
3969f31d106STina Zhang [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
3979f31d106STina Zhang [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
3989f31d106STina Zhang [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
3999f31d106STina Zhang [0x4] = {DRM_FORMAT_AYUV, 32,
4009f31d106STina Zhang "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
4019f31d106STina Zhang };
4029f31d106STina Zhang
4039f31d106STina Zhang /**
4049f31d106STina Zhang * intel_vgpu_decode_sprite_plane - Decode sprite plane
4059f31d106STina Zhang * @vgpu: input vgpu
4069f31d106STina Zhang * @plane: sprite plane to save decoded info
4079f31d106STina Zhang * This function is called for decoding plane
4089f31d106STina Zhang *
4099f31d106STina Zhang * Returns:
4109f31d106STina Zhang * 0 on success, non-zero if failed.
4119f31d106STina Zhang */
intel_vgpu_decode_sprite_plane(struct intel_vgpu * vgpu,struct intel_vgpu_sprite_plane_format * plane)4129f31d106STina Zhang int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
4139f31d106STina Zhang struct intel_vgpu_sprite_plane_format *plane)
4149f31d106STina Zhang {
4159f31d106STina Zhang u32 val, fmt;
4169f31d106STina Zhang u32 color_order, yuv_order;
4179f31d106STina Zhang int drm_format;
4189f31d106STina Zhang int pipe;
4199f31d106STina Zhang
4209f31d106STina Zhang pipe = get_active_pipe(vgpu);
4219f31d106STina Zhang if (pipe >= I915_MAX_PIPES)
4229f31d106STina Zhang return -ENODEV;
4239f31d106STina Zhang
42490551a12SZhenyu Wang val = vgpu_vreg_t(vgpu, SPRCTL(pipe));
4259f31d106STina Zhang plane->enabled = !!(val & SPRITE_ENABLE);
4269f31d106STina Zhang if (!plane->enabled)
4279f31d106STina Zhang return -ENODEV;
4289f31d106STina Zhang
4299f31d106STina Zhang plane->tiled = !!(val & SPRITE_TILED);
4309f31d106STina Zhang color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
43162f887aeSVille Syrjälä yuv_order = (val & SPRITE_YUV_ORDER_MASK) >>
4329f31d106STina Zhang _SPRITE_YUV_ORDER_SHIFT;
4339f31d106STina Zhang
4342f609fafSVille Syrjälä fmt = (val & SPRITE_FORMAT_MASK) >> _SPRITE_FMT_SHIFT;
4359f31d106STina Zhang if (!sprite_pixel_formats[fmt].bpp) {
4369f31d106STina Zhang gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
4379f31d106STina Zhang return -EINVAL;
4389f31d106STina Zhang }
4399f31d106STina Zhang plane->hw_format = fmt;
4409f31d106STina Zhang plane->bpp = sprite_pixel_formats[fmt].bpp;
4419f31d106STina Zhang drm_format = sprite_pixel_formats[fmt].drm_format;
4429f31d106STina Zhang
4439f31d106STina Zhang /* Order of RGB values in an RGBxxx buffer may be ordered RGB or
4449f31d106STina Zhang * BGR depending on the state of the color_order field
4459f31d106STina Zhang */
4469f31d106STina Zhang if (!color_order) {
4479f31d106STina Zhang if (drm_format == DRM_FORMAT_XRGB2101010)
4489f31d106STina Zhang drm_format = DRM_FORMAT_XBGR2101010;
4499f31d106STina Zhang else if (drm_format == DRM_FORMAT_XRGB8888)
4509f31d106STina Zhang drm_format = DRM_FORMAT_XBGR8888;
4519f31d106STina Zhang }
4529f31d106STina Zhang
4539f31d106STina Zhang if (drm_format == DRM_FORMAT_YUV422) {
4549f31d106STina Zhang switch (yuv_order) {
4559f31d106STina Zhang case 0:
4569f31d106STina Zhang drm_format = DRM_FORMAT_YUYV;
4579f31d106STina Zhang break;
4589f31d106STina Zhang case 1:
4599f31d106STina Zhang drm_format = DRM_FORMAT_UYVY;
4609f31d106STina Zhang break;
4619f31d106STina Zhang case 2:
4629f31d106STina Zhang drm_format = DRM_FORMAT_YVYU;
4639f31d106STina Zhang break;
4649f31d106STina Zhang case 3:
4659f31d106STina Zhang drm_format = DRM_FORMAT_VYUY;
4669f31d106STina Zhang break;
4679f31d106STina Zhang default:
4689f31d106STina Zhang /* yuv_order has only 2 bits */
4699f31d106STina Zhang break;
4709f31d106STina Zhang }
4719f31d106STina Zhang }
4729f31d106STina Zhang
4739f31d106STina Zhang plane->drm_format = drm_format;
4749f31d106STina Zhang
47590551a12SZhenyu Wang plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
476c2514409SXiong Zhang if (!vgpu_gmadr_is_valid(vgpu, plane->base))
4779f31d106STina Zhang return -EINVAL;
4789f31d106STina Zhang
4799f31d106STina Zhang plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
4809f31d106STina Zhang if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
481a733390fSXiong Zhang gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n",
482a733390fSXiong Zhang plane->base);
4839f31d106STina Zhang return -EINVAL;
4849f31d106STina Zhang }
4859f31d106STina Zhang
48690551a12SZhenyu Wang plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &
4879f31d106STina Zhang _SPRITE_STRIDE_MASK;
4889f31d106STina Zhang
48990551a12SZhenyu Wang val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));
4909f31d106STina Zhang plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
4919f31d106STina Zhang _SPRITE_SIZE_HEIGHT_SHIFT;
4929f31d106STina Zhang plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
4939f31d106STina Zhang _SPRITE_SIZE_WIDTH_SHIFT;
4949f31d106STina Zhang plane->height += 1; /* raw height is one minus the real value */
4959f31d106STina Zhang plane->width += 1; /* raw width is one minus the real value */
4969f31d106STina Zhang
49790551a12SZhenyu Wang val = vgpu_vreg_t(vgpu, SPRPOS(pipe));
4989f31d106STina Zhang plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
4999f31d106STina Zhang plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
5009f31d106STina Zhang
50190551a12SZhenyu Wang val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));
5029f31d106STina Zhang plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
5039f31d106STina Zhang _SPRITE_OFFSET_START_X_SHIFT;
5049f31d106STina Zhang plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
5059f31d106STina Zhang _SPRITE_OFFSET_START_Y_SHIFT;
5069f31d106STina Zhang
5079f31d106STina Zhang return 0;
5089f31d106STina Zhang }
509