105aa8e01SMatt Roper /* SPDX-License-Identifier: MIT */ 205aa8e01SMatt Roper /* 305aa8e01SMatt Roper * Copyright © 2023 Intel Corporation 405aa8e01SMatt Roper */ 505aa8e01SMatt Roper 605aa8e01SMatt Roper #ifndef __INTEL_DISPLAY_DEVICE_H__ 705aa8e01SMatt Roper #define __INTEL_DISPLAY_DEVICE_H__ 805aa8e01SMatt Roper 905aa8e01SMatt Roper #include <linux/types.h> 1005aa8e01SMatt Roper 115e0bff2bSMatt Roper #include "intel_display_limits.h" 1205aa8e01SMatt Roper 1312e6f6dcSMatt Roper struct drm_i915_private; 144ae7eb92SJani Nikula struct drm_printer; 1512e6f6dcSMatt Roper 1605aa8e01SMatt Roper #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 1705aa8e01SMatt Roper /* Keep in alphabetical order */ \ 1805aa8e01SMatt Roper func(cursor_needs_physical); \ 1905aa8e01SMatt Roper func(has_cdclk_crawl); \ 2005aa8e01SMatt Roper func(has_cdclk_squash); \ 2105aa8e01SMatt Roper func(has_ddi); \ 2205aa8e01SMatt Roper func(has_dp_mst); \ 2305aa8e01SMatt Roper func(has_dsb); \ 2405aa8e01SMatt Roper func(has_fpga_dbg); \ 2505aa8e01SMatt Roper func(has_gmch); \ 2605aa8e01SMatt Roper func(has_hotplug); \ 2705aa8e01SMatt Roper func(has_hti); \ 2805aa8e01SMatt Roper func(has_ipc); \ 2905aa8e01SMatt Roper func(has_overlay); \ 3005aa8e01SMatt Roper func(has_psr); \ 3105aa8e01SMatt Roper func(has_psr_hw_tracking); \ 3205aa8e01SMatt Roper func(overlay_needs_physical); \ 3305aa8e01SMatt Roper func(supports_tv); 3405aa8e01SMatt Roper 3595c08508SMatt Roper #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 3695c08508SMatt Roper #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl) 3795c08508SMatt Roper #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash) 3895c08508SMatt Roper #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7) 3995c08508SMatt Roper #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915)) 4095c08508SMatt Roper #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi) 4195c08508SMatt Roper #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0) 4295c08508SMatt Roper #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc) 4395c08508SMatt Roper #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) 4495c08508SMatt Roper #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst) 4595c08508SMatt Roper #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 4695c08508SMatt Roper #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) 4795c08508SMatt Roper #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb) 4895c08508SMatt Roper #define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc) 4975170320SVille Syrjälä #define HAS_DSC_MST(__i915) (DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915)) 5095c08508SMatt Roper #define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0) 5195c08508SMatt Roper #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg) 5295c08508SMatt Roper #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2) 5395c08508SMatt Roper #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4) 5495c08508SMatt Roper #define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915)) 5595c08508SMatt Roper #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch) 5695c08508SMatt Roper #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 5795c08508SMatt Roper #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc) 58927a8e38SDnyaneshwar Bhadane #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915)) 5995c08508SMatt Roper #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10)) 6095c08508SMatt Roper #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) 6195c08508SMatt Roper #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) 6295c08508SMatt Roper #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) 6395c08508SMatt Roper #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) 6495c08508SMatt Roper #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) 6595c08508SMatt Roper #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) 6695c08508SMatt Roper #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) 6795c08508SMatt Roper #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ 6895c08508SMatt Roper BIT(trans)) != 0) 6995c08508SMatt Roper #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) 7095c08508SMatt Roper #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) 7195c08508SMatt Roper #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) 7295c08508SMatt Roper #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) 7395c08508SMatt Roper #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv) 7495c08508SMatt Roper 7518e0deeeSMatt Roper struct intel_display_runtime_info { 7618e0deeeSMatt Roper struct { 7718e0deeeSMatt Roper u16 ver; 7818e0deeeSMatt Roper u16 rel; 7918e0deeeSMatt Roper u16 step; 8018e0deeeSMatt Roper } ip; 8118e0deeeSMatt Roper 8218e0deeeSMatt Roper u8 pipe_mask; 8318e0deeeSMatt Roper u8 cpu_transcoder_mask; 842798e4d1SVille Syrjälä u16 port_mask; 8518e0deeeSMatt Roper 8618e0deeeSMatt Roper u8 num_sprites[I915_MAX_PIPES]; 8718e0deeeSMatt Roper u8 num_scalers[I915_MAX_PIPES]; 8818e0deeeSMatt Roper 8918e0deeeSMatt Roper u8 fbc_mask; 9018e0deeeSMatt Roper 9118e0deeeSMatt Roper bool has_hdcp; 9218e0deeeSMatt Roper bool has_dmc; 9318e0deeeSMatt Roper bool has_dsc; 9418e0deeeSMatt Roper }; 9518e0deeeSMatt Roper 9605aa8e01SMatt Roper struct intel_display_device_info { 9718e0deeeSMatt Roper /* Initial runtime info. */ 9818e0deeeSMatt Roper const struct intel_display_runtime_info __runtime_defaults; 9918e0deeeSMatt Roper 10005aa8e01SMatt Roper u8 abox_mask; 10105aa8e01SMatt Roper 10205aa8e01SMatt Roper struct { 10305aa8e01SMatt Roper u16 size; /* in blocks */ 10405aa8e01SMatt Roper u8 slice_mask; 10505aa8e01SMatt Roper } dbuf; 10605aa8e01SMatt Roper 10705aa8e01SMatt Roper #define DEFINE_FLAG(name) u8 name:1 10805aa8e01SMatt Roper DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 10905aa8e01SMatt Roper #undef DEFINE_FLAG 11005aa8e01SMatt Roper 11105aa8e01SMatt Roper /* Global register offset for the display engine */ 11205aa8e01SMatt Roper u32 mmio_offset; 11305aa8e01SMatt Roper 11405aa8e01SMatt Roper /* Register offsets for the various display pipes and transcoders */ 11505aa8e01SMatt Roper u32 pipe_offsets[I915_MAX_TRANSCODERS]; 11605aa8e01SMatt Roper u32 trans_offsets[I915_MAX_TRANSCODERS]; 11705aa8e01SMatt Roper u32 cursor_offsets[I915_MAX_PIPES]; 11805aa8e01SMatt Roper 11905aa8e01SMatt Roper struct { 12005aa8e01SMatt Roper u32 degamma_lut_size; 12105aa8e01SMatt Roper u32 gamma_lut_size; 12205aa8e01SMatt Roper u32 degamma_lut_tests; 12305aa8e01SMatt Roper u32 gamma_lut_tests; 12405aa8e01SMatt Roper } color; 12505aa8e01SMatt Roper }; 12605aa8e01SMatt Roper 12769d43981SMatt Roper const struct intel_display_device_info * 12812e6f6dcSMatt Roper intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid, 12912e6f6dcSMatt Roper u16 *ver, u16 *rel, u16 *step); 1302d0cdf60SMatt Roper void intel_display_device_info_runtime_init(struct drm_i915_private *i915); 13169d43981SMatt Roper 1324ae7eb92SJani Nikula void intel_display_device_info_print(const struct intel_display_device_info *info, 1334ae7eb92SJani Nikula const struct intel_display_runtime_info *runtime, 1344ae7eb92SJani Nikula struct drm_printer *p); 1354ae7eb92SJani Nikula 13605aa8e01SMatt Roper #endif 137