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Searched refs:GPIO_BASE (Results 1 – 25 of 46) sorted by relevance

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/openbmc/u-boot/drivers/gpio/
H A Dkona_gpio.c10 #define GPIO_BASE (void *)GPIO2_BASE_ADDR macro
49 writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); in gpio_request()
51 value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio); in gpio_request()
52 writel(value, GPIO_BASE + off); in gpio_request()
61 writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); in gpio_free()
63 value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio); in gpio_free()
64 writel(value, GPIO_BASE + off); in gpio_free()
73 val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); in gpio_direction_input()
76 writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); in gpio_direction_input()
87 val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); in gpio_direction_output()
[all …]
/openbmc/u-boot/board/renesas/sh7785lcr/
H A Dlowlevel_init.S188 #define GPIO_BASE 0xffe70000 macro
189 PACR_A: .long GPIO_BASE + 0x00
190 PBCR_A: .long GPIO_BASE + 0x02
191 PCCR_A: .long GPIO_BASE + 0x04
192 PDCR_A: .long GPIO_BASE + 0x06
193 PECR_A: .long GPIO_BASE + 0x08
194 PFCR_A: .long GPIO_BASE + 0x0a
195 PGCR_A: .long GPIO_BASE + 0x0c
196 PHCR_A: .long GPIO_BASE + 0x0e
197 PJCR_A: .long GPIO_BASE + 0x10
[all …]
/openbmc/openbmc/meta-quanta/meta-q71l/recipes-phosphor/quanta-powerctrl/files/
H A Dinit_once.sh15 GPIO_BASE=$(cat /sys/devices/platform/ahb/1e780000.apb/1e780000.gpio/gpio/*/base)
18 set_gpio_active_low $((GPIO_BASE + 128 + 4)) high
21 set_gpio_active_low $((GPIO_BASE + 128 + 6)) high
24 set_gpio_active_low $((GPIO_BASE + 0 + 3)) high
27 set_gpio_active_low $((GPIO_BASE + 32 + 4)) high
30 set_gpio_active_low $((GPIO_BASE + 24 + 3)) high
H A Dpoweron.sh3 GPIO_BASE=$(cat /sys/devices/platform/ahb/1e780000.apb/1e780000.gpio/gpio/*/base)
4 GPIO_NUM=$((GPIO_BASE + 24 + 3))
H A Dpoweroff.sh3 GPIO_BASE=$(cat /sys/devices/platform/ahb/1e780000.apb/1e780000.gpio/gpio/*/base)
4 GPIO_NUM=$((GPIO_BASE + 24 + 3))
/openbmc/linux/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
H A Dgpio_private.h31 OP___assert(GPIO_BASE[ID] != (hrt_address) - 1); in gpio_reg_store()
32 ia_css_device_store_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data), value); in gpio_reg_store()
41 OP___assert(GPIO_BASE[ID] != (hrt_address) - 1); in gpio_reg_load()
42 return ia_css_device_load_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data)); in gpio_reg_load()
H A Dtimed_ctrl.c71 OP___assert(GPIO_BASE[GPIO_ID] != (hrt_address)-1); in timed_ctrl_snd_gpio_commnd()
74 GPIO_BASE[GPIO_ID] + offset, value); in timed_ctrl_snd_gpio_commnd()
/openbmc/openbmc/meta-facebook/meta-tiogapass/recipes-tiogapass/fb-powerctrl/files/
H A Dsetup_gpio14 GPIO_BASE=$(cat /sys/class/gpio/gpio*/base)
17 set_gpio_active_low $((GPIO_BASE + 144 +1)) low
20 set_gpio_active_low $((GPIO_BASE + 212)) high
/openbmc/u-boot/board/aspeed/ast2600_intel/
H A Dintel.c52 #define GPIO_BASE 0x1e780000 macro
53 #define GPIO_ABCD_VAL (GPIO_BASE + 0x0)
57 #define GPIO_ABCD_DIR (GPIO_BASE + 0x4)
61 #define GPIO_EFGH_DIR (GPIO_BASE + 0x24)
63 #define SGPIO_M1_CONF (GPIO_BASE + 0x554)
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dgpio.c10 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in jz47xx_gpio_get_value()
19 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in jz47xx_gpio_direction_input()
30 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in jz47xx_gpio_direction_output()
/openbmc/u-boot/board/imgtec/ci20/
H A Dci20.c28 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_mux_mmc()
43 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_mux_eth()
70 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_mux_jtag()
82 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_mux_nand()
106 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_mux_uart()
217 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_revision()
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dmem_io.h24 #define GPIO_BASE 0x1e780000 macro
41 #define GPIO_RD(offset) readl(GPIO_BASE + offset)
42 #define GPIO_WR(value, offset) writel(value, GPIO_BASE + offset)
/openbmc/skeleton/pysystemmgr/obmc/system/
H A D__init__.py17 GPIO_BASE = find_gpio_base() variable
26 base = a * 8 + GPIO_BASE
/openbmc/u-boot/drivers/pch/
H A Dpch9.c10 #define GPIO_BASE 0x48 macro
38 dm_pci_read_config32(dev, GPIO_BASE, &base); in pch9_get_gpio_base()
H A Dpch7.c10 #define GPIO_BASE 0x44 macro
54 dm_pci_read_config32(dev, GPIO_BASE, &base); in pch7_get_gpio_base()
/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dled.c17 register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; in switch_LED_on()
25 register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; in switch_LED_off()
/openbmc/openbmc-test-automation/data/
H A DPalmetto.py6 GPIO_BASE = 320 variable
391 base = a * 8 + GPIO_BASE
/openbmc/u-boot/board/aspeed/evb_ast2600/
H A Devb_ast2600.c15 #define GPIO_BASE 0x1e780000 macro
68 writel(value, GPIO_BASE + GPIO554); in sgpio_init()
/openbmc/u-boot/board/renesas/sh7752evb/
H A Dsh7752evb.c24 struct gpio_regs *gpio = GPIO_BASE; in init_gpio()
84 struct gpio_regs *gpio = GPIO_BASE; in init_gether_mdio()
164 struct gpio_regs *gpio = GPIO_BASE; in board_mmc_init()
/openbmc/u-boot/board/renesas/sh7753evb/
H A Dsh7753evb.c24 struct gpio_regs *gpio = GPIO_BASE; in init_gpio()
91 struct gpio_regs *gpio = GPIO_BASE; in init_gether_mdio()
180 struct gpio_regs *gpio = GPIO_BASE; in board_mmc_init()
/openbmc/u-boot/board/aspeed/ast2600_dcscm/
H A Dast2600_dcscm.c15 #define GPIO_BASE 0x1e780000 macro
68 writel(value, GPIO_BASE + GPIO554); in sgpio_init()
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dbd82x6x.c23 #define GPIO_BASE 0x48 macro
202 dm_pci_read_config32(dev, GPIO_BASE, &base); in bd82x6x_get_gpio_base()
/openbmc/linux/drivers/mfd/
H A Dlpc_sch.c25 #define GPIO_BASE 0x44 macro
148 ret = lpc_sch_populate_cell(dev, GPIO_BASE, "sch_gpio", in lpc_sch_probe()
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h28 #define GPIO_BASE 0x40028000 /* GPIO registers base */ macro
/openbmc/u-boot/board/timll/devkit3250/
H A Ddevkit3250_spl.c16 static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;

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