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Searched refs:FPGA (Results 1 – 25 of 77) sorted by relevance

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/openbmc/u-boot/drivers/fpga/
H A DKconfig1 menu "FPGA support"
3 config FPGA config
7 bool "Enable Altera FPGA drivers"
8 select FPGA
10 Say Y here to enable the Altera FPGA driver
12 This provides basic infrastructure to support Altera FPGA devices.
13 Enable Altera FPGA specific functions which includes bitstream
17 bool "Enable Gen5 and Arria10 common FPGA drivers"
20 Say Y here to enable the Gen5 and Arria10 common FPGA driver
25 bool "Enable Altera FPGA driver for Cyclone II"
[all …]
/openbmc/u-boot/Documentation/devicetree/bindings/misc/
H A Dgdsys,iocon_fpga.txt1 gdsys IHS FPGA for CON devices
3 The gdsys IHS FPGA is the main FPGA on gdsys CON devices. This driver provides
4 support for enabling and starting the FPGA, as well as verifying working bus
9 - reset-gpios: List of GPIOs controlling the FPGA's reset
10 - done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
H A Dgdsys,iocpu_fpga.txt1 gdsys IHS FPGA for CPU devices
3 The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides
4 support for enabling and starting the FPGA, as well as verifying working bus
9 - reset-gpios: List of GPIOs controlling the FPGA's reset
10 - done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
H A Dgdsys,io-endpoint.txt1 gdsys IO endpoint of IHS FPGA devices
3 The IO endpoint of IHS FPGA devices is a packet-based transmission interface
5 FPGA's main ethernet connection.
10 the FPGA's register space)
H A Dgdsys,soc.txt5 within the FPGA's register space.
8 - fpga: A phandle to the controlling IHS FPGA
/openbmc/u-boot/doc/device-tree-bindings/fpga/
H A Daltera-socfpga-a10-fpga-mgr.txt1 Altera SOCFPGA Arria10 FPGA Manager
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
/openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/
H A Drelease-notes.rst36 …- Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide can …
42 - This software release is tested on Corstone-1000 FPGA version AN550_v2
66 …- Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide can …
73 - This software release is tested on Corstone-1000 FPGA version AN550_v2
84 …- FPGA supports Linux distro install and boot through installer. However, FVP only supports openSU…
85 …- Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide can …
96 - This software release is tested on Corstone-1000 FPGA version AN550_v2
107 …- The external-system can not be reset individually on (or using) AN550_v1 FPGA release. However, …
108 …- FPGA supports Linux distro install and boot through installer. However, FVP only supports openSU…
109 …- Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide can …
[all …]
/openbmc/qemu/docs/system/arm/
H A Dmps2.rst6 The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
7 bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
8 FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
10 Since the CPU itself and most of the devices are in the FPGA, the
12 FPGA image.
14 QEMU models the following FPGA images:
16 FPGA images using M-profile CPUs:
35 FPGA images using R-profile CPUs:
65 of the way the real FPGA image usually runs with the second Cortex-R52
H A Demcraft-sf2.rst6 based on the SmartFusion2 SoC FPGA from Microsemi Corporation.
/openbmc/openbmc/meta-amd/meta-ethanolx/recipes-amd/amd-fpga/
H A Damd-fpga.bb2 SUMMARY = "AMD FPGA Register Dump Utility"
3 DESCRIPTION = "AMD FPGA Register Dump Utility"
/openbmc/openbmc/meta-amd/meta-daytonax/recipes-amd/amd-fpga/
H A Damd-fpga.bb2 SUMMARY = "AMD FPGA Register Dump Utility"
3 DESCRIPTION = "AMD FPGA Register Dump Utility"
/openbmc/u-boot/board/imgtec/xilfpga/
H A DREADME10 MIPSfpga is an FPGA based development platform by Imagination Technologies
11 As we are dealing with a MIPS core instantiated on an FPGA, specifications
15 Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
34 The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
/openbmc/u-boot/Documentation/devicetree/bindings/axi/
H A Dgdsys,ihs_axi.txt1 gdsys AXI busses of IHS FPGA devices
9 the FPGA's register space)
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A DKconfig21 bool "FPGA-AST2600"
24 FPGA-AST2600 is Aspeed FPGA board for AST2600 chip.
/openbmc/u-boot/drivers/axi/
H A DKconfig22 Interface (IHS AXI) bus on a gdsys IHS FPGA used to communicate with
23 IP cores in the FPGA (e.g. video transmitter cores).
/openbmc/qemu/docs/system/riscv/
H A Dxiangshan-kunminghu.rst1 BOSC Xiangshan Kunminghu FPGA prototype platform (``xiangshan-kunminghu``)
3 The ``xiangshan-kunminghu`` machine is compatible with our FPGA prototype
/openbmc/openbmc/meta-ibm/meta-system1/recipes-phosphor/power/
H A Dphosphor-power_%.bbappend1 # System1 requires 30s for FPGA poweron
/openbmc/u-boot/board/samtec/vining_fpga/
H A DMAINTAINERS1 VINING FPGA BOARD
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dphysical_context.hpp25 FPGA, enumerator
99 {PhysicalContext::FPGA, "FPGA"},
/openbmc/openbmc/meta-amd/meta-ethanolx/recipes-amd/amd-fpga/files/
H A Dip-to-fpga.service2 Description=Transfer IP address to the FPGA
/openbmc/openbmc/meta-nuvoton/recipes-nuvoton/loadsvf/
H A Dloadsvf_git.bb1 DESCRIPTION = "CPLD/FPGA Programmer"
/openbmc/u-boot/doc/SPI/
H A DREADME.altera_spi5 - Load the bitstream into FPGA, enable bridges
/openbmc/u-boot/board/synopsys/emsdp/
H A DREADME8 The DesignWare ARC EM Software Development Platform is FPGA-bases platform
11 Since this board is based on FPGA it's possible to load and use different
45 - This so-called "ROM" is a part of FPGA image and even though it
/openbmc/u-boot/doc/driver-model/
H A Dfs_firmware_loader.txt14 such as memory, then consumer driver such as FPGA driver can program FPGA image
15 from the target location into FPGA.
/openbmc/u-boot/board/gdsys/mpc8308/
H A DKconfig41 These commands provide FPGA tests.

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