| /openbmc/linux/Documentation/devicetree/bindings/fpga/ |
| H A D | fpga-region.txt | 1 FPGA Region Device Tree Binding
9 - FPGA Region
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
22 This device tree binding document hits some of the high points of FPGA usage and
23 attempts to include terminology used by both major FPGA manufacturers. This
24 document isn't a replacement for any manufacturers specifications for FPGA
32 * The entire FPGA is programmed.
35 * A section of an FPGA is reprogrammed while the rest of the FPGA is not
37 * Not all FPGA's support PR.
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| H A D | altera-socfpga-fpga-mgr.txt | 1 Altera SOCFPGA FPGA Manager
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - interrupts : interrupt for the FPGA Manager device.
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| /openbmc/linux/drivers/fpga/ |
| H A D | Kconfig | 3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
45 FPGA manager driver support for Altera Arria/Cyclone/Stratix
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| /openbmc/u-boot/drivers/fpga/ |
| H A D | Kconfig | 1 menu "FPGA support"
3 config FPGA config
7 bool "Enable Altera FPGA drivers"
8 select FPGA
10 Say Y here to enable the Altera FPGA driver
12 This provides basic infrastructure to support Altera FPGA devices.
13 Enable Altera FPGA specific functions which includes bitstream
17 bool "Enable Gen5 and Arria10 common FPGA drivers"
20 Say Y here to enable the Gen5 and Arria10 common FPGA driver
25 bool "Enable Altera FPGA driver for Cyclone II"
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| /openbmc/linux/Documentation/driver-api/fpga/ |
| H A D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
23 FPGA Manager
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
32 FPGA Bridge
35 FPGA Bridges prevent spurious signals from going out of an FPGA or a
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| H A D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
22 The struct fpga_image_info specifies what FPGA image to program. It is
26 How to program an FPGA using a region
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| H A D | fpga-region.rst | 1 FPGA Region
7 This document is meant to be a brief overview of the FPGA region API usage. A
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
18 to program the FPGA and then DT to handle enumeration. The common region code
24 * which FPGA manager to use to do the programming
28 Additional info needed to program the FPGA image is passed in the struct
37 How to add a new FPGA region
45 API to add a new FPGA region
48 * struct fpga_region - The FPGA region struct
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| H A D | fpga-mgr.rst | 1 FPGA Manager
7 The FPGA manager core exports a set of functions for programming an FPGA with
10 The FPGA image data itself is very manufacturer specific, but for our purposes
11 it's just binary data. The FPGA manager core won't parse it.
13 The FPGA image to be programmed can be in a scatter gather list, a single
20 FPGA image as well as image-specific particulars such as whether the image was
23 How to support a new FPGA device
26 To add another FPGA manager, write a driver that implements a set of ops. The
53 mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
80 do the programming sequence for this particular FPGA. These ops return 0 for
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| H A D | fpga-bridge.rst | 1 FPGA Bridge
4 API to implement a new FPGA bridge
7 * struct fpga_bridge - The FPGA Bridge structure
13 the module that registers the FPGA bridge as the owner.
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-fpga-manager | 13 wrong during FPGA programming (something that the driver can't
18 This is a superset of FPGA states and fpga manager driver
20 to get the FPGA into a known operating state. It's a sequence,
21 though some steps may get skipped. Valid FPGA states will vary
25 * power off = FPGA power is off
26 * power up = FPGA reports power is up
27 * reset = FPGA held in reset state
30 * write init = preparing FPGA for programming
31 * write init error = Error while preparing FPGA for programming
32 * write = FPGA ready to receive image data
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| H A D | sysfs-bus-mcb | 11 Description: The FPGA's revision number
17 Description: The FPGA's minor number
23 Description: The FPGA's model number
29 Description: The FPGA's name
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| /openbmc/u-boot/Documentation/devicetree/bindings/misc/ |
| H A D | gdsys,iocon_fpga.txt | 1 gdsys IHS FPGA for CON devices
3 The gdsys IHS FPGA is the main FPGA on gdsys CON devices. This driver provides
4 support for enabling and starting the FPGA, as well as verifying working bus
9 - reset-gpios: List of GPIOs controlling the FPGA's reset
10 - done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
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| H A D | gdsys,iocpu_fpga.txt | 1 gdsys IHS FPGA for CPU devices
3 The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides
4 support for enabling and starting the FPGA, as well as verifying working bus
9 - reset-gpios: List of GPIOs controlling the FPGA's reset
10 - done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
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| H A D | gdsys,io-endpoint.txt | 1 gdsys IO endpoint of IHS FPGA devices
3 The IO endpoint of IHS FPGA devices is a packet-based transmission interface
5 FPGA's main ethernet connection.
10 the FPGA's register space)
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | ts-nbus.txt | 4 Systems FPGA on the TS-4600 SoM.
10 - pwms : The PWM bound to the FPGA
11 - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA
12 - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA
13 - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA
14 - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA
15 - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA
16 - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 2 Xillybus driver for generic FPGA interface
22 -- Host never reads from the FPGA
37 An FPGA (Field Programmable Gate Array) is a piece of logic hardware, which
48 level, even lower than assembly language. In order to allow FPGA designers to
51 FPGA parallels of library functions. IP cores may implement certain
57 One of the daunting tasks in FPGA design is communicating with a fullblown
60 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's
62 make sense to design the FPGA's interface logic specifically for the project.
63 A special driver is then written to present the FPGA as a well-known interface
65 FPGA differently than any device on the bus.
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| /openbmc/linux/Documentation/fpga/ |
| H A D | dfl.rst | 2 FPGA Device Feature List (DFL) Framework Overview
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
56 FPGA Interface Unit (FIU) represents a standalone functional unit for the
57 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
60 Accelerated Function Unit (AFU) represents an FPGA programmable region and
75 and can be implemented in register regions of any FPGA device.
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| /openbmc/linux/Documentation/devicetree/bindings/board/ |
| H A D | fsl-board.txt | 20 * Freescale on-board FPGA
22 This is the memory-mapped registers for on board FPGA.
26 indicating the type of FPGA. Example:
29 - reg: should contain the address and the length of the FPGA register set.
50 * Freescale on-board FPGA connected on I2C bus
52 Some Freescale boards like BSC9132QDS have on board FPGA connected on
57 indicating the type of FPGA. Example:
59 - reg: Should contain the address of the FPGA
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| /openbmc/linux/drivers/char/xillybus/ |
| H A D | Kconfig | 10 tristate "Xillybus generic FPGA interface"
16 programmable logic (FPGA). The driver probes the hardware for
28 with the FPGA. The module will be called xillybus_pcie.
43 tristate "XillyUSB: Xillybus generic FPGA interface for USB"
49 with the FPGA.
52 the FPGA. The module will be called xillyusb.
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| /openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/ |
| H A D | release-notes.rst | 36 …- Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide can …
42 - This software release is tested on Corstone-1000 FPGA version AN550_v2
66 …- Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide can …
73 - This software release is tested on Corstone-1000 FPGA version AN550_v2
84 …- FPGA supports Linux distro install and boot through installer. However, FVP only supports openSU…
85 …- Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide can …
96 - This software release is tested on Corstone-1000 FPGA version AN550_v2
107 …- The external-system can not be reset individually on (or using) AN550_v1 FPGA release. However, …
108 …- FPGA supports Linux distro install and boot through installer. However, FVP only supports openSU…
109 …- Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide can …
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-ts4900.txt | 1 * Technologic Systems I2C-FPGA's GPIO controller bindings
3 This bindings describes the GPIO controller for Technologic's FPGA core.
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
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| /openbmc/qemu/docs/system/arm/ |
| H A D | mps2.rst | 6 The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
7 bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
8 FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
10 Since the CPU itself and most of the devices are in the FPGA, the
12 FPGA image.
14 QEMU models the following FPGA images:
16 FPGA images using M-profile CPUs:
35 FPGA images using R-profile CPUs:
65 of the way the real FPGA image usually runs with the second Cortex-R52
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| /openbmc/linux/drivers/misc/altera-stapl/ |
| H A D | Kconfig | 2 comment "Altera FPGA firmware download module (requires I2C)"
6 tristate "Altera FPGA firmware download module"
9 An Altera FPGA module. Say Y when you want to support this tool.
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | arm,versatile-fpga-irq.txt | 1 * ARM Versatile FPGA interrupt controller
3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
12 as the FPGA IRQ controller has no configuration options for interrupt
14 - reg: The register bank for the FPGA interrupt controller.
36 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
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| /openbmc/linux/drivers/fpga/tests/ |
| H A D | Kconfig | 2 bool "KUnit test for the FPGA subsystem" if !KUNIT_ALL_TESTS
3 depends on FPGA=y && FPGA_REGION=y && FPGA_BRIDGE=y && KUNIT=y && MODULES=n
6 This builds unit tests for the FPGA subsystem
|