Kconfig - OpenGrok cross reference for /openbmc/linux/drivers/fpga/Kconfig

3 # FPGA framework configuration
6 menuconfig FPGA  config
7 	tristate "FPGA Configuration Framework"
10 	  kernel.  The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 	tristate "Altera SOCFPGA FPGA Manager"
19 	  FPGA manager driver support for Altera SOCFPGA.
26 	  FPGA manager driver support for Altera Arria10 SoCFPGA.
41 	tristate "Altera FPGA Passive Serial over SPI"
45 	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
49 	tristate "Altera CvP FPGA Manager"
52 	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
56 	tristate "Xilinx Zynq FPGA"
59 	  FPGA manager driver support for Xilinx Zynq FPGAs.
62 	tristate "Intel Stratix10 SoC FPGA Manager"
65 	  FPGA manager driver support for the Intel Stratix10 SoC.
71 	  FPGA manager driver support for Xilinx FPGA configuration
78 	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
84 	  FPGA manager driver support for Lattice MachXO2 configuration
88 	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
91 	  FPGA manager driver support for the Altera Cyclone II FPGA
95 	tristate "FPGA Bridge Framework"
101 	tristate "Altera SoCFPGA FPGA Bridges"
104 	  Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
108 	tristate "Altera FPGA Freeze Bridge"
111 	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
112 	  freeze bridge is a bridge that exists in the FPGA fabric to
113 	  isolate one region of the FPGA from the busses while that
123 	  The PR Decoupler exists in the FPGA fabric to isolate one
124 	  region of the FPGA from the busses while that region is
134 	tristate "FPGA Region"
137 	  FPGA Region common code.  An FPGA Region controls an FPGA Manager
138 	  and the FPGA Bridges associated with either a reconfigurable
139 	  region of an FPGA or a whole FPGA.
142 	tristate "FPGA Region Device Tree Overlay Support"
145 	  Support for loading FPGA images by applying a Device Tree
149 	tristate "FPGA Device Feature List (DFL) support"
156 	  to provide an extensible way of adding features for FPGA.
158 	  devices (e.g. FPGA Management Engine, Port and Accelerator
159 	  Function Unit) and their private features for target FPGA devices.
162 	  Gate Array (FPGA) solutions which implement Device Feature List.
166 	tristate "FPGA DFL FME Driver"
169 	  The FPGA Management Engine (FME) is a feature device implemented
172 	  FPGA platform level management features. There shall be one FME
173 	  per DFL based FPGA device.
176 	tristate "FPGA DFL FME Manager Driver"
179 	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
182 	tristate "FPGA DFL FME Bridge Driver"
185 	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
188 	tristate "FPGA DFL FME Region Driver"
191 	  Say Y to enable FPGA Region driver for FPGA Management Engine.
194 	tristate "FPGA DFL AFU Driver"
197 	  This is the driver for FPGA Accelerated Function Unit (AFU) which
199 	  to the FPGA infrastructure via a Port. There may be more than one
200 	  Port/AFU per DFL based FPGA device.
203 	tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
214 	tristate "FPGA DFL PCIe Device Driver"
218 	  Field-Programmable Gate Array (FPGA) solutions which implement
221 	  FPGA accelerators on the FPGA DFL devices, enables system level
222 	  management functions such as FPGA partial reconfiguration, power
229 	tristate "Xilinx ZynqMP FPGA"
232 	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
238 	tristate "Xilinx Versal FPGA"
241 	  Select this option to enable FPGA manager driver support for
258 	  the FPGA image, the Root Entry Hashes, etc.
261 	tristate "Microchip Polarfire SPI FPGA manager"
264 	  FPGA manager driver support for Microchip Polarfire FPGAs
272 	tristate "Lattice sysCONFIG SPI FPGA manager"
276 	  FPGA manager driver support for Lattice FPGAs programming over slave
281 endif # FPGA