Documentation/fpga/dfl.rst

2 FPGA Device Feature List (DFL) Framework Overview
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
56 FPGA Interface Unit (FIU) represents a standalone functional unit for the
57 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more
60 Accelerated Function Unit (AFU) represents an FPGA programmable region and
75 and can be implemented in register regions of any FPGA device.
197 FIU - FME (FPGA Management Engine)
199 The FPGA Management Engine performs reconfiguration and other infrastructure
200 functions. Each FPGA device only has one FME.
219      bitstream_id indicates version of the static FPGA region.
222      bitstream_metadata includes detailed information of static FPGA region,
226      one FPGA device may have more than one port, this sysfs interface indicates
227      how many ports the FPGA device has.
251 A port represents the interface between the static FPGA fabric and a partially
253 to the accelerator and exposes features such as reset and debug. Each FPGA
280   reset the FPGA Port and its AFU. Userspace can do Port
308                  | FPGA Container Device |    Device Feature List
309                  |  (FPGA Base Region)   |         Framework
313                |   FPGA DFL Device Module   |
317                  |  FPGA Hardware Device  |
321 (FPGA base region), discover feature devices and their private features from the
327 The FPGA DFL Device could be different hardware, e.g. PCIe device, platform
334 The FPGA Management Engine (FME) driver is a platform driver which is loaded
336 provides the key features for FPGA management, including:
338 	a) Expose static FPGA region information, e.g. version and metadata.
342 	b) Partial Reconfiguration. The FME driver creates FPGA manager, FPGA
343 	   bridges and FPGA regions during PR sub feature initialization. Once
345 	   common interface function from FPGA Region to complete the partial
348 Similar to the FME driver, the FPGA Accelerated Function Unit (AFU) driver is
364 generated for the exact static FPGA region and targeted reconfigurable region
365 (port) of the FPGA, otherwise, the reconfiguration operation will fail and
368 the compat_id exposed by the target FPGA region. This check is usually done by
372 FPGA virtualization - PCIe SRIOV
374 This section describes the virtualization support on DFL based FPGA device to
376 (VM). This section only describes the PCIe based FPGA device with SRIOV support.
378 Features supported by the particular FPGA device are exposed through Device
399   |            DFL based FPGA PCIe Device             |
414     | FPGA  || FPGA || FPGA |             |
422           | FPGA Container Device |       |       | FPGA Container Device |
423           |  (FPGA Base Region)   |       |       |  (FPGA Base Region)   |
426             | FPGA PCIE Module |          | Virtual | FPGA PCIE Module |
433 FPGA PCIe device driver is always loaded first once an FPGA PCIe PF or VF device
436 * Finishes enumeration on both FPGA PCIe PF and VF device using common
472 In the example below, two DFL based FPGA devices are installed in the host. Each
475 FPGA regions are created under /sys/class/fpga_region/::
484 fpga region which represents the FPGA device.
518 FPGA cache hit/miss rate, transaction number, interface clock counter of AFU
519 and other FPGA performance events.
521 Different FPGA devices may have different counter sets, depending on hardware
522 implementation. E.g., some discrete FPGA cards don't have any cache. User could
533 category; "portid" is introduced to decide counters set to monitor on FPGA
586 since they are system-wide counters on FPGA device.
661 The purpose of an FPGA is to be reprogrammed with newly developed hardware