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Searched refs:DEBUG_INIT_S (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr_ml_wrapper.h27 #define DEBUG_INIT_S(s) puts(s) macro
31 #define DEBUG_INIT_S(s) macro
41 { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
42 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
44 { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
45 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
59 { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.h20 #define DEBUG_INIT_S(s) puts(s) macro
24 #define DEBUG_INIT_S(s) macro
34 { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
35 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
37 { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
38 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
50 { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
H A Dddr3_init.c283 DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset"); in ddr3_init()
285 DEBUG_INIT_S("DDR3 Training Error: Bad DIMM setup"); in ddr3_init()
287 DEBUG_INIT_S("DDR3 Training Error: Max CS limit"); in ddr3_init()
289 DEBUG_INIT_S("DDR3 Training Error: Max enable CS limit"); in ddr3_init()
291 DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup"); in ddr3_init()
293 DEBUG_INIT_S("DDR3 Training Error: TWSI failure"); in ddr3_init()
295 DEBUG_INIT_S("DDR3 Training Error: DIMM type no match"); in ddr3_init()
297 DEBUG_INIT_S("DDR3 Training Error: TWSI bad type"); in ddr3_init()
299 DEBUG_INIT_S("DDR3 Training Error: bus width no match"); in ddr3_init()
371 DEBUG_INIT_S("4\n"); in ddr3_init_main()
[all …]
H A Dddr3_spd.c513 DEBUG_INIT_S("DDR3 Dimm Compare - DIMM type does not match - FAIL\n"); in ddr3_spd_sum_init()
518 DEBUG_INIT_S("DDR3 Dimm Compare - ECC does not match. ECC is disabled\n"); in ddr3_spd_sum_init()
521 DEBUG_INIT_S("DDR3 Dimm Compare - DRAM bus width does not match - FAIL\n"); in ddr3_spd_sum_init()
615 DEBUG_INIT_S("DDR3 Training Sequence - No DIMMs detected\n");
617 DEBUG_INIT_S("DDR3 Training Sequence - FAILED (Wrong DIMMs Setup)\n");
726 DEBUG_INIT_S("DDR3 Training Sequence - FAIL - Illegal R-DIMM setup\n");
1194 DEBUG_INIT_S("DDR3 Training Sequence - Registered DIMM detected\n");
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dctrl_pex.c116 DEBUG_INIT_S("PCIe, Idx "); in hws_pex_config()
118 DEBUG_INIT_S(": detected no link\n"); in hws_pex_config()
145 DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n"); in hws_pex_config()
165 DEBUG_INIT_S("PCIe, Idx "); in hws_pex_config()
167 DEBUG_INIT_S(": remains Gen1\n"); in hws_pex_config()
191 DEBUG_INIT_S("PCIe, Idx "); in hws_pex_config()
193 DEBUG_INIT_S in hws_pex_config()
H A Dhigh_speed_env_spec.c1374 DEBUG_INIT_S(" | "); in print_topology_details()
1376 DEBUG_INIT_S(" | "); in print_topology_details()
1378 DEBUG_INIT_S(" | "); in print_topology_details()
1379 DEBUG_INIT_S((char *) in print_topology_details()
1382 DEBUG_INIT_S("\t|\n"); in print_topology_details()
1419 DEBUG_INIT_S("High speed PHY - Version: "); in serdes_phy_config()
1420 DEBUG_INIT_S(SERDES_VERSION); in serdes_phy_config()
1421 DEBUG_INIT_S("\n"); in serdes_phy_config()
1451 DEBUG_INIT_S(ENDED_OK); in serdes_phy_config()
1516 DEBUG_INIT_S in hws_power_up_serdes_lanes()
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H A Dseq_exec.c119 DEBUG_INIT_S("poll_op_execute: TIMEOUT\n"); in poll_op_execute()
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c286 DEBUG_INIT_S("High speed PHY - Version: "); in serdes_phy_config()
287 DEBUG_INIT_S(SERDES_VERSION); in serdes_phy_config()
288 DEBUG_INIT_S(" - 2nd boot - Skip\n"); in serdes_phy_config()
291 DEBUG_INIT_S("High speed PHY - Version: "); in serdes_phy_config()
292 DEBUG_INIT_S(SERDES_VERSION); in serdes_phy_config()
293 DEBUG_INIT_S(" (COM-PHY-V20)\n"); in serdes_phy_config()
358 DEBUG_INIT_S("Hight speed PHY Error #1\n"); in serdes_phy_config()
1263 DEBUG_INIT_S("PEX"); in serdes_phy_config()
1414 DEBUG_INIT_S(ENDED_OK); in serdes_phy_config()