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Searched refs:DDR3 (Results 1 – 25 of 109) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dclock-k2hk.h38 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
39 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
40 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
41 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
/openbmc/u-boot/board/freescale/mx6memcal/
H A DKconfig88 Select the type of DDR (DDR3 or LPDDR2) used on your design
90 config DDR3 config in mx6memcal specifics""choicec87005010304
91 bool "DDR3"
93 Select this if your board design uses DDR3.
107 depends on DDR3
111 depends on DDR3
115 depends on DDR3
119 depends on DDR3
H A DREADME35 4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
38 parts and four DDR3 and two LPDDR2 parts are currently defined
/openbmc/u-boot/arch/mips/mach-mscc/
H A DKconfig66 bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"
72 bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
75 bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3368-dmc.txt8 (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
19 the DDR3 device's speed-bin (as specified according to JESD-79)
51 Example (for DDR3-1600K and 800MHz)
/openbmc/u-boot/drivers/ddr/fsl/
H A DKconfig93 Enable Freescale DDR3 controller for PowerPC SoCs.
99 Enable Freescale DDR3 controller for ARM SoCs.
131 bool "Freescale DDR3 controller"
/openbmc/u-boot/arch/arm/mach-mediatek/
H A DKconfig18 including NEON and GPU, Mali-450 graphics, several DDR3 options,
31 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml52 DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
53 datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
130 When the DRAM type is DDR3, this parameter defines the ODT disable
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
/openbmc/u-boot/board/toradex/colibri_imx6/
H A D800mhz_2x64mx16.cfg17 /* DDR3 DATA BUS SIZE: 64BIT */
19 /* DDR3 DATA BUS SIZE: 32BIT */
H A D800mhz_4x64mx16.cfg17 /* DDR3 DATA BUS SIZE: 64BIT */
19 /* DDR3 DATA BUS SIZE: 32BIT */
/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig12 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
71 video interfaces supporting HDMI and eDP, several DDR3 options
91 video interfaces supporting HDMI and eDP, several DDR3 options
111 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
145 video interfaces supporting HDMI and eDP, several DDR3 options
/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp15-ddr3-2x4Gb-1066-binG.dtsi10 * DDR type / Platform DDR3/3L
13 * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
20 #define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
/openbmc/u-boot/arch/arm/mach-sunxi/
H A DKconfig372 bool "DDR3 1333"
402 Set the dram type, 3: DDR3, 7: LPDDR3
416 (for DDR3-1600) are 312 to 792.
486 Select the timings of the DDR3 chips.
494 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
496 Use the timings of the standard JEDEC DDR3-1066F speed bin for
498 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
501 that down binning to DDR3-1066F is supported (because DDR3-1066F
502 uses a bit faster timings than DDR3-1333H).
505 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
[all …]
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32mp1-ddr.txt1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
175 st,mem-name = "DDR3 2x4Gb 533MHz";
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dprocessor.hpp45 DDR3, enumerator
131 {ProcessorMemoryType::DDR3, "DDR3"},
H A Dmemory.hpp22 DDR3, enumerator
125 {MemoryDeviceType::DDR3, "DDR3"},
/openbmc/u-boot/board/seco/mx6quq7/
H A Dmx6quq7-2g.cfg76 * DDR3 SETTINGS
115 * in DDR3, 64-bit mode, only MMDC0 is init
135 /* Initialize DDR3 on CS_0 and CS_1 */
/openbmc/u-boot/arch/arm/mach-mvebu/
H A Dkwbimage.cfg.in11 # Binary Header (bin_hdr) with DDR3 training code
/openbmc/u-boot/board/alliedtelesis/x530/
H A Dkwbimage.cfg11 # Binary Header (bin_hdr) with DDR3 training code
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A DREADME13 They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
17 * DDR3
/openbmc/u-boot/drivers/ram/stm32mp1/
H A DKconfig10 family: support for LPDDR2, LPDDR3 and DDR3
/openbmc/u-boot/arch/arm/mach-rockchip/rk3399/
H A DKconfig27 * on-module DDR3 (1GB, 2GB and 4GB configurations available)
50 * 2GiB/4GiB DDR3 RAM
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dti-keystone-pllctrl.txt4 and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
/openbmc/u-boot/arch/arm/mach-imx/
H A DKconfig83 bool "Enable DDRMC (DDR3) on-chip calibration"
86 Vybrid (vf610) SoC provides some on-chip facility to tune the DDR3
/openbmc/u-boot/arch/arm/mach-rockchip/rv1108/
H A DKconfig13 * 128M DDR3

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