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Searched refs:CONFIG_SYS_I2C_RTC_ADDR (Results 1 – 25 of 59) sorted by relevance

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/openbmc/u-boot/drivers/rtc/
H A Dm41t11.c77 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); in rtc_get()
95 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, &cent, M41T11_YEAR_SIZE); in rtc_get()
103 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, &cent, M41T11_YEAR_SIZE); in rtc_get()
148 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, &cent, M41T11_YEAR_SIZE); in rtc_set()
151 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); in rtc_set()
160 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, 1); in rtc_reset()
162 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, RTC_REG_CNT); in rtc_reset()
164 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); in rtc_reset()
166 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); in rtc_reset()
H A Dds1374.c32 #ifndef CONFIG_SYS_I2C_RTC_ADDR
33 # define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
197 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
203 val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg); in rtc_write()
204 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
206 val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val; in rtc_write()
207 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
213 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write_raw()
H A Drs5c372.c42 #ifndef CONFIG_SYS_I2C_RTC_ADDR
43 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 macro
66 ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); in rs5c372_readram()
106 ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); in rs5c372_enable()
207 ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); in rtc_set()
236 ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); in rtc_set()
H A Dm41t60.c62 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { in rtc_dump()
91 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { in rtc_validate()
102 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) { in rtc_validate()
138 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { in rtc_validate()
189 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) { in rtc_set()
232 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) { in rtc_reset()
H A Dmax6900.c18 #ifndef CONFIG_SYS_I2C_RTC_ADDR
19 #define CONFIG_SYS_I2C_RTC_ADDR 0x50 macro
26 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
31 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
H A Drx8025.c26 #ifndef CONFIG_SYS_I2C_RTC_ADDR
27 # define CONFIG_SYS_I2C_RTC_ADDR 0x32 macro
84 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16)) in rtc_get()
170 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16)) in rtc_reset()
187 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 2) != 0) in rtc_write()
H A Dm41t62.c182 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); in rtc_get()
192 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); in rtc_set()
195 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, in rtc_set()
212 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); in rtc_reset()
214 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); in rtc_reset()
H A Drx8010sj.c35 #ifndef CONFIG_SYS_I2C_RTC_ADDR
36 # define CONFIG_SYS_I2C_RTC_ADDR 0x32 macro
315 .chip = CONFIG_SYS_I2C_RTC_ADDR, in rtc_get()
324 .chip = CONFIG_SYS_I2C_RTC_ADDR, in rtc_set()
333 .chip = CONFIG_SYS_I2C_RTC_ADDR, in rtc_reset()
342 .chip = CONFIG_SYS_I2C_RTC_ADDR, in rtc_init()
H A Dds1307.c64 #ifndef CONFIG_SYS_I2C_RTC_ADDR
65 # define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
196 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
202 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
H A Dpcf8563.c111 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
116 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
H A Dpt7c4338.c52 return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg); in rtc_read()
57 i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
H A Dx1205.c79 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); in rtc_write()
91 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); in rtc_get()
H A Dds3231.c159 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
165 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
H A Dds1337.c183 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); in rtc_read()
189 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); in rtc_write()
/openbmc/u-boot/drivers/bootcount/
H A Dbootcount_i2c.c20 ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, in bootcount_store()
31 ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, in bootcount_load()
/openbmc/u-boot/board/freescale/mpc8349itx/
H A Dmpc8349itx.c257 #ifdef CONFIG_SYS_I2C_RTC_ADDR in misc_init_r()
311 #ifdef CONFIG_SYS_I2C_RTC_ADDR in misc_init_r()
314 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) in misc_init_r()
358 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, in misc_init_r()
/openbmc/u-boot/include/configs/
H A Dtqma6_wru4.h25 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
H A Dxpedite520x.h63 CONFIG_SYS_I2C_RTC_ADDR}
188 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
H A Dxpedite550x.h80 CONFIG_SYS_I2C_RTC_ADDR}
221 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
H A Daristainetos-common.h177 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
H A Dpcm052.h61 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
H A Dls1012aqds.h57 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ macro
H A Dls2080ardb.h305 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 macro
308 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
H A Dmcx.h76 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 macro
H A Dmx53ppd.h54 #define CONFIG_SYS_I2C_RTC_ADDR 0x30 macro

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