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Searched refs:CONFIG_SYS_DDR_BASE (Results 1 – 25 of 29) sorted by relevance

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/openbmc/u-boot/include/configs/km/
H A Dkm83xx-common.h37 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
38 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
41 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
/openbmc/u-boot/include/configs/
H A Dmpc8308_p1m.h119 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
120 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
121 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DTQM834x.h47 #define CONFIG_SYS_DDR_BASE 0x00000000 macro
48 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
49 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DMPC8308RDB.h116 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
118 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DMPC8323ERDB.h73 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
75 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A Dids8313.h95 #define CONFIG_SYS_DDR_BASE 0x00000000 macro
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
97 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A Dve8313.h48 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ macro
49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
50 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DMPC832XEMDS.h80 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
82 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A Dvme8349.h83 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ macro
84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
85 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DMPC8315ERDB.h92 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
94 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A Dsbc8349.h75 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ macro
76 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
77 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A Dhrcon.h106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
108 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DMPC8313ERDB.h110 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ macro
111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
112 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DMPC837XERDB.h129 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
130 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
131 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DMPC8349ITX.h157 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ macro
158 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
159 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DMPC837XEMDS.h107 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
109 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A Dstrider.h106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ macro
107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
108 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
H A DMPC8349EMDS.h80 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ macro
81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
82 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
/openbmc/u-boot/board/tqc/tqm834x/
H A Dtqm834x.c75 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; in dram_init()
81 CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), in dram_init()
105 (long *)(CONFIG_SYS_DDR_BASE + size)); in dram_init()
/openbmc/u-boot/board/keymile/km83xx/
H A Dkm83xx.c314 msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); in fixed_sdram()
341 CONFIG_SYS_DDR_BASE & LAWBAR_BAR); in dram_init()
/openbmc/u-boot/board/freescale/mpc832xemds/
H A Dmpc832xemds.c101 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; in dram_init()
/openbmc/u-boot/board/esd/vme8349/
H A Dvme8349.c41 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; in dram_init()
/openbmc/u-boot/board/sbc8349/
H A Dsbc8349.c48 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; in dram_init()
/openbmc/u-boot/board/freescale/mpc8323erdb/
H A Dmpc8323erdb.c83 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; in dram_init()
/openbmc/u-boot/board/ve8313/
H A Dve8313.c83 msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); in fixed_sdram()

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