Searched refs:CLK_TOP_MSDC30_0_SEL (Results 1 – 16 of 16) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt8135-clk.h | 97 #define CLK_TOP_MSDC30_0_SEL 86 macro
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| H A D | mt7629-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 85 macro
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| H A D | mt7622-clk.h | 80 #define CLK_TOP_MSDC30_0_SEL 68 macro
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| H A D | mt2701-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 84 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 99 #define CLK_TOP_MSDC30_0_SEL 85 macro
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| H A D | mt7623-clk.h | 112 #define CLK_TOP_MSDC30_0_SEL 98 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt8135.c | 388 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
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| H A D | clk-mt7622.c | 416 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
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| H A D | clk-mt7629.c | 489 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
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| H A D | clk-mt2701.c | 511 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 523 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
660 GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
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| H A D | clk-mt7629.c | 382 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | mt7623.dtsi | 236 <&topckgen CLK_TOP_MSDC30_0_SEL>;
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7622-rfb1.dts | 200 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
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| H A D | mt7622-bananapi-bpi-r64.dts | 231 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
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| /openbmc/linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7623.dtsi | 721 <&topckgen CLK_TOP_MSDC30_0_SEL>;
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