/openbmc/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7623.c | 84 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ), 147 FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2), 148 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4), 149 FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1), 199 CLK_TOP_DMPLL 215 CLK_TOP_DMPLL 403 CLK_TOP_DMPLL 444 CLK_TOP_DMPLL,
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H A D | clk-mt7629.c | 97 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), 159 CLK_TOP_DMPLL 164 CLK_TOP_DMPLL 180 CLK_TOP_DMPLL
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 31 #define CLK_TOP_DMPLL 21 macro
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H A D | mt8516-clk.h | 35 #define CLK_TOP_DMPLL 3 macro
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H A D | mt7622-clk.h | 29 #define CLK_TOP_DMPLL 17 macro
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H A D | mediatek,mt6795-clk.h | 38 #define CLK_TOP_DMPLL 27 macro
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H A D | mt6765-clk.h | 86 #define CLK_TOP_DMPLL 51 macro
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H A D | mt8173-clk.h | 37 #define CLK_TOP_DMPLL 27 macro
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H A D | mt2712-clk.h | 121 #define CLK_TOP_DMPLL 90 macro
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H A D | mt2701-clk.h | 53 #define CLK_TOP_DMPLL 43 macro
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/openbmc/u-boot/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 34 #define CLK_TOP_DMPLL 21 macro
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H A D | mt7623-clk.h | 13 #define CLK_TOP_DMPLL 1 macro
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt6795-topckgen.c | 389 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
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H A D | clk-mt8173-topckgen.c | 464 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
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H A D | clk-mt7622.c | 271 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
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H A D | clk-mt8516.c | 30 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
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H A D | clk-mt8167.c | 33 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
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H A D | clk-mt7629.c | 374 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
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H A D | clk-mt2712.c | 25 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
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H A D | clk-mt6765.c | 79 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 466000000),
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H A D | clk-mt2701.c | 30 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
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/openbmc/u-boot/arch/arm/dts/ |
H A D | mt7629.dtsi | 125 <&topckgen CLK_TOP_DMPLL>;
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