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Searched refs:CLK_TOP_APLL12_CK_DIV0 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt8516-clk.h196 #define CLK_TOP_APLL12_CK_DIV0 164 macro
H A Dmediatek,mt8365-clk.h122 #define CLK_TOP_APLL12_CK_DIV0 112 macro
H A Dmt8186-clk.h150 #define CLK_TOP_APLL12_CK_DIV0 131 macro
H A Dmediatek,mt8188-clk.h190 #define CLK_TOP_APLL12_CK_DIV0 179 macro
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmt8186-afe-pcm.yaml141 <&topckgen 131>, //CLK_TOP_APLL12_CK_DIV0
H A Dmediatek,mt8188-afe.yaml196 <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8186-topckgen.c672 DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "apll_i2s0_mck_sel",
H A Dclk-mt8516.c479 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
H A Dclk-mt8167.c668 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
H A Dclk-mt8188-topckgen.c1181 DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "top_i2si1", 0x0320, 0, 0x0328, 8, 0),
H A Dclk-mt8365.c553 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel",
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186.dtsi1491 <&topckgen CLK_TOP_APLL12_CK_DIV0>,