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Searched refs:reg_offset (Results 26 – 50 of 393) sorted by relevance

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/openbmc/u-boot/drivers/power/pmic/
H A Dpmic_tps65910.c82 unsigned int reg_offset; in tps65910_voltage_update() local
86 reg_offset = TPS65910_VDD1_OP_REG; in tps65910_voltage_update()
88 reg_offset = TPS65910_VDD2_OP_REG; in tps65910_voltage_update()
91 ret = tps65910_read_reg(reg_offset, &buf); in tps65910_voltage_update()
97 ret = tps65910_write_reg(reg_offset, &buf); in tps65910_voltage_update()
102 ret = tps65910_read_reg(reg_offset, &buf); in tps65910_voltage_update()
109 ret = tps65910_write_reg(reg_offset, &buf); in tps65910_voltage_update()
113 ret = tps65910_read_reg(reg_offset, &buf); in tps65910_voltage_update()
/openbmc/linux/drivers/gpio/
H A Dgpio-madera.c28 unsigned int reg_offset = 2 * offset; in madera_gpio_get_direction() local
32 ret = regmap_read(madera->regmap, MADERA_GPIO1_CTRL_2 + reg_offset, in madera_gpio_get_direction()
47 unsigned int reg_offset = 2 * offset; in madera_gpio_direction_in() local
50 MADERA_GPIO1_CTRL_2 + reg_offset, in madera_gpio_direction_in()
58 unsigned int reg_offset = 2 * offset; in madera_gpio_get() local
75 unsigned int reg_offset = 2 * offset; in madera_gpio_direction_out() local
80 MADERA_GPIO1_CTRL_2 + reg_offset, in madera_gpio_direction_out()
86 MADERA_GPIO1_CTRL_1 + reg_offset, in madera_gpio_direction_out()
95 unsigned int reg_offset = 2 * offset; in madera_gpio_set() local
100 MADERA_GPIO1_CTRL_1 + reg_offset, in madera_gpio_set()
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c85 unsigned int reg_offset; member
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
112 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
165 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
188 rk_phy->reg_offset + GRF_EMMCPHY_CON0, in rockchip_emmc_phy_power()
194 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
289 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power_on()
296 rk_phy->reg_offset + GRF_EMMCPHY_CON0, in rockchip_emmc_phy_power_on()
303 rk_phy->reg_offset + GRF_EMMCPHY_CON0, in rockchip_emmc_phy_power_on()
354 unsigned int reg_offset; in rockchip_emmc_phy_probe() local
[all …]
/openbmc/linux/drivers/mfd/
H A Dda9150-core.c258 .reg_offset = 0,
262 .reg_offset = 0,
266 .reg_offset = 0,
270 .reg_offset = 0,
274 .reg_offset = 0,
278 .reg_offset = 1,
282 .reg_offset = 1,
286 .reg_offset = 1,
290 .reg_offset = 1,
294 .reg_offset = 1,
[all …]
H A Dmax77693.c113 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, },
114 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, },
116 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, },
118 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, },
120 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, },
121 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, },
122 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, },
123 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, },
125 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_EOC, },
126 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CGMBC, },
[all …]
H A Dda9062-core.c31 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
35 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
39 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
44 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
48 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
52 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
56 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
61 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
65 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
69 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
[all …]
H A Dtps65090.c90 .reg_offset = 1,
94 .reg_offset = 1,
98 .reg_offset = 1,
102 .reg_offset = 1,
106 .reg_offset = 1,
110 .reg_offset = 1,
114 .reg_offset = 1,
118 .reg_offset = 1,
H A Dhi655x-pmic.c24 { .reg_offset = 0, .mask = OTMP_D1R_INT_MASK },
25 { .reg_offset = 0, .mask = VSYS_2P5_R_INT_MASK },
26 { .reg_offset = 0, .mask = VSYS_UV_D3R_INT_MASK },
27 { .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT_MASK },
28 { .reg_offset = 0, .mask = PWRON_D4SR_INT_MASK },
29 { .reg_offset = 0, .mask = PWRON_D20F_INT_MASK },
30 { .reg_offset = 0, .mask = PWRON_D20R_INT_MASK },
31 { .reg_offset = 0, .mask = RESERVE_INT_MASK },
H A Dmax77686.c116 { .reg_offset = 0, .mask = MAX77686_INT1_PWRONF_MSK, },
117 { .reg_offset = 0, .mask = MAX77686_INT1_PWRONR_MSK, },
118 { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBF_MSK, },
119 { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBR_MSK, },
120 { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBF_MSK, },
121 { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBR_MSK, },
122 { .reg_offset = 0, .mask = MAX77686_INT1_ONKEY1S_MSK, },
123 { .reg_offset = 0, .mask = MAX77686_INT1_MRSTB_MSK, },
125 { .reg_offset = 1, .mask = MAX77686_INT2_140C_MSK, },
126 { .reg_offset = 1, .mask = MAX77686_INT2_120C_MSK, },
H A D88pm800.c179 .reg_offset = 1,
183 .reg_offset = 1,
187 .reg_offset = 1,
191 .reg_offset = 1,
196 .reg_offset = 2,
200 .reg_offset = 2,
204 .reg_offset = 2,
208 .reg_offset = 2,
212 .reg_offset = 2,
217 .reg_offset = 3,
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dintel_gmbus.c254 int i, reg_offset; in gmbus_xfer() local
260 reg_offset = 0; in gmbus_xfer()
269 GMBUS_REG_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
275 GMBUS_REG_READ(GMBUS2+reg_offset); in gmbus_xfer()
299 GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer()
300 GMBUS_REG_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
305 GMBUS_REG_READ(GMBUS2+reg_offset); in gmbus_xfer()
321 GMBUS_REG_READ(GMBUS2+reg_offset); in gmbus_xfer()
339 GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0); in gmbus_xfer()
345 GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0); in gmbus_xfer()
[all …]
/openbmc/linux/drivers/extcon/
H A Dextcon-sm5502.c208 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_ATTACH_MASK, },
209 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_DETACH_MASK, },
210 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_KP_MASK, },
211 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKP_MASK, },
212 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKR_MASK, },
223 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_MHL_MASK, },
256 { .reg_offset = 0, .mask = SM5504_IRQ_INT1_ATTACH_MASK, },
257 { .reg_offset = 0, .mask = SM5504_IRQ_INT1_DETACH_MASK, },
260 { .reg_offset = 0, .mask = SM5504_IRQ_INT1_OVP_MASK, },
266 { .reg_offset = 1, .mask = SM5504_IRQ_INT2_UVLO_MASK, },
[all …]
/openbmc/linux/sound/soc/sof/amd/
H A Dacp-stream.c41 stream->reg_offset = PTE_GRP1_OFFSET; in acp_dsp_stream_config()
47 stream->reg_offset = PTE_GRP2_OFFSET; in acp_dsp_stream_config()
53 stream->reg_offset = PTE_GRP3_OFFSET; in acp_dsp_stream_config()
59 stream->reg_offset = PTE_GRP4_OFFSET; in acp_dsp_stream_config()
65 stream->reg_offset = PTE_GRP5_OFFSET; in acp_dsp_stream_config()
71 stream->reg_offset = PTE_GRP6_OFFSET; in acp_dsp_stream_config()
77 stream->reg_offset = PTE_GRP7_OFFSET; in acp_dsp_stream_config()
83 stream->reg_offset = PTE_GRP8_OFFSET; in acp_dsp_stream_config()
93 offsetof(struct scratch_reg_conf, reg_offset); in acp_dsp_stream_config()
98 phy_addr_offset, stream->reg_offset); in acp_dsp_stream_config()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c251 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
260 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()
262 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()
305 uint32_t reg_offset, value; in cik_sdma_ctx_switch_enable() local
310 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
312 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
332 u32 me_cntl, reg_offset; in cik_sdma_enable() local
342 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_enable()
344 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_enable()
369 u32 reg_offset, wb_offset; in cik_sdma_gfx_resume() local
[all …]
H A Dni_dma.c191 u32 reg_offset, wb_offset; in cayman_dma_resume() local
197 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
201 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
214 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
217 WREG32(DMA_RB_RPTR + reg_offset, 0); in cayman_dma_resume()
218 WREG32(DMA_RB_WPTR + reg_offset, 0); in cayman_dma_resume()
221 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, in cayman_dma_resume()
223 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, in cayman_dma_resume()
236 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); in cayman_dma_resume()
238 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmmsch_v2_0.h245 uint32_t reg_offset : 28; member
250 uint32_t reg_offset : 20; member
283 uint32_t reg_offset, in mmsch_v2_0_insert_direct_wt() argument
286 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v2_0_insert_direct_wt()
293 uint32_t reg_offset, in mmsch_v2_0_insert_direct_rd_mod_wt() argument
296 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v2_0_insert_direct_rd_mod_wt()
305 uint32_t reg_offset, in mmsch_v2_0_insert_direct_poll() argument
308 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v2_0_insert_direct_poll()
H A Dsoc15.h56 uint32_t reg_offset; member
63 uint32_t reg_offset; member
73 uint32_t reg_offset; member
82 uint32_t reg_offset; member
91 …define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.…
H A Dmmsch_v4_0.h70 uint32_t reg_offset : 28; member
75 uint32_t reg_offset : 20; member
109 direct_rd_mod_wt.cmd_header.reg_offset = reg; \
120 direct_wt.cmd_header.reg_offset = reg; \
130 direct_poll.cmd_header.reg_offset = reg; \
/openbmc/linux/drivers/gpu/drm/loongson/
H A Dloongson_device.c43 .reg_offset = LS7A1000_PLL_GFX_REG,
48 .reg_offset = LS7A1000_PIXPLL0_REG,
52 .reg_offset = LS7A1000_PIXPLL1_REG,
75 .reg_offset = LS7A2000_PLL_GFX_REG,
80 .reg_offset = LS7A2000_PIXPLL0_REG,
84 .reg_offset = LS7A2000_PIXPLL1_REG,
/openbmc/linux/drivers/pwm/
H A Dpwm-mediatek.c40 const unsigned int *reg_offset; member
292 .reg_offset = mtk_pwm_reg_offset_v1,
299 .reg_offset = mtk_pwm_reg_offset_v1,
306 .reg_offset = mtk_pwm_reg_offset_v1,
313 .reg_offset = mtk_pwm_reg_offset_v1,
320 .reg_offset = mtk_pwm_reg_offset_v1,
327 .reg_offset = mtk_pwm_reg_offset_v1,
334 .reg_offset = mtk_pwm_reg_offset_v2,
341 .reg_offset = mtk_pwm_reg_offset_v1,
348 .reg_offset = mtk_pwm_reg_offset_v1,
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dns16550.c60 u32 reg_offset; in ns16550_console_init() local
67 n = getprop(devp, "reg-offset", &reg_offset, sizeof(reg_offset)); in ns16550_console_init()
68 if (n == sizeof(reg_offset)) in ns16550_console_init()
69 reg_base += be32_to_cpu(reg_offset); in ns16550_console_init()
/openbmc/linux/drivers/comedi/drivers/
H A Dcomedi_8254.c131 val = readb(i8254->mmio + reg_offset); in __i8254_read()
133 val = inb(i8254->iobase + reg_offset); in __i8254_read()
137 val = readw(i8254->mmio + reg_offset); in __i8254_read()
139 val = inw(i8254->iobase + reg_offset); in __i8254_read()
143 val = readl(i8254->mmio + reg_offset); in __i8254_read()
145 val = inl(i8254->iobase + reg_offset); in __i8254_read()
160 writeb(val, i8254->mmio + reg_offset); in __i8254_write()
162 outb(val, i8254->iobase + reg_offset); in __i8254_write()
166 writew(val, i8254->mmio + reg_offset); in __i8254_write()
168 outw(val, i8254->iobase + reg_offset); in __i8254_write()
[all …]
/openbmc/linux/drivers/net/ethernet/natsemi/
H A Dmacsonic.c299 lp->reg_offset = 0; in mac_onboard_sonic_probe()
307 lp->reg_offset = 2; in mac_onboard_sonic_probe()
316 lp->reg_offset = 0; in mac_onboard_sonic_probe()
320 lp->reg_offset = 2; in mac_onboard_sonic_probe()
326 lp->reg_offset); in mac_onboard_sonic_probe()
415 reg_offset = 2; in mac_sonic_nubus_probe_board()
422 reg_offset = 0; in mac_sonic_nubus_probe_board()
430 reg_offset = 0; in mac_sonic_nubus_probe_board()
438 reg_offset = 0; in mac_sonic_nubus_probe_board()
446 reg_offset = 0; in mac_sonic_nubus_probe_board()
[all …]
/openbmc/linux/arch/x86/kernel/
H A Duprobes.c769 u8 opc1 = OPCODE1(insn), reg_offset = 0; in push_setup_xol_ops() local
785 reg_offset = offsetof(struct pt_regs, r8); in push_setup_xol_ops()
788 reg_offset = offsetof(struct pt_regs, r9); in push_setup_xol_ops()
815 reg_offset = offsetof(struct pt_regs, ax); in push_setup_xol_ops()
818 reg_offset = offsetof(struct pt_regs, cx); in push_setup_xol_ops()
821 reg_offset = offsetof(struct pt_regs, dx); in push_setup_xol_ops()
824 reg_offset = offsetof(struct pt_regs, bx); in push_setup_xol_ops()
827 reg_offset = offsetof(struct pt_regs, sp); in push_setup_xol_ops()
830 reg_offset = offsetof(struct pt_regs, bp); in push_setup_xol_ops()
833 reg_offset = offsetof(struct pt_regs, si); in push_setup_xol_ops()
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_liodn.h14 unsigned long reg_offset[2]; member
20 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
26 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
28 .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
34 .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
44 unsigned long reg_offset; member
56 unsigned long reg_offset; member
73 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
80 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
87 .reg_offset = off + CONFIG_SYS_CCSRBAR, \

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