163127922SJane Jian /* 263127922SJane Jian * Copyright 2022 Advanced Micro Devices, Inc. 363127922SJane Jian * 463127922SJane Jian * Permission is hereby granted, free of charge, to any person obtaining a 563127922SJane Jian * copy of this software and associated documentation files (the "Software"), 663127922SJane Jian * to deal in the Software without restriction, including without limitation 763127922SJane Jian * the rights to use, copy, modify, merge, publish, distribute, sublicense, 863127922SJane Jian * and/or sell copies of the Software, and to permit persons to whom the 963127922SJane Jian * Software is furnished to do so, subject to the following conditions: 1063127922SJane Jian * 1163127922SJane Jian * The above copyright notice and this permission notice shall be included in 1263127922SJane Jian * all copies or substantial portions of the Software. 1363127922SJane Jian * 1463127922SJane Jian * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1563127922SJane Jian * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1663127922SJane Jian * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1763127922SJane Jian * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1863127922SJane Jian * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1963127922SJane Jian * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2063127922SJane Jian * OTHER DEALINGS IN THE SOFTWARE. 2163127922SJane Jian * 2263127922SJane Jian */ 2363127922SJane Jian 2463127922SJane Jian #ifndef __MMSCH_V4_0_H__ 2563127922SJane Jian #define __MMSCH_V4_0_H__ 2663127922SJane Jian 2763127922SJane Jian #include "amdgpu_vcn.h" 2863127922SJane Jian 2963127922SJane Jian #define MMSCH_VERSION_MAJOR 4 3063127922SJane Jian #define MMSCH_VERSION_MINOR 0 3163127922SJane Jian #define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR) 3263127922SJane Jian 3363127922SJane Jian #define RB_ENABLED (1 << 0) 3463127922SJane Jian #define RB4_ENABLED (1 << 1) 3563127922SJane Jian 3663127922SJane Jian #define MMSCH_VF_ENGINE_STATUS__PASS 0x1 3763127922SJane Jian 3863127922SJane Jian #define MMSCH_VF_MAILBOX_RESP__OK 0x1 3963127922SJane Jian #define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2 4063127922SJane Jian 41bf35dbc1SJane Jian #define MMSCH_VF_ENGINE_STATUS__PASS 0x1 42bf35dbc1SJane Jian 43bf35dbc1SJane Jian #define MMSCH_VF_MAILBOX_RESP__OK 0x1 44bf35dbc1SJane Jian #define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2 45bf35dbc1SJane Jian 46*f2bcc0c7SEmily Deng #define MMSCH_V4_0_VCN_INSTANCES 0x2 47*f2bcc0c7SEmily Deng 4863127922SJane Jian enum mmsch_v4_0_command_type { 4963127922SJane Jian MMSCH_COMMAND__DIRECT_REG_WRITE = 0, 5063127922SJane Jian MMSCH_COMMAND__DIRECT_REG_POLLING = 2, 5163127922SJane Jian MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3, 5263127922SJane Jian MMSCH_COMMAND__INDIRECT_REG_WRITE = 8, 5363127922SJane Jian MMSCH_COMMAND__END = 0xf 5463127922SJane Jian }; 5563127922SJane Jian 5663127922SJane Jian struct mmsch_v4_0_table_info { 5763127922SJane Jian uint32_t init_status; 5863127922SJane Jian uint32_t table_offset; 5963127922SJane Jian uint32_t table_size; 6063127922SJane Jian }; 6163127922SJane Jian 6263127922SJane Jian struct mmsch_v4_0_init_header { 6363127922SJane Jian uint32_t version; 6463127922SJane Jian uint32_t total_size; 65*f2bcc0c7SEmily Deng struct mmsch_v4_0_table_info inst[MMSCH_V4_0_VCN_INSTANCES]; 6663127922SJane Jian struct mmsch_v4_0_table_info jpegdec; 6763127922SJane Jian }; 6863127922SJane Jian 6963127922SJane Jian struct mmsch_v4_0_cmd_direct_reg_header { 7063127922SJane Jian uint32_t reg_offset : 28; 7163127922SJane Jian uint32_t command_type : 4; 7263127922SJane Jian }; 7363127922SJane Jian 7463127922SJane Jian struct mmsch_v4_0_cmd_indirect_reg_header { 7563127922SJane Jian uint32_t reg_offset : 20; 7663127922SJane Jian uint32_t reg_idx_space : 8; 7763127922SJane Jian uint32_t command_type : 4; 7863127922SJane Jian }; 7963127922SJane Jian 8063127922SJane Jian struct mmsch_v4_0_cmd_direct_write { 8163127922SJane Jian struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 8263127922SJane Jian uint32_t reg_value; 8363127922SJane Jian }; 8463127922SJane Jian 8563127922SJane Jian struct mmsch_v4_0_cmd_direct_read_modify_write { 8663127922SJane Jian struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 8763127922SJane Jian uint32_t write_data; 8863127922SJane Jian uint32_t mask_value; 8963127922SJane Jian }; 9063127922SJane Jian 9163127922SJane Jian struct mmsch_v4_0_cmd_direct_polling { 9263127922SJane Jian struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 9363127922SJane Jian uint32_t mask_value; 9463127922SJane Jian uint32_t wait_value; 9563127922SJane Jian }; 9663127922SJane Jian 9763127922SJane Jian struct mmsch_v4_0_cmd_end { 9863127922SJane Jian struct mmsch_v4_0_cmd_direct_reg_header cmd_header; 9963127922SJane Jian }; 10063127922SJane Jian 10163127922SJane Jian struct mmsch_v4_0_cmd_indirect_write { 10263127922SJane Jian struct mmsch_v4_0_cmd_indirect_reg_header cmd_header; 10363127922SJane Jian uint32_t reg_value; 10463127922SJane Jian }; 10563127922SJane Jian 10663127922SJane Jian #define MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ 10763127922SJane Jian size = sizeof(struct mmsch_v4_0_cmd_direct_read_modify_write); \ 10863127922SJane Jian size_dw = size / 4; \ 10963127922SJane Jian direct_rd_mod_wt.cmd_header.reg_offset = reg; \ 11063127922SJane Jian direct_rd_mod_wt.mask_value = mask; \ 11163127922SJane Jian direct_rd_mod_wt.write_data = data; \ 11263127922SJane Jian memcpy((void *)table_loc, &direct_rd_mod_wt, size); \ 11363127922SJane Jian table_loc += size_dw; \ 11463127922SJane Jian table_size += size_dw; \ 11563127922SJane Jian } 11663127922SJane Jian 11763127922SJane Jian #define MMSCH_V4_0_INSERT_DIRECT_WT(reg, value) { \ 11863127922SJane Jian size = sizeof(struct mmsch_v4_0_cmd_direct_write); \ 11963127922SJane Jian size_dw = size / 4; \ 12063127922SJane Jian direct_wt.cmd_header.reg_offset = reg; \ 12163127922SJane Jian direct_wt.reg_value = value; \ 12263127922SJane Jian memcpy((void *)table_loc, &direct_wt, size); \ 12363127922SJane Jian table_loc += size_dw; \ 12463127922SJane Jian table_size += size_dw; \ 12563127922SJane Jian } 12663127922SJane Jian 12763127922SJane Jian #define MMSCH_V4_0_INSERT_DIRECT_POLL(reg, mask, wait) { \ 12863127922SJane Jian size = sizeof(struct mmsch_v4_0_cmd_direct_polling); \ 12963127922SJane Jian size_dw = size / 4; \ 13063127922SJane Jian direct_poll.cmd_header.reg_offset = reg; \ 13163127922SJane Jian direct_poll.mask_value = mask; \ 13263127922SJane Jian direct_poll.wait_value = wait; \ 13363127922SJane Jian memcpy((void *)table_loc, &direct_poll, size); \ 13463127922SJane Jian table_loc += size_dw; \ 13563127922SJane Jian table_size += size_dw; \ 13663127922SJane Jian } 13763127922SJane Jian 13863127922SJane Jian #define MMSCH_V4_0_INSERT_END() { \ 13963127922SJane Jian size = sizeof(struct mmsch_v4_0_cmd_end); \ 14063127922SJane Jian size_dw = size / 4; \ 14163127922SJane Jian memcpy((void *)table_loc, &end, size); \ 14263127922SJane Jian table_loc += size_dw; \ 14363127922SJane Jian table_size += size_dw; \ 14463127922SJane Jian } 14563127922SJane Jian 14663127922SJane Jian #endif 147