Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70 |
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#
e56c9ef6 |
| 23-Sep-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add soc config init for GC9.4.3 ASICs
Add function to initialize soc configuration information for GC 9.4.3 ASICs. Use it to map IPs and other SOC related information once IP configurati
drm/amdgpu: Add soc config init for GC9.4.3 ASICs
Add function to initialize soc configuration information for GC 9.4.3 ASICs. Use it to map IPs and other SOC related information once IP configuration information is available through discovery.
For GC9.4.3 compute partition related callbacks are initialized as part of configuration init.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2fa480d3 |
| 27-Sep-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add helpers to access registers on different AIDs
SMN address which is larger than 32bit has different indications through bit[34:32] on different AIDs.
v2: put smn addressing of differ
drm/amdgpu: add helpers to access registers on different AIDs
SMN address which is larger than 32bit has different indications through bit[34:32] on different AIDs.
v2: put smn addressing of different AIDs into asic specific place v3: change to ext_id/ext_offset naming
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42 |
|
#
1dfcdc30 |
| 24-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: switch to aqua_vanjaram_doorbell_index_init
New doorbell index assignment is used by aqua_vanjaram.
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Sig
drm/amdgpu: switch to aqua_vanjaram_doorbell_index_init
New doorbell index assignment is used by aqua_vanjaram.
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cab7d478 |
| 29-Jun-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add IP instance map for aqua vanjaram
Add XCC logical to physical instance map for aqua vanjaram
v2: Keep look up table only for required IPs, for others return default mapping (Felix)
drm/amdgpu: Add IP instance map for aqua vanjaram
Add XCC logical to physical instance map for aqua vanjaram
v2: Keep look up table only for required IPs, for others return default mapping (Felix).
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3 |
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#
5aa998ba |
| 17-Nov-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to soc15_grbm_select
To support grbm select for multiple XCD case.
v2: unify naming style
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawkin
drm/amdgpu: add xcc index argument to soc15_grbm_select
To support grbm select for multiple XCD case.
v2: unify naming style
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12 |
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#
7092432e |
| 11-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop soc15_set_ip_blocks()
No longer used since IP enumeration is now driven by amdgpu IP discovery code.
Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.
drm/amdgpu: drop soc15_set_ip_blocks()
No longer used since IP enumeration is now driven by amdgpu IP discovery code.
Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60 |
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#
994470b2 |
| 30-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/soc15: export common IP functions
So they can be driven by IP discovery table.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2485e275 |
| 30-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: make soc15_common_ip_funcs static
It's not used outside of soc15.c
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
4abc2567 |
| 27-Jan-2021 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: refine ras codes for GC utc of aldebaran
The bank number of both VML2 and ATCL2 are changed to 8, so refine related codes to avoid defining long name arrays.
Signed-off-by: Dennis Li <D
drm/amdgpu: refine ras codes for GC utc of aldebaran
The bank number of both VML2 and ATCL2 are changed to 8, so refine related codes to avoid defining long name arrays.
Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
22616eb5 |
| 25-Jan-2021 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: add ras support for gfx of aldebaran
add edc counter/status reset and query functions for gfx block of aldebaran.
v2: change to clear edc counter explicitly aldebaran hardware will not
drm/amdgpu: add ras support for gfx of aldebaran
add edc counter/status reset and query functions for gfx block of aldebaran.
v2: change to clear edc counter explicitly aldebaran hardware will not clear edc counter after driver reading them, so driver should clear them explicitly.
Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8 |
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#
42b72608 |
| 05-Sep-2020 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add register base init for aldebaran (v2)
v1: add aldebaran_reg_base_init function to initialize register base for aldebaran (Le) v2: update VCN HWIP and initialize base offset (James)
drm/amdgpu: add register base init for aldebaran (v2)
v1: add aldebaran_reg_base_init function to initialize register base for aldebaran (Le) v2: update VCN HWIP and initialize base offset (James)
Signed-off-by: Le Ma <le.ma@amd.com> Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6 |
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#
c1299461 |
| 22-Jun-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: request init data in virt detection
Move request init data to virt detection func, so we can insert request full access between request init data and set ip blocks.
Signed-off-by: Wenhu
drm/amdgpu: request init data in virt detection
Move request init data to virt detection func, so we can insert request full access between request init data and set ip blocks.
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25 |
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#
2e0cc4d4 |
| 10-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: revise RLCG access path
what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op function can acc
drm/amdgpu: revise RLCG access path
what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op function can access reg that need RLCG path help
now even debugfs's reg_op can used to dump wave.
tested-by: Monk Liu <monk.liu@amd.com> tested-by: Zhou pengju <pengju.zhou@amd.com> Signed-off-by: Zhou pengju <pengju.zhou@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12 |
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#
f920d1bb |
| 18-Nov-2019 |
changzhu <Changfeng.Zhu@amd.com> |
drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add sema
drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire before invalidation and semaphore release after invalidation.
After adding semaphore acquire before invalidation, the semaphore register become read-only if another process try to acquire semaphore. Then it will not be able to release this semaphore. Then it may cause deadlock problem. If this deadlock problem happens, it needs a semaphore firmware fix.
Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
4ed8a037 |
| 18-Nov-2019 |
changzhu <Changfeng.Zhu@amd.com> |
drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add sema
drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire before invalidation and semaphore release after invalidation.
After adding semaphore acquire before invalidation, the semaphore register become read-only if another process try to acquire semaphore. Then it will not be able to release this semaphore. Then it may cause deadlock problem. If this deadlock problem happens, it needs a semaphore firmware fix.
Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
46f71969 |
| 19-Nov-2019 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: define soc15_ras_field_entry for reuse
The struct soc15_ras_field_entry will be reused by other IPs, such as mmhub and gc
v2: rename ras_subblock_regs to gc_ras_fields_vg20, because the
drm/amdgpu: define soc15_ras_field_entry for reuse
The struct soc15_ras_field_entry will be reused by other IPs, such as mmhub and gc
v2: rename ras_subblock_regs to gc_ras_fields_vg20, because the future asic maybe have a different table.
Signed-off-by: Dennis Li <dennis.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7 |
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#
13ba0344 |
| 12-Oct-2019 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: change to query the actual EDC counter
For the potential request in the future, change to query the actual EDC counter.
Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking
drm/amdgpu: change to query the actual EDC counter
For the potential request in the future, change to query the actual EDC counter.
Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <hawking.zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1 |
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#
e78705ec |
| 09-Jul-2019 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: dynamically initialize IP offset for Arcturus
Add support for the IP offsets on Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by:
drm/amdgpu: dynamically initialize IP offset for Arcturus
Add support for the IP offsets on Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1 |
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#
44f1bb1f |
| 10-May-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10
Move to the header file.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10
Move to the header file.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
052af915 |
| 04-Jun-2019 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: Fixed missing to clear some EDC count
EDC counts are related to instance and se. They are not the same for different type of EDC. EDC clearing are changed to base on individual EDC's ins
drm/amdgpu: Fixed missing to clear some EDC count
EDC counts are related to instance and se. They are not the same for different type of EDC. EDC clearing are changed to base on individual EDC's instance and SE number.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7 |
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#
5326ad54 |
| 05-Apr-2019 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled
When RAS is enabled, initializes the VGPRs/LDS/SGPRs and resets EDC error counts. This is done in late_init, before RAS TA GFX enable.
Si
drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled
When RAS is enabled, initializes the VGPRs/LDS/SGPRs and resets EDC error counts. This is done in late_init, before RAS TA GFX enable.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3 |
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#
c93aa775 |
| 19-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Doorbell layout for vega20 and future asic
This introduces new doorbell layout for vega20 and future asics
v2: Use enum definition instead of hardcoded value
Signed-off-by: Oak Zeng <o
drm/amdgpu: Doorbell layout for vega20 and future asic
This introduces new doorbell layout for vega20 and future asics
v2: Use enum definition instead of hardcoded value
Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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062f3807 |
| 19-Nov-2018 |
Oak Zeng <ozeng@amd.com> |
drm/amdgpu: Vega10 doorbell index initialization
v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition
Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kue
drm/amdgpu: Vega10 doorbell index initialization
v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition
Signed-off-by: Oak Zeng <ozeng@amd.com> Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6, v4.17.5, v4.17.4, v4.17.3, v4.17.2, v4.17.1, v4.17, v4.16 |
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fe3c9489 |
| 23-Mar-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu: Add nbio 7.4 support for vega20 (v3)
Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20.
v2: fix doorbell range for sdma (Alex) v3: squ
drm/amdgpu: Add nbio 7.4 support for vega20 (v3)
Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20.
v2: fix doorbell range for sdma (Alex) v3: squash in static fix (kbuild test robot)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8ee273e5 |
| 23-Mar-2018 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu/soc15: dynamic initialize ip offset for vega20
Vega20 need a seperate vega20_reg_init.c due to ip base offset difference.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-o
drm/amdgpu/soc15: dynamic initialize ip offset for vega20
Vega20 need a seperate vega20_reg_init.c due to ip base offset difference.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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