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Searched refs:reg1 (Results 76 – 100 of 213) sorted by relevance

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/openbmc/linux/drivers/media/dvb-frontends/
H A Dm88rs2000.c241 u8 reg0, reg1; in m88rs2000_send_diseqc_burst() local
246 reg1 = m88rs2000_readreg(state, 0xb2); in m88rs2000_send_diseqc_burst()
248 m88rs2000_writereg(state, 0xb2, reg1); in m88rs2000_send_diseqc_burst()
259 u8 reg0, reg1; in m88rs2000_set_tone() local
262 reg1 = m88rs2000_readreg(state, 0xb2); in m88rs2000_set_tone()
264 reg1 &= 0x3f; in m88rs2000_set_tone()
272 reg1 |= 0x80; in m88rs2000_set_tone()
277 m88rs2000_writereg(state, 0xb2, reg1); in m88rs2000_set_tone()
H A Ds5h1409.c556 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode() local
571 reg1 = s5h1409_readreg(state, 0xb2); in s5h1409_set_qam_interleave_mode()
576 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); in s5h1409_set_qam_interleave_mode()
594 u16 reg, reg1, reg2; in s5h1409_set_qam_interleave_mode_legacy() local
602 reg1 = s5h1409_readreg(state, 0xb2); in s5h1409_set_qam_interleave_mode_legacy()
607 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); in s5h1409_set_qam_interleave_mode_legacy()
H A Dstv0297.c95 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len) in stv0297_readregs() argument
99 &reg1,.len = 1}, in stv0297_readregs()
106 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret); in stv0297_readregs()
110 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret); in stv0297_readregs()
115 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret); in stv0297_readregs()
/openbmc/linux/drivers/hwmon/
H A Dnct7904.c392 unsigned int reg1, reg2, reg3; in nct7904_read_temp() local
465 reg1 = LTD_HV_LL_REG; in nct7904_read_temp()
470 reg1 = LTD_LV_LL_REG; in nct7904_read_temp()
475 reg1 = LTD_HV_HL_REG; in nct7904_read_temp()
480 reg1 = LTD_LV_HL_REG; in nct7904_read_temp()
489 ret = nct7904_read_reg(data, BANK_1, reg1); in nct7904_read_temp()
569 unsigned int reg1, reg2, reg3; in nct7904_write_temp() local
575 reg1 = LTD_HV_LL_REG; in nct7904_write_temp()
580 reg1 = LTD_LV_LL_REG; in nct7904_write_temp()
585 reg1 = LTD_HV_HL_REG; in nct7904_write_temp()
[all …]
/openbmc/linux/drivers/tee/optee/
H A Doptee_private.h330 static inline void *reg_pair_to_ptr(u32 reg0, u32 reg1) in reg_pair_to_ptr() argument
332 return (void *)(unsigned long)(((u64)reg0 << 32) | reg1); in reg_pair_to_ptr()
335 static inline void reg_pair_from_64(u32 *reg0, u32 *reg1, u64 val) in reg_pair_from_64() argument
338 *reg1 = val; in reg_pair_from_64()
/openbmc/u-boot/drivers/sound/
H A Dwm8994.c424 int reg1 = 0; in configure_aif_clock() local
436 reg1 |= SEL_MCLK1; in configure_aif_clock()
441 reg1 |= SEL_MCLK2; in configure_aif_clock()
446 reg1 |= SEL_FLL1; in configure_aif_clock()
451 reg1 |= SEL_FLL2; in configure_aif_clock()
464 reg1 |= WM8994_AIF1CLK_DIV; in configure_aif_clock()
471 reg1); in configure_aif_clock()
/openbmc/linux/drivers/pci/controller/
H A Dpcie-altera.c121 u32 reg1; member
172 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); in tlp_write_tx()
203 u32 reg0, reg1; in tlp_read_packet() local
214 reg1 = cra_readl(pcie, RP_RXCPL_REG1); in tlp_read_packet()
218 comp_status = TLP_COMP_STATUS(reg1); in tlp_read_packet()
290 tlp_rp_regdata.reg1 = headers[1]; in tlp_write_packet()
296 tlp_rp_regdata.reg1 = 0; in tlp_write_packet()
301 tlp_rp_regdata.reg1 = 0; in tlp_write_packet()
304 tlp_rp_regdata.reg1 = data; in tlp_write_packet()
/openbmc/linux/drivers/net/dsa/sja1105/
H A Dsja1105_dynamic_config.c585 u8 *reg1 = buf + 4; in sja1105et_mac_config_cmd_packing() local
587 sja1105_packing(reg1, &cmd->valid, 31, 31, size, op); in sja1105et_mac_config_cmd_packing()
588 sja1105_packing(reg1, &cmd->index, 26, 24, size, op); in sja1105et_mac_config_cmd_packing()
597 u8 *reg1 = buf + 4; in sja1105et_mac_config_entry_packing() local
600 sja1105_packing(reg1, &entry->speed, 30, 29, size, op); in sja1105et_mac_config_entry_packing()
601 sja1105_packing(reg1, &entry->drpdtag, 23, 23, size, op); in sja1105et_mac_config_entry_packing()
602 sja1105_packing(reg1, &entry->drpuntag, 22, 22, size, op); in sja1105et_mac_config_entry_packing()
603 sja1105_packing(reg1, &entry->retag, 21, 21, size, op); in sja1105et_mac_config_entry_packing()
604 sja1105_packing(reg1, &entry->dyn_learn, 20, 20, size, op); in sja1105et_mac_config_entry_packing()
605 sja1105_packing(reg1, &entry->egress, 19, 19, size, op); in sja1105et_mac_config_entry_packing()
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dcrct10dif-ce-core.S218 .macro fold_32_bytes, p, reg1, reg2
221 __pmull_\p v8, \reg1, fold_consts, 2
222 __pmull_\p \reg1, \reg1, fold_consts
233 eor \reg1\().16b, \reg1\().16b, v8.16b
235 eor \reg1\().16b, \reg1\().16b, v11.16b
/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-dc.c123 u32 reg1, reg2; in dc_write_tmpl() local
126 reg1 = (operand << 20) & 0xfff00000; in dc_write_tmpl()
129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); in dc_write_tmpl()
132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); in dc_write_tmpl()
135 writel(reg1, priv->dc_tmpl_reg + word * 8); in dc_write_tmpl()
/openbmc/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_mdio.c139 u32 reg1, reg2; in calculate_i1clk() local
142 reg1 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG1); in calculate_i1clk()
145 core_f = (reg1 & MLXBF_GIGE_MDIO_CORE_F_MASK) >> in calculate_i1clk()
147 core_r = (reg1 & MLXBF_GIGE_MDIO_CORE_R_MASK) >> in calculate_i1clk()
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dspectral.c71 u32 reg0, reg1; in ath10k_spectral_process_fft() local
83 reg1 = __le32_to_cpu(fftr->reg1); in ath10k_spectral_process_fft()
114 fft_sample->relpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB); in ath10k_spectral_process_fft()
115 fft_sample->avgpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB); in ath10k_spectral_process_fft()
117 peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG); in ath10k_spectral_process_fft()
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
143 if (reg1 <= 0x405c) { in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
175 if (ret || !(reg1 = pll_lim.reg)) in nouveau_hw_get_pllvals()
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
179 if (reg1 <= 0x405c) in nouveau_hw_get_pllvals()
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
182 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); in nouveau_hw_get_pllvals()
187 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { in nouveau_hw_get_pllvals()
191 if (reg1 == NV_PRAMDAC_VPLL_COEFF) { in nouveau_hw_get_pllvals()
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dprocessor.h329 unsigned int reg1, reg2; in __extract_psw() local
331 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); in __extract_psw()
332 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); in __extract_psw()
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Drockchip,rk806.yaml34 The input supply for dcdc-reg1.
74 The input supply for pldo-reg1, pldo-reg2 and pldo-reg3.
82 The input supply for nldo-reg1, nldo-reg2 and nldo-reg3.
157 vdd_gpu_s0: dcdc-reg1 {
277 avcc_1v8_s0: pldo-reg1 {
351 vdd_0v75_s3: nldo-reg1 {
/openbmc/linux/drivers/media/platform/ti/cal/
H A Dcal-camerarx.c135 unsigned int reg0, reg1; in cal_camerarx_config() local
157 reg1 = camerarx_read(phy, CAL_CSI2_PHY_REG1); in cal_camerarx_config()
158 cal_set_field(&reg1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK); in cal_camerarx_config()
159 cal_set_field(&reg1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK); in cal_camerarx_config()
160 cal_set_field(&reg1, TCLK_MISS, in cal_camerarx_config()
162 cal_set_field(&reg1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK); in cal_camerarx_config()
164 phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x\n", phy->instance, reg1); in cal_camerarx_config()
165 camerarx_write(phy, CAL_CSI2_PHY_REG1, reg1); in cal_camerarx_config()
/openbmc/linux/drivers/ata/
H A Dpata_hpt366.c391 u32 reg1; in hpt36x_init_one() local
405 pci_read_config_dword(dev, 0x40, &reg1); in hpt36x_init_one()
409 switch ((reg1 & 0xf00) >> 8) { in hpt36x_init_one()
/openbmc/linux/drivers/i2c/busses/
H A Di2c-mchp-pci1xxxx.c524 u16 reg1; in pci1xxxx_i2c_isr() local
531 reg1 = readw(p1); in pci1xxxx_i2c_isr()
533 if (reg1 & I2C_BUF_MSTR_INTR_MASK) { in pci1xxxx_i2c_isr()
543 if (reg1 & SMBALERT_INTR_MASK) { in pci1xxxx_i2c_isr()
648 u8 reg1; in pci1xxxx_i2c_configure_core_reg() local
651 reg1 = readb(p1); in pci1xxxx_i2c_configure_core_reg()
654 reg1 |= SMB_CONFIG1_ENAB | SMB_CONFIG1_FEN; in pci1xxxx_i2c_configure_core_reg()
657 reg1 &= ~(SMB_CONFIG1_ENAB | SMB_CONFIG1_FEN); in pci1xxxx_i2c_configure_core_reg()
661 writeb(reg1, p1); in pci1xxxx_i2c_configure_core_reg()
/openbmc/linux/drivers/power/supply/
H A Dwm831x_power.c260 int ret, reg1, reg2; in wm831x_config_battery() local
270 reg1 = 0; in wm831x_config_battery()
278 reg1 |= WM831X_CHG_ENA; in wm831x_config_battery()
282 reg1 |= WM831X_CHG_FAST; in wm831x_config_battery()
298 pdata->eoc_iterm, &reg1, in wm831x_config_battery()
315 reg1); in wm831x_config_battery()
/openbmc/linux/arch/s390/boot/
H A Dipl_parm.c34 unsigned long reg1, reg2; in __diag308() local
50 [reg1] "=&d" (reg1), in __diag308()
/openbmc/linux/sound/soc/codecs/
H A Dwm8993.c471 u16 reg1, reg4, reg5; in _wm8993_set_fll() local
486 reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1); in _wm8993_set_fll()
487 reg1 &= ~WM8993_FLL_ENA; in _wm8993_set_fll()
488 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1); in _wm8993_set_fll()
519 reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1); in _wm8993_set_fll()
520 reg1 &= ~WM8993_FLL_ENA; in _wm8993_set_fll()
521 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1); in _wm8993_set_fll()
525 reg1 |= WM8993_FLL_FRAC_MASK; in _wm8993_set_fll()
527 reg1 &= ~WM8993_FLL_FRAC_MASK; in _wm8993_set_fll()
528 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1); in _wm8993_set_fll()
[all …]
H A Dwm9081.c549 u16 reg1, reg4, reg5; in wm9081_set_fll() local
592 reg1 = snd_soc_component_read(component, WM9081_FLL_CONTROL_1); in wm9081_set_fll()
593 reg1 &= ~WM9081_FLL_ENA; in wm9081_set_fll()
594 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1); in wm9081_set_fll()
598 reg1 |= WM9081_FLL_FRAC_MASK; in wm9081_set_fll()
600 reg1 &= ~WM9081_FLL_FRAC_MASK; in wm9081_set_fll()
601 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1); in wm9081_set_fll()
622 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); in wm9081_set_fll()
/openbmc/linux/drivers/tty/serial/
H A Dmvebu-uart.c1051 void __iomem *reg1; member
1099 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_prepare()
1147 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_prepare()
1180 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_enable()
1187 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_enable()
1204 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_disable()
1211 writel(val, uart_clock_base->reg1); in mvebu_uart_clock_disable()
1223 val = readl(uart_clock_base->reg1); in mvebu_uart_clock_is_enabled()
1239 uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1); in mvebu_uart_clock_save_context()
1361 uart_clock_base->reg1 = devm_ioremap(dev, res->start, in mvebu_uart_clock_probe()
[all …]
/openbmc/linux/arch/ia64/include/asm/native/
H A Dinst.h72 #define THASH(pred, reg0, reg1, clob) \ argument
73 (pred) thash reg0 = reg1
/openbmc/linux/arch/parisc/kernel/
H A Dsyscall.S54 .macro lws_pagefault_disable reg1,reg2
57 ldw 0(%sr2,\reg2), \reg1
58 ldo 1(\reg1), \reg1
59 stw \reg1, 0(%sr2,\reg2)
62 .macro lws_pagefault_enable reg1,reg2
65 ldw 0(%sr2,\reg2), \reg1
66 ldo -1(\reg1), \reg1
67 stw \reg1, 0(%sr2,\reg2)

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