1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+
230530791SWilson Ding /*
330530791SWilson Ding * ***************************************************************************
489ebc274SPaul Gortmaker * Marvell Armada-3700 Serial Driver
589ebc274SPaul Gortmaker * Author: Wilson Ding <dingwei@marvell.com>
630530791SWilson Ding * Copyright (C) 2015 Marvell International Ltd.
730530791SWilson Ding * ***************************************************************************
830530791SWilson Ding */
930530791SWilson Ding
1030530791SWilson Ding #include <linux/clk.h>
11b7e2b536SPali Rohár #include <linux/clk-provider.h>
1230530791SWilson Ding #include <linux/console.h>
1330530791SWilson Ding #include <linux/delay.h>
1430530791SWilson Ding #include <linux/device.h>
1530530791SWilson Ding #include <linux/init.h>
1630530791SWilson Ding #include <linux/io.h>
1730530791SWilson Ding #include <linux/iopoll.h>
18b7e2b536SPali Rohár #include <linux/math64.h>
1930530791SWilson Ding #include <linux/of.h>
2030530791SWilson Ding #include <linux/of_address.h>
2130530791SWilson Ding #include <linux/of_device.h>
2230530791SWilson Ding #include <linux/of_irq.h>
2330530791SWilson Ding #include <linux/of_platform.h>
2430530791SWilson Ding #include <linux/platform_device.h>
2530530791SWilson Ding #include <linux/serial.h>
2630530791SWilson Ding #include <linux/serial_core.h>
2730530791SWilson Ding #include <linux/slab.h>
2830530791SWilson Ding #include <linux/tty.h>
2930530791SWilson Ding #include <linux/tty_flip.h>
3030530791SWilson Ding
3130530791SWilson Ding /* Register Map */
325218d769SMiquel Raynal #define UART_STD_RBR 0x00
3353501e02SMiquel Raynal #define UART_EXT_RBR 0x18
3430530791SWilson Ding
355218d769SMiquel Raynal #define UART_STD_TSH 0x04
3653501e02SMiquel Raynal #define UART_EXT_TSH 0x1C
3730530791SWilson Ding
385218d769SMiquel Raynal #define UART_STD_CTRL1 0x08
3953501e02SMiquel Raynal #define UART_EXT_CTRL1 0x04
4030530791SWilson Ding #define CTRL_SOFT_RST BIT(31)
4130530791SWilson Ding #define CTRL_TXFIFO_RST BIT(15)
4230530791SWilson Ding #define CTRL_RXFIFO_RST BIT(14)
4330530791SWilson Ding #define CTRL_SND_BRK_SEQ BIT(11)
4430530791SWilson Ding #define CTRL_BRK_DET_INT BIT(3)
4530530791SWilson Ding #define CTRL_FRM_ERR_INT BIT(2)
4630530791SWilson Ding #define CTRL_PAR_ERR_INT BIT(1)
4730530791SWilson Ding #define CTRL_OVR_ERR_INT BIT(0)
485218d769SMiquel Raynal #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
495218d769SMiquel Raynal CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
5030530791SWilson Ding
515218d769SMiquel Raynal #define UART_STD_CTRL2 UART_STD_CTRL1
5253501e02SMiquel Raynal #define UART_EXT_CTRL2 0x20
535218d769SMiquel Raynal #define CTRL_STD_TX_RDY_INT BIT(5)
5453501e02SMiquel Raynal #define CTRL_EXT_TX_RDY_INT BIT(6)
555218d769SMiquel Raynal #define CTRL_STD_RX_RDY_INT BIT(4)
5653501e02SMiquel Raynal #define CTRL_EXT_RX_RDY_INT BIT(5)
575218d769SMiquel Raynal
585218d769SMiquel Raynal #define UART_STAT 0x0C
5930530791SWilson Ding #define STAT_TX_FIFO_EMP BIT(13)
6030530791SWilson Ding #define STAT_TX_FIFO_FUL BIT(11)
6130530791SWilson Ding #define STAT_TX_EMP BIT(6)
625218d769SMiquel Raynal #define STAT_STD_TX_RDY BIT(5)
6353501e02SMiquel Raynal #define STAT_EXT_TX_RDY BIT(15)
645218d769SMiquel Raynal #define STAT_STD_RX_RDY BIT(4)
6553501e02SMiquel Raynal #define STAT_EXT_RX_RDY BIT(14)
6630530791SWilson Ding #define STAT_BRK_DET BIT(3)
6730530791SWilson Ding #define STAT_FRM_ERR BIT(2)
6830530791SWilson Ding #define STAT_PAR_ERR BIT(1)
6930530791SWilson Ding #define STAT_OVR_ERR BIT(0)
700ef5a6e0SColin Ian King #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \
7130530791SWilson Ding | STAT_PAR_ERR | STAT_OVR_ERR)
7230530791SWilson Ding
73b7e2b536SPali Rohár /*
74b7e2b536SPali Rohár * Marvell Armada 3700 Functional Specifications describes that bit 21 of UART
75b7e2b536SPali Rohár * Clock Control register controls UART1 and bit 20 controls UART2. But in
76b7e2b536SPali Rohár * reality bit 21 controls UART2 and bit 20 controls UART1. This seems to be an
77b7e2b536SPali Rohár * error in Marvell's documentation. Hence following CLK_DIS macros are swapped.
78b7e2b536SPali Rohár */
79b7e2b536SPali Rohár
8030530791SWilson Ding #define UART_BRDV 0x10
81b7e2b536SPali Rohár /* These bits are located in UART1 address space and control UART2 */
82b7e2b536SPali Rohár #define UART2_CLK_DIS BIT(21)
83b7e2b536SPali Rohár /* These bits are located in UART1 address space and control UART1 */
84b7e2b536SPali Rohár #define UART1_CLK_DIS BIT(20)
85b7e2b536SPali Rohár /* These bits are located in UART1 address space and control both UARTs */
86b7e2b536SPali Rohár #define CLK_NO_XTAL BIT(19)
87b7e2b536SPali Rohár #define CLK_TBG_DIV1_SHIFT 15
88b7e2b536SPali Rohár #define CLK_TBG_DIV1_MASK 0x7
89b7e2b536SPali Rohár #define CLK_TBG_DIV1_MAX 6
90b7e2b536SPali Rohár #define CLK_TBG_DIV2_SHIFT 12
91b7e2b536SPali Rohár #define CLK_TBG_DIV2_MASK 0x7
92b7e2b536SPali Rohár #define CLK_TBG_DIV2_MAX 6
93b7e2b536SPali Rohár #define CLK_TBG_SEL_SHIFT 10
94b7e2b536SPali Rohár #define CLK_TBG_SEL_MASK 0x3
95b7e2b536SPali Rohár /* These bits are located in both UARTs address space */
9668a0db1dSAllen Yan #define BRDV_BAUD_MASK 0x3FF
97b7e2b536SPali Rohár #define BRDV_BAUD_MAX BRDV_BAUD_MASK
9830530791SWilson Ding
99394e8351SMiquel Raynal #define UART_OSAMP 0x14
1000e4cf69eSMiquel Raynal #define OSAMP_DEFAULT_DIVISOR 16
10135d7a58aSMiquel Raynal #define OSAMP_DIVISORS_MASK 0x3F3F3F3F
102694b7112SPali Rohár #define OSAMP_MAX_DIVISOR 63
103394e8351SMiquel Raynal
1043a75e91bSMiquel Raynal #define MVEBU_NR_UARTS 2
10530530791SWilson Ding
10630530791SWilson Ding #define MVEBU_UART_TYPE "mvebu-uart"
10702c33330SYehuda Yitschak #define DRIVER_NAME "mvebu_serial"
10830530791SWilson Ding
10995f78768SMiquel Raynal enum {
11095f78768SMiquel Raynal /* Either there is only one summed IRQ... */
11195f78768SMiquel Raynal UART_IRQ_SUM = 0,
11295f78768SMiquel Raynal /* ...or there are two separate IRQ for RX and TX */
11395f78768SMiquel Raynal UART_RX_IRQ = 0,
11495f78768SMiquel Raynal UART_TX_IRQ,
11595f78768SMiquel Raynal UART_IRQ_COUNT
11695f78768SMiquel Raynal };
11795f78768SMiquel Raynal
11895f78768SMiquel Raynal /* Diverging register offsets */
1195218d769SMiquel Raynal struct uart_regs_layout {
1205218d769SMiquel Raynal unsigned int rbr;
1215218d769SMiquel Raynal unsigned int tsh;
1225218d769SMiquel Raynal unsigned int ctrl;
1235218d769SMiquel Raynal unsigned int intr;
1245218d769SMiquel Raynal };
12530530791SWilson Ding
1265218d769SMiquel Raynal /* Diverging flags */
1275218d769SMiquel Raynal struct uart_flags {
1285218d769SMiquel Raynal unsigned int ctrl_tx_rdy_int;
1295218d769SMiquel Raynal unsigned int ctrl_rx_rdy_int;
1305218d769SMiquel Raynal unsigned int stat_tx_rdy;
1315218d769SMiquel Raynal unsigned int stat_rx_rdy;
1325218d769SMiquel Raynal };
1335218d769SMiquel Raynal
1345218d769SMiquel Raynal /* Driver data, a structure for each UART port */
1355218d769SMiquel Raynal struct mvebu_uart_driver_data {
1365218d769SMiquel Raynal bool is_ext;
1375218d769SMiquel Raynal struct uart_regs_layout regs;
1385218d769SMiquel Raynal struct uart_flags flags;
1395218d769SMiquel Raynal };
1405218d769SMiquel Raynal
141394e8351SMiquel Raynal /* Saved registers during suspend */
142394e8351SMiquel Raynal struct mvebu_uart_pm_regs {
143394e8351SMiquel Raynal unsigned int rbr;
144394e8351SMiquel Raynal unsigned int tsh;
145394e8351SMiquel Raynal unsigned int ctrl;
146394e8351SMiquel Raynal unsigned int intr;
147394e8351SMiquel Raynal unsigned int stat;
148394e8351SMiquel Raynal unsigned int brdv;
149394e8351SMiquel Raynal unsigned int osamp;
150394e8351SMiquel Raynal };
151394e8351SMiquel Raynal
1525218d769SMiquel Raynal /* MVEBU UART driver structure */
1535218d769SMiquel Raynal struct mvebu_uart {
15430530791SWilson Ding struct uart_port *port;
15530530791SWilson Ding struct clk *clk;
15695f78768SMiquel Raynal int irq[UART_IRQ_COUNT];
1575218d769SMiquel Raynal struct mvebu_uart_driver_data *data;
158394e8351SMiquel Raynal #if defined(CONFIG_PM)
159394e8351SMiquel Raynal struct mvebu_uart_pm_regs pm_regs;
160394e8351SMiquel Raynal #endif /* CONFIG_PM */
16130530791SWilson Ding };
16230530791SWilson Ding
to_mvuart(struct uart_port * port)1635218d769SMiquel Raynal static struct mvebu_uart *to_mvuart(struct uart_port *port)
1645218d769SMiquel Raynal {
1655218d769SMiquel Raynal return (struct mvebu_uart *)port->private_data;
1665218d769SMiquel Raynal }
1675218d769SMiquel Raynal
1685218d769SMiquel Raynal #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
1695218d769SMiquel Raynal
1705218d769SMiquel Raynal #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
1715218d769SMiquel Raynal #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
1725218d769SMiquel Raynal #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
1735218d769SMiquel Raynal #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
1745218d769SMiquel Raynal
1755218d769SMiquel Raynal #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
1765218d769SMiquel Raynal #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
1775218d769SMiquel Raynal #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
1785218d769SMiquel Raynal #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
1795218d769SMiquel Raynal
1805218d769SMiquel Raynal static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
1815218d769SMiquel Raynal
182b7e2b536SPali Rohár static DEFINE_SPINLOCK(mvebu_uart_lock);
183b7e2b536SPali Rohár
18430530791SWilson Ding /* Core UART Driver Operations */
mvebu_uart_tx_empty(struct uart_port * port)18530530791SWilson Ding static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
18630530791SWilson Ding {
18730530791SWilson Ding unsigned long flags;
18830530791SWilson Ding unsigned int st;
18930530791SWilson Ding
19030530791SWilson Ding spin_lock_irqsave(&port->lock, flags);
19130530791SWilson Ding st = readl(port->membase + UART_STAT);
19230530791SWilson Ding spin_unlock_irqrestore(&port->lock, flags);
19330530791SWilson Ding
19474e1eb3bSPali Rohár return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0;
19530530791SWilson Ding }
19630530791SWilson Ding
mvebu_uart_get_mctrl(struct uart_port * port)19730530791SWilson Ding static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
19830530791SWilson Ding {
19930530791SWilson Ding return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
20030530791SWilson Ding }
20130530791SWilson Ding
mvebu_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)20230530791SWilson Ding static void mvebu_uart_set_mctrl(struct uart_port *port,
20330530791SWilson Ding unsigned int mctrl)
20430530791SWilson Ding {
20530530791SWilson Ding /*
20630530791SWilson Ding * Even if we do not support configuring the modem control lines, this
20730530791SWilson Ding * function must be proided to the serial core
20830530791SWilson Ding */
20930530791SWilson Ding }
21030530791SWilson Ding
mvebu_uart_stop_tx(struct uart_port * port)21130530791SWilson Ding static void mvebu_uart_stop_tx(struct uart_port *port)
21230530791SWilson Ding {
2135218d769SMiquel Raynal unsigned int ctl = readl(port->membase + UART_INTR(port));
21430530791SWilson Ding
2155218d769SMiquel Raynal ctl &= ~CTRL_TX_RDY_INT(port);
2165218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port));
21730530791SWilson Ding }
21830530791SWilson Ding
mvebu_uart_start_tx(struct uart_port * port)21930530791SWilson Ding static void mvebu_uart_start_tx(struct uart_port *port)
22030530791SWilson Ding {
22130434b07SAllen Yan unsigned int ctl;
22230434b07SAllen Yan struct circ_buf *xmit = &port->state->xmit;
22330530791SWilson Ding
22430434b07SAllen Yan if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
22530434b07SAllen Yan writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
226269599faSIlpo Järvinen uart_xmit_advance(port, 1);
22730434b07SAllen Yan }
22830434b07SAllen Yan
22930434b07SAllen Yan ctl = readl(port->membase + UART_INTR(port));
2305218d769SMiquel Raynal ctl |= CTRL_TX_RDY_INT(port);
2315218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port));
23230530791SWilson Ding }
23330530791SWilson Ding
mvebu_uart_stop_rx(struct uart_port * port)23430530791SWilson Ding static void mvebu_uart_stop_rx(struct uart_port *port)
23530530791SWilson Ding {
2365218d769SMiquel Raynal unsigned int ctl;
23730530791SWilson Ding
2385218d769SMiquel Raynal ctl = readl(port->membase + UART_CTRL(port));
2395218d769SMiquel Raynal ctl &= ~CTRL_BRK_INT;
2405218d769SMiquel Raynal writel(ctl, port->membase + UART_CTRL(port));
2415218d769SMiquel Raynal
2425218d769SMiquel Raynal ctl = readl(port->membase + UART_INTR(port));
2435218d769SMiquel Raynal ctl &= ~CTRL_RX_RDY_INT(port);
2445218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port));
24530530791SWilson Ding }
24630530791SWilson Ding
mvebu_uart_break_ctl(struct uart_port * port,int brk)24730530791SWilson Ding static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
24830530791SWilson Ding {
24930530791SWilson Ding unsigned int ctl;
25030530791SWilson Ding unsigned long flags;
25130530791SWilson Ding
25230530791SWilson Ding spin_lock_irqsave(&port->lock, flags);
2535218d769SMiquel Raynal ctl = readl(port->membase + UART_CTRL(port));
25430530791SWilson Ding if (brk == -1)
25530530791SWilson Ding ctl |= CTRL_SND_BRK_SEQ;
25630530791SWilson Ding else
25730530791SWilson Ding ctl &= ~CTRL_SND_BRK_SEQ;
2585218d769SMiquel Raynal writel(ctl, port->membase + UART_CTRL(port));
25930530791SWilson Ding spin_unlock_irqrestore(&port->lock, flags);
26030530791SWilson Ding }
26130530791SWilson Ding
mvebu_uart_rx_chars(struct uart_port * port,unsigned int status)26230530791SWilson Ding static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
26330530791SWilson Ding {
26430530791SWilson Ding struct tty_port *tport = &port->state->port;
26530530791SWilson Ding unsigned char ch = 0;
26630530791SWilson Ding char flag = 0;
267a7209541SNarendra Hadke int ret;
26830530791SWilson Ding
26930530791SWilson Ding do {
2705218d769SMiquel Raynal if (status & STAT_RX_RDY(port)) {
2715218d769SMiquel Raynal ch = readl(port->membase + UART_RBR(port));
27230530791SWilson Ding ch &= 0xff;
27330530791SWilson Ding flag = TTY_NORMAL;
27430530791SWilson Ding port->icount.rx++;
27530530791SWilson Ding
27630530791SWilson Ding if (status & STAT_PAR_ERR)
27730530791SWilson Ding port->icount.parity++;
27830530791SWilson Ding }
27930530791SWilson Ding
280a7209541SNarendra Hadke /*
281a7209541SNarendra Hadke * For UART2, error bits are not cleared on buffer read.
282a7209541SNarendra Hadke * This causes interrupt loop and system hang.
283a7209541SNarendra Hadke */
284a7209541SNarendra Hadke if (IS_EXTENDED(port) && (status & STAT_BRK_ERR)) {
285a7209541SNarendra Hadke ret = readl(port->membase + UART_STAT);
286a7209541SNarendra Hadke ret |= STAT_BRK_ERR;
287a7209541SNarendra Hadke writel(ret, port->membase + UART_STAT);
288a7209541SNarendra Hadke }
289a7209541SNarendra Hadke
29030530791SWilson Ding if (status & STAT_BRK_DET) {
29130530791SWilson Ding port->icount.brk++;
29230530791SWilson Ding status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
29330530791SWilson Ding if (uart_handle_break(port))
29430530791SWilson Ding goto ignore_char;
29530530791SWilson Ding }
29630530791SWilson Ding
29730530791SWilson Ding if (status & STAT_OVR_ERR)
29830530791SWilson Ding port->icount.overrun++;
29930530791SWilson Ding
30030530791SWilson Ding if (status & STAT_FRM_ERR)
30130530791SWilson Ding port->icount.frame++;
30230530791SWilson Ding
30330530791SWilson Ding if (uart_handle_sysrq_char(port, ch))
30430530791SWilson Ding goto ignore_char;
30530530791SWilson Ding
30630530791SWilson Ding if (status & port->ignore_status_mask & STAT_PAR_ERR)
3075218d769SMiquel Raynal status &= ~STAT_RX_RDY(port);
30830530791SWilson Ding
30930530791SWilson Ding status &= port->read_status_mask;
31030530791SWilson Ding
31130530791SWilson Ding if (status & STAT_PAR_ERR)
31230530791SWilson Ding flag = TTY_PARITY;
31330530791SWilson Ding
31430530791SWilson Ding status &= ~port->ignore_status_mask;
31530530791SWilson Ding
3165218d769SMiquel Raynal if (status & STAT_RX_RDY(port))
31730530791SWilson Ding tty_insert_flip_char(tport, ch, flag);
31830530791SWilson Ding
31930530791SWilson Ding if (status & STAT_BRK_DET)
32030530791SWilson Ding tty_insert_flip_char(tport, 0, TTY_BREAK);
32130530791SWilson Ding
32230530791SWilson Ding if (status & STAT_FRM_ERR)
32330530791SWilson Ding tty_insert_flip_char(tport, 0, TTY_FRAME);
32430530791SWilson Ding
32530530791SWilson Ding if (status & STAT_OVR_ERR)
32630530791SWilson Ding tty_insert_flip_char(tport, 0, TTY_OVERRUN);
32730530791SWilson Ding
32830530791SWilson Ding ignore_char:
32930530791SWilson Ding status = readl(port->membase + UART_STAT);
3305218d769SMiquel Raynal } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
33130530791SWilson Ding
33230530791SWilson Ding tty_flip_buffer_push(tport);
33330530791SWilson Ding }
33430530791SWilson Ding
mvebu_uart_tx_chars(struct uart_port * port,unsigned int status)33530530791SWilson Ding static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
33630530791SWilson Ding {
337d11cc8c3SJiri Slaby (SUSE) u8 ch;
33830530791SWilson Ding
339d11cc8c3SJiri Slaby (SUSE) uart_port_tx_limited(port, ch, port->fifosize,
340d11cc8c3SJiri Slaby (SUSE) !(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL),
341d11cc8c3SJiri Slaby (SUSE) writel(ch, port->membase + UART_TSH(port)),
342d11cc8c3SJiri Slaby (SUSE) ({}));
34330530791SWilson Ding }
34430530791SWilson Ding
mvebu_uart_isr(int irq,void * dev_id)34530530791SWilson Ding static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
34630530791SWilson Ding {
34730530791SWilson Ding struct uart_port *port = (struct uart_port *)dev_id;
34830530791SWilson Ding unsigned int st = readl(port->membase + UART_STAT);
34930530791SWilson Ding
3505218d769SMiquel Raynal if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
3515218d769SMiquel Raynal STAT_BRK_DET))
35230530791SWilson Ding mvebu_uart_rx_chars(port, st);
35330530791SWilson Ding
3545218d769SMiquel Raynal if (st & STAT_TX_RDY(port))
35530530791SWilson Ding mvebu_uart_tx_chars(port, st);
35630530791SWilson Ding
35730530791SWilson Ding return IRQ_HANDLED;
35830530791SWilson Ding }
35930530791SWilson Ding
mvebu_uart_rx_isr(int irq,void * dev_id)36095f78768SMiquel Raynal static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
36195f78768SMiquel Raynal {
36295f78768SMiquel Raynal struct uart_port *port = (struct uart_port *)dev_id;
36395f78768SMiquel Raynal unsigned int st = readl(port->membase + UART_STAT);
36495f78768SMiquel Raynal
36595f78768SMiquel Raynal if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
36695f78768SMiquel Raynal STAT_BRK_DET))
36795f78768SMiquel Raynal mvebu_uart_rx_chars(port, st);
36895f78768SMiquel Raynal
36995f78768SMiquel Raynal return IRQ_HANDLED;
37095f78768SMiquel Raynal }
37195f78768SMiquel Raynal
mvebu_uart_tx_isr(int irq,void * dev_id)37295f78768SMiquel Raynal static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
37395f78768SMiquel Raynal {
37495f78768SMiquel Raynal struct uart_port *port = (struct uart_port *)dev_id;
37595f78768SMiquel Raynal unsigned int st = readl(port->membase + UART_STAT);
37695f78768SMiquel Raynal
37795f78768SMiquel Raynal if (st & STAT_TX_RDY(port))
37895f78768SMiquel Raynal mvebu_uart_tx_chars(port, st);
37995f78768SMiquel Raynal
38095f78768SMiquel Raynal return IRQ_HANDLED;
38195f78768SMiquel Raynal }
38295f78768SMiquel Raynal
mvebu_uart_startup(struct uart_port * port)38330530791SWilson Ding static int mvebu_uart_startup(struct uart_port *port)
38430530791SWilson Ding {
38595f78768SMiquel Raynal struct mvebu_uart *mvuart = to_mvuart(port);
3865218d769SMiquel Raynal unsigned int ctl;
38730530791SWilson Ding int ret;
38830530791SWilson Ding
38930530791SWilson Ding writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
3905218d769SMiquel Raynal port->membase + UART_CTRL(port));
39130530791SWilson Ding udelay(1);
3922ff23c48SAllen Yan
3932ff23c48SAllen Yan /* Clear the error bits of state register before IRQ request */
3942ff23c48SAllen Yan ret = readl(port->membase + UART_STAT);
3952ff23c48SAllen Yan ret |= STAT_BRK_ERR;
3962ff23c48SAllen Yan writel(ret, port->membase + UART_STAT);
3972ff23c48SAllen Yan
3985218d769SMiquel Raynal writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
3995218d769SMiquel Raynal
4005218d769SMiquel Raynal ctl = readl(port->membase + UART_INTR(port));
4015218d769SMiquel Raynal ctl |= CTRL_RX_RDY_INT(port);
4025218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port));
40330530791SWilson Ding
40495f78768SMiquel Raynal if (!mvuart->irq[UART_TX_IRQ]) {
40595f78768SMiquel Raynal /* Old bindings with just one interrupt (UART0 only) */
40695f78768SMiquel Raynal ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
40795f78768SMiquel Raynal mvebu_uart_isr, port->irqflags,
40895f78768SMiquel Raynal dev_name(port->dev), port);
40930530791SWilson Ding if (ret) {
41095f78768SMiquel Raynal dev_err(port->dev, "unable to request IRQ %d\n",
41195f78768SMiquel Raynal mvuart->irq[UART_IRQ_SUM]);
41230530791SWilson Ding return ret;
41330530791SWilson Ding }
41495f78768SMiquel Raynal } else {
41595f78768SMiquel Raynal /* New bindings with an IRQ for RX and TX (both UART) */
41695f78768SMiquel Raynal ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
41795f78768SMiquel Raynal mvebu_uart_rx_isr, port->irqflags,
41895f78768SMiquel Raynal dev_name(port->dev), port);
41995f78768SMiquel Raynal if (ret) {
42095f78768SMiquel Raynal dev_err(port->dev, "unable to request IRQ %d\n",
42195f78768SMiquel Raynal mvuart->irq[UART_RX_IRQ]);
42295f78768SMiquel Raynal return ret;
42395f78768SMiquel Raynal }
42495f78768SMiquel Raynal
42595f78768SMiquel Raynal ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
42695f78768SMiquel Raynal mvebu_uart_tx_isr, port->irqflags,
42795f78768SMiquel Raynal dev_name(port->dev),
42895f78768SMiquel Raynal port);
42995f78768SMiquel Raynal if (ret) {
43095f78768SMiquel Raynal dev_err(port->dev, "unable to request IRQ %d\n",
43195f78768SMiquel Raynal mvuart->irq[UART_TX_IRQ]);
43295f78768SMiquel Raynal devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
43395f78768SMiquel Raynal port);
43495f78768SMiquel Raynal return ret;
43595f78768SMiquel Raynal }
43695f78768SMiquel Raynal }
43730530791SWilson Ding
43830530791SWilson Ding return 0;
43930530791SWilson Ding }
44030530791SWilson Ding
mvebu_uart_shutdown(struct uart_port * port)44130530791SWilson Ding static void mvebu_uart_shutdown(struct uart_port *port)
44230530791SWilson Ding {
44395f78768SMiquel Raynal struct mvebu_uart *mvuart = to_mvuart(port);
44495f78768SMiquel Raynal
4455218d769SMiquel Raynal writel(0, port->membase + UART_INTR(port));
446c2c1659bSThomas Petazzoni
44795f78768SMiquel Raynal if (!mvuart->irq[UART_TX_IRQ]) {
44895f78768SMiquel Raynal devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
44995f78768SMiquel Raynal } else {
45095f78768SMiquel Raynal devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
45195f78768SMiquel Raynal devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
45295f78768SMiquel Raynal }
45330530791SWilson Ding }
45430530791SWilson Ding
mvebu_uart_baud_rate_set(struct uart_port * port,unsigned int baud)4554f532c1eSPali Rohár static unsigned int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
45668a0db1dSAllen Yan {
4570e4cf69eSMiquel Raynal unsigned int d_divisor, m_divisor;
458b7e2b536SPali Rohár unsigned long flags;
45935d7a58aSMiquel Raynal u32 brdv, osamp;
46068a0db1dSAllen Yan
461ecd6b010SPali Rohár if (!port->uartclk)
4624f532c1eSPali Rohár return 0;
46368a0db1dSAllen Yan
46468a0db1dSAllen Yan /*
465694b7112SPali Rohár * The baudrate is derived from the UART clock thanks to divisors:
466694b7112SPali Rohár * > d1 * d2 ("TBG divisors"): can divide only TBG clock from 1 to 6
467694b7112SPali Rohár * > D ("baud generator"): can divide the clock from 1 to 1023
468694b7112SPali Rohár * > M ("fractional divisor"): allows a better accuracy (from 1 to 63)
4690e4cf69eSMiquel Raynal *
470694b7112SPali Rohár * Exact formulas for calculating baudrate:
471694b7112SPali Rohár *
472694b7112SPali Rohár * with default x16 scheme:
473694b7112SPali Rohár * baudrate = xtal / (d * 16)
474694b7112SPali Rohár * baudrate = tbg / (d1 * d2 * d * 16)
475694b7112SPali Rohár *
476694b7112SPali Rohár * with fractional divisor:
477694b7112SPali Rohár * baudrate = 10 * xtal / (d * (3 * (m1 + m2) + 2 * (m3 + m4)))
478694b7112SPali Rohár * baudrate = 10 * tbg / (d1*d2 * d * (3 * (m1 + m2) + 2 * (m3 + m4)))
479694b7112SPali Rohár *
480694b7112SPali Rohár * Oversampling value:
481694b7112SPali Rohár * osamp = (m1 << 0) | (m2 << 8) | (m3 << 16) | (m4 << 24);
482694b7112SPali Rohár *
483694b7112SPali Rohár * Where m1 controls number of clock cycles per bit for bits 1,2,3;
484694b7112SPali Rohár * m2 for bits 4,5,6; m3 for bits 7,8 and m4 for bits 9,10.
485694b7112SPali Rohár *
486694b7112SPali Rohár * To simplify baudrate setup set all the M prescalers to the same
487694b7112SPali Rohár * value. For baudrates 9600 Bd and higher, it is enough to use the
488694b7112SPali Rohár * default (x16) divisor or fractional divisor with M = 63, so there
489694b7112SPali Rohár * is no need to use real fractional support (where the M prescalers
490694b7112SPali Rohár * are not equal).
491694b7112SPali Rohár *
492694b7112SPali Rohár * When all the M prescalers are zeroed then default (x16) divisor is
493694b7112SPali Rohár * used. Default x16 scheme is more stable than M (fractional divisor),
494694b7112SPali Rohár * so use M only when D divisor is not enough to derive baudrate.
495694b7112SPali Rohár *
496694b7112SPali Rohár * Member port->uartclk is either xtal clock rate or TBG clock rate
497694b7112SPali Rohár * divided by (d1 * d2). So d1 and d2 are already set by the UART clock
498694b7112SPali Rohár * driver (and UART driver itself cannot change them). Moreover they are
499694b7112SPali Rohár * shared between both UARTs.
50068a0db1dSAllen Yan */
501694b7112SPali Rohár
5020e4cf69eSMiquel Raynal m_divisor = OSAMP_DEFAULT_DIVISOR;
5039078204cSPali Rohár d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
5040e4cf69eSMiquel Raynal
505694b7112SPali Rohár if (d_divisor > BRDV_BAUD_MAX) {
506694b7112SPali Rohár /*
507694b7112SPali Rohár * Experiments show that small M divisors are unstable.
508694b7112SPali Rohár * Use maximal possible M = 63 and calculate D divisor.
509694b7112SPali Rohár */
510694b7112SPali Rohár m_divisor = OSAMP_MAX_DIVISOR;
511694b7112SPali Rohár d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor);
512694b7112SPali Rohár }
513694b7112SPali Rohár
514694b7112SPali Rohár if (d_divisor < 1)
515694b7112SPali Rohár d_divisor = 1;
516694b7112SPali Rohár else if (d_divisor > BRDV_BAUD_MAX)
517694b7112SPali Rohár d_divisor = BRDV_BAUD_MAX;
518694b7112SPali Rohár
519b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags);
52068a0db1dSAllen Yan brdv = readl(port->membase + UART_BRDV);
52168a0db1dSAllen Yan brdv &= ~BRDV_BAUD_MASK;
5220e4cf69eSMiquel Raynal brdv |= d_divisor;
52368a0db1dSAllen Yan writel(brdv, port->membase + UART_BRDV);
524b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags);
52568a0db1dSAllen Yan
52635d7a58aSMiquel Raynal osamp = readl(port->membase + UART_OSAMP);
52735d7a58aSMiquel Raynal osamp &= ~OSAMP_DIVISORS_MASK;
528694b7112SPali Rohár if (m_divisor != OSAMP_DEFAULT_DIVISOR)
529694b7112SPali Rohár osamp |= (m_divisor << 0) | (m_divisor << 8) |
530694b7112SPali Rohár (m_divisor << 16) | (m_divisor << 24);
53135d7a58aSMiquel Raynal writel(osamp, port->membase + UART_OSAMP);
53235d7a58aSMiquel Raynal
5334f532c1eSPali Rohár return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor);
53468a0db1dSAllen Yan }
53568a0db1dSAllen Yan
mvebu_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)53630530791SWilson Ding static void mvebu_uart_set_termios(struct uart_port *port,
53730530791SWilson Ding struct ktermios *termios,
538bec5b814SIlpo Järvinen const struct ktermios *old)
53930530791SWilson Ding {
54030530791SWilson Ding unsigned long flags;
541deeaf963SPali Rohár unsigned int baud, min_baud, max_baud;
54230530791SWilson Ding
54330530791SWilson Ding spin_lock_irqsave(&port->lock, flags);
54430530791SWilson Ding
5455218d769SMiquel Raynal port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
5465218d769SMiquel Raynal STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
54730530791SWilson Ding
54830530791SWilson Ding if (termios->c_iflag & INPCK)
54930530791SWilson Ding port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
55030530791SWilson Ding
55130530791SWilson Ding port->ignore_status_mask = 0;
55230530791SWilson Ding if (termios->c_iflag & IGNPAR)
55330530791SWilson Ding port->ignore_status_mask |=
55430530791SWilson Ding STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
55530530791SWilson Ding
55630530791SWilson Ding if ((termios->c_cflag & CREAD) == 0)
5575218d769SMiquel Raynal port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
55830530791SWilson Ding
55968a0db1dSAllen Yan /*
560694b7112SPali Rohár * Maximal divisor is 1023 and maximal fractional divisor is 63. And
561694b7112SPali Rohár * experiments show that baudrates above 1/80 of parent clock rate are
562694b7112SPali Rohár * not stable. So disallow baudrates above 1/80 of the parent clock
563694b7112SPali Rohár * rate. If port->uartclk is not available, then
564694b7112SPali Rohár * mvebu_uart_baud_rate_set() fails, so values min_baud and max_baud
565694b7112SPali Rohár * in this case do not matter.
56668a0db1dSAllen Yan */
567694b7112SPali Rohár min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX *
568694b7112SPali Rohár OSAMP_MAX_DIVISOR);
569694b7112SPali Rohár max_baud = port->uartclk / 80;
570deeaf963SPali Rohár
571deeaf963SPali Rohár baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud);
5724f532c1eSPali Rohár baud = mvebu_uart_baud_rate_set(port, baud);
5734f532c1eSPali Rohár
5744f532c1eSPali Rohár /* In case baudrate cannot be changed, report previous old value */
5754f532c1eSPali Rohár if (baud == 0 && old)
5764f532c1eSPali Rohár baud = tty_termios_baud_rate(old);
57768a0db1dSAllen Yan
57868a0db1dSAllen Yan /* Only the following flag changes are supported */
57968a0db1dSAllen Yan if (old) {
58068a0db1dSAllen Yan termios->c_iflag &= INPCK | IGNPAR;
58168a0db1dSAllen Yan termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
58268a0db1dSAllen Yan termios->c_cflag &= CREAD | CBAUD;
58368a0db1dSAllen Yan termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
584e0bf2d49SJan Kiszka termios->c_cflag |= CS8;
58568a0db1dSAllen Yan }
58630530791SWilson Ding
5874f532c1eSPali Rohár if (baud != 0) {
5884f532c1eSPali Rohár tty_termios_encode_baud_rate(termios, baud, baud);
5894f532c1eSPali Rohár uart_update_timeout(port, termios->c_cflag, baud);
5904f532c1eSPali Rohár }
5914f532c1eSPali Rohár
59230530791SWilson Ding spin_unlock_irqrestore(&port->lock, flags);
59330530791SWilson Ding }
59430530791SWilson Ding
mvebu_uart_type(struct uart_port * port)59530530791SWilson Ding static const char *mvebu_uart_type(struct uart_port *port)
59630530791SWilson Ding {
59730530791SWilson Ding return MVEBU_UART_TYPE;
59830530791SWilson Ding }
59930530791SWilson Ding
mvebu_uart_release_port(struct uart_port * port)60030530791SWilson Ding static void mvebu_uart_release_port(struct uart_port *port)
60130530791SWilson Ding {
60230530791SWilson Ding /* Nothing to do here */
60330530791SWilson Ding }
60430530791SWilson Ding
mvebu_uart_request_port(struct uart_port * port)60530530791SWilson Ding static int mvebu_uart_request_port(struct uart_port *port)
60630530791SWilson Ding {
60730530791SWilson Ding return 0;
60830530791SWilson Ding }
60930530791SWilson Ding
61030530791SWilson Ding #ifdef CONFIG_CONSOLE_POLL
mvebu_uart_get_poll_char(struct uart_port * port)61130530791SWilson Ding static int mvebu_uart_get_poll_char(struct uart_port *port)
61230530791SWilson Ding {
61330530791SWilson Ding unsigned int st = readl(port->membase + UART_STAT);
61430530791SWilson Ding
6155218d769SMiquel Raynal if (!(st & STAT_RX_RDY(port)))
61630530791SWilson Ding return NO_POLL_CHAR;
61730530791SWilson Ding
6185218d769SMiquel Raynal return readl(port->membase + UART_RBR(port));
61930530791SWilson Ding }
62030530791SWilson Ding
mvebu_uart_put_poll_char(struct uart_port * port,unsigned char c)62130530791SWilson Ding static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
62230530791SWilson Ding {
62330530791SWilson Ding unsigned int st;
62430530791SWilson Ding
62530530791SWilson Ding for (;;) {
62630530791SWilson Ding st = readl(port->membase + UART_STAT);
62730530791SWilson Ding
62830530791SWilson Ding if (!(st & STAT_TX_FIFO_FUL))
62930530791SWilson Ding break;
63030530791SWilson Ding
63130530791SWilson Ding udelay(1);
63230530791SWilson Ding }
63330530791SWilson Ding
6345218d769SMiquel Raynal writel(c, port->membase + UART_TSH(port));
63530530791SWilson Ding }
63630530791SWilson Ding #endif
63730530791SWilson Ding
63830530791SWilson Ding static const struct uart_ops mvebu_uart_ops = {
63930530791SWilson Ding .tx_empty = mvebu_uart_tx_empty,
64030530791SWilson Ding .set_mctrl = mvebu_uart_set_mctrl,
64130530791SWilson Ding .get_mctrl = mvebu_uart_get_mctrl,
64230530791SWilson Ding .stop_tx = mvebu_uart_stop_tx,
64330530791SWilson Ding .start_tx = mvebu_uart_start_tx,
64430530791SWilson Ding .stop_rx = mvebu_uart_stop_rx,
64530530791SWilson Ding .break_ctl = mvebu_uart_break_ctl,
64630530791SWilson Ding .startup = mvebu_uart_startup,
64730530791SWilson Ding .shutdown = mvebu_uart_shutdown,
64830530791SWilson Ding .set_termios = mvebu_uart_set_termios,
64930530791SWilson Ding .type = mvebu_uart_type,
65030530791SWilson Ding .release_port = mvebu_uart_release_port,
65130530791SWilson Ding .request_port = mvebu_uart_request_port,
65230530791SWilson Ding #ifdef CONFIG_CONSOLE_POLL
65330530791SWilson Ding .poll_get_char = mvebu_uart_get_poll_char,
65430530791SWilson Ding .poll_put_char = mvebu_uart_put_poll_char,
65530530791SWilson Ding #endif
65630530791SWilson Ding };
65730530791SWilson Ding
65830530791SWilson Ding /* Console Driver Operations */
65930530791SWilson Ding
66030530791SWilson Ding #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
66130530791SWilson Ding /* Early Console */
mvebu_uart_putc(struct uart_port * port,unsigned char c)6623f8bab17SJiri Slaby static void mvebu_uart_putc(struct uart_port *port, unsigned char c)
66330530791SWilson Ding {
66430530791SWilson Ding unsigned int st;
66530530791SWilson Ding
66630530791SWilson Ding for (;;) {
66730530791SWilson Ding st = readl(port->membase + UART_STAT);
66830530791SWilson Ding if (!(st & STAT_TX_FIFO_FUL))
66930530791SWilson Ding break;
67030530791SWilson Ding }
67130530791SWilson Ding
6725218d769SMiquel Raynal /* At early stage, DT is not parsed yet, only use UART0 */
6735218d769SMiquel Raynal writel(c, port->membase + UART_STD_TSH);
67430530791SWilson Ding
67530530791SWilson Ding for (;;) {
67630530791SWilson Ding st = readl(port->membase + UART_STAT);
67730530791SWilson Ding if (st & STAT_TX_FIFO_EMP)
67830530791SWilson Ding break;
67930530791SWilson Ding }
68030530791SWilson Ding }
68130530791SWilson Ding
mvebu_uart_putc_early_write(struct console * con,const char * s,unsigned int n)68230530791SWilson Ding static void mvebu_uart_putc_early_write(struct console *con,
68330530791SWilson Ding const char *s,
6845607fa6cSJinchao Wang unsigned int n)
68530530791SWilson Ding {
68630530791SWilson Ding struct earlycon_device *dev = con->data;
68730530791SWilson Ding
68830530791SWilson Ding uart_console_write(&dev->port, s, n, mvebu_uart_putc);
68930530791SWilson Ding }
69030530791SWilson Ding
69130530791SWilson Ding static int __init
mvebu_uart_early_console_setup(struct earlycon_device * device,const char * opt)69230530791SWilson Ding mvebu_uart_early_console_setup(struct earlycon_device *device,
69330530791SWilson Ding const char *opt)
69430530791SWilson Ding {
69530530791SWilson Ding if (!device->port.membase)
69630530791SWilson Ding return -ENODEV;
69730530791SWilson Ding
69830530791SWilson Ding device->con->write = mvebu_uart_putc_early_write;
69930530791SWilson Ding
70030530791SWilson Ding return 0;
70130530791SWilson Ding }
70230530791SWilson Ding
70330530791SWilson Ding EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
70430530791SWilson Ding OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
70530530791SWilson Ding mvebu_uart_early_console_setup);
70630530791SWilson Ding
wait_for_xmitr(struct uart_port * port)70730530791SWilson Ding static void wait_for_xmitr(struct uart_port *port)
70830530791SWilson Ding {
70930530791SWilson Ding u32 val;
71030530791SWilson Ding
71130530791SWilson Ding readl_poll_timeout_atomic(port->membase + UART_STAT, val,
712c685af11SGabriel Matni (val & STAT_TX_RDY(port)), 1, 10000);
71330530791SWilson Ding }
71430530791SWilson Ding
wait_for_xmite(struct uart_port * port)71554ca955bSPali Rohár static void wait_for_xmite(struct uart_port *port)
71654ca955bSPali Rohár {
71754ca955bSPali Rohár u32 val;
71854ca955bSPali Rohár
71954ca955bSPali Rohár readl_poll_timeout_atomic(port->membase + UART_STAT, val,
72054ca955bSPali Rohár (val & STAT_TX_EMP), 1, 10000);
72154ca955bSPali Rohár }
72254ca955bSPali Rohár
mvebu_uart_console_putchar(struct uart_port * port,unsigned char ch)7233f8bab17SJiri Slaby static void mvebu_uart_console_putchar(struct uart_port *port, unsigned char ch)
72430530791SWilson Ding {
72530530791SWilson Ding wait_for_xmitr(port);
7265218d769SMiquel Raynal writel(ch, port->membase + UART_TSH(port));
72730530791SWilson Ding }
72830530791SWilson Ding
mvebu_uart_console_write(struct console * co,const char * s,unsigned int count)72930530791SWilson Ding static void mvebu_uart_console_write(struct console *co, const char *s,
73030530791SWilson Ding unsigned int count)
73130530791SWilson Ding {
73230530791SWilson Ding struct uart_port *port = &mvebu_uart_ports[co->index];
73330530791SWilson Ding unsigned long flags;
7345218d769SMiquel Raynal unsigned int ier, intr, ctl;
73530530791SWilson Ding int locked = 1;
73630530791SWilson Ding
73730530791SWilson Ding if (oops_in_progress)
73830530791SWilson Ding locked = spin_trylock_irqsave(&port->lock, flags);
73930530791SWilson Ding else
74030530791SWilson Ding spin_lock_irqsave(&port->lock, flags);
74130530791SWilson Ding
7425218d769SMiquel Raynal ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
7435218d769SMiquel Raynal intr = readl(port->membase + UART_INTR(port)) &
7445218d769SMiquel Raynal (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
7455218d769SMiquel Raynal writel(0, port->membase + UART_CTRL(port));
7465218d769SMiquel Raynal writel(0, port->membase + UART_INTR(port));
74730530791SWilson Ding
74830530791SWilson Ding uart_console_write(port, s, count, mvebu_uart_console_putchar);
74930530791SWilson Ding
75054ca955bSPali Rohár wait_for_xmite(port);
75130530791SWilson Ding
75230530791SWilson Ding if (ier)
7535218d769SMiquel Raynal writel(ier, port->membase + UART_CTRL(port));
7545218d769SMiquel Raynal
7555218d769SMiquel Raynal if (intr) {
7565218d769SMiquel Raynal ctl = intr | readl(port->membase + UART_INTR(port));
7575218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port));
7585218d769SMiquel Raynal }
75930530791SWilson Ding
76030530791SWilson Ding if (locked)
76130530791SWilson Ding spin_unlock_irqrestore(&port->lock, flags);
76230530791SWilson Ding }
76330530791SWilson Ding
mvebu_uart_console_setup(struct console * co,char * options)76430530791SWilson Ding static int mvebu_uart_console_setup(struct console *co, char *options)
76530530791SWilson Ding {
76630530791SWilson Ding struct uart_port *port;
76730530791SWilson Ding int baud = 9600;
76830530791SWilson Ding int bits = 8;
76930530791SWilson Ding int parity = 'n';
77030530791SWilson Ding int flow = 'n';
77130530791SWilson Ding
77230530791SWilson Ding if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
77330530791SWilson Ding return -EINVAL;
77430530791SWilson Ding
77530530791SWilson Ding port = &mvebu_uart_ports[co->index];
77630530791SWilson Ding
77730530791SWilson Ding if (!port->mapbase || !port->membase) {
77830530791SWilson Ding pr_debug("console on ttyMV%i not present\n", co->index);
77930530791SWilson Ding return -ENODEV;
78030530791SWilson Ding }
78130530791SWilson Ding
78230530791SWilson Ding if (options)
78330530791SWilson Ding uart_parse_options(options, &baud, &parity, &bits, &flow);
78430530791SWilson Ding
78530530791SWilson Ding return uart_set_options(port, co, baud, parity, bits, flow);
78630530791SWilson Ding }
78730530791SWilson Ding
78830530791SWilson Ding static struct uart_driver mvebu_uart_driver;
78930530791SWilson Ding
79030530791SWilson Ding static struct console mvebu_uart_console = {
79130530791SWilson Ding .name = "ttyMV",
79230530791SWilson Ding .write = mvebu_uart_console_write,
79330530791SWilson Ding .device = uart_console_device,
79430530791SWilson Ding .setup = mvebu_uart_console_setup,
79530530791SWilson Ding .flags = CON_PRINTBUFFER,
79630530791SWilson Ding .index = -1,
79730530791SWilson Ding .data = &mvebu_uart_driver,
79830530791SWilson Ding };
79930530791SWilson Ding
mvebu_uart_console_init(void)80030530791SWilson Ding static int __init mvebu_uart_console_init(void)
80130530791SWilson Ding {
80230530791SWilson Ding register_console(&mvebu_uart_console);
80330530791SWilson Ding return 0;
80430530791SWilson Ding }
80530530791SWilson Ding
80630530791SWilson Ding console_initcall(mvebu_uart_console_init);
80730530791SWilson Ding
80830530791SWilson Ding
80930530791SWilson Ding #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
81030530791SWilson Ding
81130530791SWilson Ding static struct uart_driver mvebu_uart_driver = {
81230530791SWilson Ding .owner = THIS_MODULE,
81302c33330SYehuda Yitschak .driver_name = DRIVER_NAME,
81430530791SWilson Ding .dev_name = "ttyMV",
81530530791SWilson Ding .nr = MVEBU_NR_UARTS,
81630530791SWilson Ding #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
81730530791SWilson Ding .cons = &mvebu_uart_console,
81830530791SWilson Ding #endif
81930530791SWilson Ding };
82030530791SWilson Ding
821394e8351SMiquel Raynal #if defined(CONFIG_PM)
mvebu_uart_suspend(struct device * dev)822394e8351SMiquel Raynal static int mvebu_uart_suspend(struct device *dev)
823394e8351SMiquel Raynal {
824394e8351SMiquel Raynal struct mvebu_uart *mvuart = dev_get_drvdata(dev);
825394e8351SMiquel Raynal struct uart_port *port = mvuart->port;
826b7e2b536SPali Rohár unsigned long flags;
827394e8351SMiquel Raynal
828394e8351SMiquel Raynal uart_suspend_port(&mvebu_uart_driver, port);
829394e8351SMiquel Raynal
830394e8351SMiquel Raynal mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
831394e8351SMiquel Raynal mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
832394e8351SMiquel Raynal mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
833394e8351SMiquel Raynal mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
834394e8351SMiquel Raynal mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
835b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags);
836394e8351SMiquel Raynal mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
837b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags);
838394e8351SMiquel Raynal mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
839394e8351SMiquel Raynal
840394e8351SMiquel Raynal device_set_wakeup_enable(dev, true);
841394e8351SMiquel Raynal
842394e8351SMiquel Raynal return 0;
843394e8351SMiquel Raynal }
844394e8351SMiquel Raynal
mvebu_uart_resume(struct device * dev)845394e8351SMiquel Raynal static int mvebu_uart_resume(struct device *dev)
846394e8351SMiquel Raynal {
847394e8351SMiquel Raynal struct mvebu_uart *mvuart = dev_get_drvdata(dev);
848394e8351SMiquel Raynal struct uart_port *port = mvuart->port;
849b7e2b536SPali Rohár unsigned long flags;
850394e8351SMiquel Raynal
851394e8351SMiquel Raynal writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
852394e8351SMiquel Raynal writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
853394e8351SMiquel Raynal writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
854394e8351SMiquel Raynal writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
855394e8351SMiquel Raynal writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
856b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags);
857394e8351SMiquel Raynal writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
858b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags);
859394e8351SMiquel Raynal writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
860394e8351SMiquel Raynal
861394e8351SMiquel Raynal uart_resume_port(&mvebu_uart_driver, port);
862394e8351SMiquel Raynal
863394e8351SMiquel Raynal return 0;
864394e8351SMiquel Raynal }
865394e8351SMiquel Raynal
866394e8351SMiquel Raynal static const struct dev_pm_ops mvebu_uart_pm_ops = {
867394e8351SMiquel Raynal .suspend = mvebu_uart_suspend,
868394e8351SMiquel Raynal .resume = mvebu_uart_resume,
869394e8351SMiquel Raynal };
870394e8351SMiquel Raynal #endif /* CONFIG_PM */
871394e8351SMiquel Raynal
8725218d769SMiquel Raynal static const struct of_device_id mvebu_uart_of_match[];
8735218d769SMiquel Raynal
87494228f95SAllen Yan /* Counter to keep track of each UART port id when not using CONFIG_OF */
87594228f95SAllen Yan static int uart_num_counter;
87694228f95SAllen Yan
mvebu_uart_probe(struct platform_device * pdev)87730530791SWilson Ding static int mvebu_uart_probe(struct platform_device *pdev)
87830530791SWilson Ding {
8795218d769SMiquel Raynal const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
8805218d769SMiquel Raynal &pdev->dev);
88130530791SWilson Ding struct uart_port *port;
8825218d769SMiquel Raynal struct mvebu_uart *mvuart;
883*ffd793ebSYangtao Li struct resource *reg;
88458e49346SQinglang Miao int id, irq;
88530530791SWilson Ding
88694228f95SAllen Yan /* Assume that all UART ports have a DT alias or none has */
88794228f95SAllen Yan id = of_alias_get_id(pdev->dev.of_node, "serial");
88894228f95SAllen Yan if (!pdev->dev.of_node || id < 0)
88994228f95SAllen Yan pdev->id = uart_num_counter++;
89094228f95SAllen Yan else
89194228f95SAllen Yan pdev->id = id;
89294228f95SAllen Yan
89394228f95SAllen Yan if (pdev->id >= MVEBU_NR_UARTS) {
89494228f95SAllen Yan dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
89594228f95SAllen Yan MVEBU_NR_UARTS);
89694228f95SAllen Yan return -EINVAL;
89794228f95SAllen Yan }
89894228f95SAllen Yan
89994228f95SAllen Yan port = &mvebu_uart_ports[pdev->id];
90030530791SWilson Ding
90130530791SWilson Ding spin_lock_init(&port->lock);
90230530791SWilson Ding
90330530791SWilson Ding port->dev = &pdev->dev;
90430530791SWilson Ding port->type = PORT_MVEBU;
90530530791SWilson Ding port->ops = &mvebu_uart_ops;
90630530791SWilson Ding port->regshift = 0;
90730530791SWilson Ding
90830530791SWilson Ding port->fifosize = 32;
90930530791SWilson Ding port->iotype = UPIO_MEM32;
91030530791SWilson Ding port->flags = UPF_FIXED_PORT;
91194228f95SAllen Yan port->line = pdev->id;
91230530791SWilson Ding
91395f78768SMiquel Raynal /*
91495f78768SMiquel Raynal * IRQ number is not stored in this structure because we may have two of
91595f78768SMiquel Raynal * them per port (RX and TX). Instead, use the driver UART structure
91695f78768SMiquel Raynal * array so called ->irq[].
91795f78768SMiquel Raynal */
91895f78768SMiquel Raynal port->irq = 0;
91930530791SWilson Ding port->irqflags = 0;
92030530791SWilson Ding
921*ffd793ebSYangtao Li port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, ®);
92230530791SWilson Ding if (IS_ERR(port->membase))
9234a3e2084Stangbin return PTR_ERR(port->membase);
924*ffd793ebSYangtao Li port->mapbase = reg->start;
92530530791SWilson Ding
9265218d769SMiquel Raynal mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
92730530791SWilson Ding GFP_KERNEL);
9285218d769SMiquel Raynal if (!mvuart)
92930530791SWilson Ding return -ENOMEM;
93030530791SWilson Ding
93168a0db1dSAllen Yan /* Get controller data depending on the compatible string */
9325218d769SMiquel Raynal mvuart->data = (struct mvebu_uart_driver_data *)match->data;
9335218d769SMiquel Raynal mvuart->port = port;
93430530791SWilson Ding
9355218d769SMiquel Raynal port->private_data = mvuart;
9365218d769SMiquel Raynal platform_set_drvdata(pdev, mvuart);
93730530791SWilson Ding
93868a0db1dSAllen Yan /* Get fixed clock frequency */
93968a0db1dSAllen Yan mvuart->clk = devm_clk_get(&pdev->dev, NULL);
94068a0db1dSAllen Yan if (IS_ERR(mvuart->clk)) {
94168a0db1dSAllen Yan if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
94268a0db1dSAllen Yan return PTR_ERR(mvuart->clk);
94368a0db1dSAllen Yan
94468a0db1dSAllen Yan if (IS_EXTENDED(port)) {
94568a0db1dSAllen Yan dev_err(&pdev->dev, "unable to get UART clock\n");
94668a0db1dSAllen Yan return PTR_ERR(mvuart->clk);
94768a0db1dSAllen Yan }
94868a0db1dSAllen Yan } else {
94968a0db1dSAllen Yan if (!clk_prepare_enable(mvuart->clk))
95068a0db1dSAllen Yan port->uartclk = clk_get_rate(mvuart->clk);
95168a0db1dSAllen Yan }
95268a0db1dSAllen Yan
95395f78768SMiquel Raynal /* Manage interrupts */
95495f78768SMiquel Raynal if (platform_irq_count(pdev) == 1) {
95595f78768SMiquel Raynal /* Old bindings: no name on the single unamed UART0 IRQ */
95695f78768SMiquel Raynal irq = platform_get_irq(pdev, 0);
9571df21786SStephen Boyd if (irq < 0)
95895f78768SMiquel Raynal return irq;
95995f78768SMiquel Raynal
96095f78768SMiquel Raynal mvuart->irq[UART_IRQ_SUM] = irq;
96195f78768SMiquel Raynal } else {
96295f78768SMiquel Raynal /*
96395f78768SMiquel Raynal * New bindings: named interrupts (RX, TX) for both UARTS,
96495f78768SMiquel Raynal * only make use of uart-rx and uart-tx interrupts, do not use
96595f78768SMiquel Raynal * uart-sum of UART0 port.
96695f78768SMiquel Raynal */
96795f78768SMiquel Raynal irq = platform_get_irq_byname(pdev, "uart-rx");
9681df21786SStephen Boyd if (irq < 0)
96995f78768SMiquel Raynal return irq;
97095f78768SMiquel Raynal
97195f78768SMiquel Raynal mvuart->irq[UART_RX_IRQ] = irq;
97295f78768SMiquel Raynal
97395f78768SMiquel Raynal irq = platform_get_irq_byname(pdev, "uart-tx");
9741df21786SStephen Boyd if (irq < 0)
97595f78768SMiquel Raynal return irq;
97695f78768SMiquel Raynal
97795f78768SMiquel Raynal mvuart->irq[UART_TX_IRQ] = irq;
97895f78768SMiquel Raynal }
97995f78768SMiquel Raynal
9809c3d3ee1SAllen Yan /* UART Soft Reset*/
9819c3d3ee1SAllen Yan writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
9829c3d3ee1SAllen Yan udelay(1);
9839c3d3ee1SAllen Yan writel(0, port->membase + UART_CTRL(port));
9849c3d3ee1SAllen Yan
985b6353702SQinglang Miao return uart_add_one_port(&mvebu_uart_driver, port);
98630530791SWilson Ding }
98730530791SWilson Ding
9885218d769SMiquel Raynal static struct mvebu_uart_driver_data uart_std_driver_data = {
9895218d769SMiquel Raynal .is_ext = false,
9905218d769SMiquel Raynal .regs.rbr = UART_STD_RBR,
9915218d769SMiquel Raynal .regs.tsh = UART_STD_TSH,
9925218d769SMiquel Raynal .regs.ctrl = UART_STD_CTRL1,
9935218d769SMiquel Raynal .regs.intr = UART_STD_CTRL2,
9945218d769SMiquel Raynal .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
9955218d769SMiquel Raynal .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
9965218d769SMiquel Raynal .flags.stat_tx_rdy = STAT_STD_TX_RDY,
9975218d769SMiquel Raynal .flags.stat_rx_rdy = STAT_STD_RX_RDY,
9985218d769SMiquel Raynal };
9995218d769SMiquel Raynal
100053501e02SMiquel Raynal static struct mvebu_uart_driver_data uart_ext_driver_data = {
100153501e02SMiquel Raynal .is_ext = true,
100253501e02SMiquel Raynal .regs.rbr = UART_EXT_RBR,
100353501e02SMiquel Raynal .regs.tsh = UART_EXT_TSH,
100453501e02SMiquel Raynal .regs.ctrl = UART_EXT_CTRL1,
100553501e02SMiquel Raynal .regs.intr = UART_EXT_CTRL2,
100653501e02SMiquel Raynal .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
100753501e02SMiquel Raynal .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
100853501e02SMiquel Raynal .flags.stat_tx_rdy = STAT_EXT_TX_RDY,
100953501e02SMiquel Raynal .flags.stat_rx_rdy = STAT_EXT_RX_RDY,
101053501e02SMiquel Raynal };
101153501e02SMiquel Raynal
101230530791SWilson Ding /* Match table for of_platform binding */
101330530791SWilson Ding static const struct of_device_id mvebu_uart_of_match[] = {
10145218d769SMiquel Raynal {
10155218d769SMiquel Raynal .compatible = "marvell,armada-3700-uart",
10165218d769SMiquel Raynal .data = (void *)&uart_std_driver_data,
10175218d769SMiquel Raynal },
101853501e02SMiquel Raynal {
101953501e02SMiquel Raynal .compatible = "marvell,armada-3700-uart-ext",
102053501e02SMiquel Raynal .data = (void *)&uart_ext_driver_data,
102153501e02SMiquel Raynal },
102230530791SWilson Ding {}
102330530791SWilson Ding };
102430530791SWilson Ding
102530530791SWilson Ding static struct platform_driver mvebu_uart_platform_driver = {
102630530791SWilson Ding .probe = mvebu_uart_probe,
102730530791SWilson Ding .driver = {
102830530791SWilson Ding .name = "mvebu-uart",
102930530791SWilson Ding .of_match_table = of_match_ptr(mvebu_uart_of_match),
103089ebc274SPaul Gortmaker .suppress_bind_attrs = true,
1031394e8351SMiquel Raynal #if defined(CONFIG_PM)
1032394e8351SMiquel Raynal .pm = &mvebu_uart_pm_ops,
1033394e8351SMiquel Raynal #endif /* CONFIG_PM */
103430530791SWilson Ding },
103530530791SWilson Ding };
103630530791SWilson Ding
1037b7e2b536SPali Rohár /* This code is based on clk-fixed-factor.c driver and modified. */
1038b7e2b536SPali Rohár
1039b7e2b536SPali Rohár struct mvebu_uart_clock {
1040b7e2b536SPali Rohár struct clk_hw clk_hw;
1041b7e2b536SPali Rohár int clock_idx;
1042b7e2b536SPali Rohár u32 pm_context_reg1;
1043b7e2b536SPali Rohár u32 pm_context_reg2;
1044b7e2b536SPali Rohár };
1045b7e2b536SPali Rohár
1046b7e2b536SPali Rohár struct mvebu_uart_clock_base {
1047b7e2b536SPali Rohár struct mvebu_uart_clock clocks[2];
1048b7e2b536SPali Rohár unsigned int parent_rates[5];
1049b7e2b536SPali Rohár int parent_idx;
1050b7e2b536SPali Rohár unsigned int div;
1051b7e2b536SPali Rohár void __iomem *reg1;
1052b7e2b536SPali Rohár void __iomem *reg2;
1053b7e2b536SPali Rohár bool configured;
1054b7e2b536SPali Rohár };
1055b7e2b536SPali Rohár
1056b7e2b536SPali Rohár #define PARENT_CLOCK_XTAL 4
1057b7e2b536SPali Rohár
1058b7e2b536SPali Rohár #define to_uart_clock(hw) container_of(hw, struct mvebu_uart_clock, clk_hw)
1059b7e2b536SPali Rohár #define to_uart_clock_base(uart_clock) container_of(uart_clock, \
1060b7e2b536SPali Rohár struct mvebu_uart_clock_base, clocks[uart_clock->clock_idx])
1061b7e2b536SPali Rohár
mvebu_uart_clock_prepare(struct clk_hw * hw)1062b7e2b536SPali Rohár static int mvebu_uart_clock_prepare(struct clk_hw *hw)
1063b7e2b536SPali Rohár {
1064b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1065b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base =
1066b7e2b536SPali Rohár to_uart_clock_base(uart_clock);
1067b7e2b536SPali Rohár unsigned int prev_clock_idx, prev_clock_rate, prev_d1d2;
1068b7e2b536SPali Rohár unsigned int parent_clock_idx, parent_clock_rate;
1069b7e2b536SPali Rohár unsigned long flags;
1070b7e2b536SPali Rohár unsigned int d1, d2;
1071b7e2b536SPali Rohár u64 divisor;
1072b7e2b536SPali Rohár u32 val;
1073b7e2b536SPali Rohár
1074b7e2b536SPali Rohár /*
1075b7e2b536SPali Rohár * This function just reconfigures UART Clock Control register (located
1076b7e2b536SPali Rohár * in UART1 address space which controls both UART1 and UART2) to
1077b7e2b536SPali Rohár * selected UART base clock and recalculates current UART1/UART2
1078b7e2b536SPali Rohár * divisors in their address spaces, so that final baudrate will not be
1079b7e2b536SPali Rohár * changed by switching UART parent clock. This is required for
1080b7e2b536SPali Rohár * otherwise kernel's boot log stops working - we need to ensure that
1081b7e2b536SPali Rohár * UART baudrate does not change during this setup. It is a one time
1082b7e2b536SPali Rohár * operation, it will execute only once and set `configured` to true,
1083b7e2b536SPali Rohár * and be skipped on subsequent calls. Because this UART Clock Control
1084b7e2b536SPali Rohár * register (UART_BRDV) is shared between UART1 baudrate function,
1085b7e2b536SPali Rohár * UART1 clock selector and UART2 clock selector, every access to
1086b7e2b536SPali Rohár * UART_BRDV (reg1) needs to be protected by a lock.
1087b7e2b536SPali Rohár */
1088b7e2b536SPali Rohár
1089b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags);
1090b7e2b536SPali Rohár
1091b7e2b536SPali Rohár if (uart_clock_base->configured) {
1092b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1093b7e2b536SPali Rohár return 0;
1094b7e2b536SPali Rohár }
1095b7e2b536SPali Rohár
1096b7e2b536SPali Rohár parent_clock_idx = uart_clock_base->parent_idx;
1097b7e2b536SPali Rohár parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx];
1098b7e2b536SPali Rohár
1099b7e2b536SPali Rohár val = readl(uart_clock_base->reg1);
1100b7e2b536SPali Rohár
1101b7e2b536SPali Rohár if (uart_clock_base->div > CLK_TBG_DIV1_MAX) {
1102b7e2b536SPali Rohár d1 = CLK_TBG_DIV1_MAX;
1103b7e2b536SPali Rohár d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX;
1104b7e2b536SPali Rohár } else {
1105b7e2b536SPali Rohár d1 = uart_clock_base->div;
1106b7e2b536SPali Rohár d2 = 1;
1107b7e2b536SPali Rohár }
1108b7e2b536SPali Rohár
1109b7e2b536SPali Rohár if (val & CLK_NO_XTAL) {
1110b7e2b536SPali Rohár prev_clock_idx = (val >> CLK_TBG_SEL_SHIFT) & CLK_TBG_SEL_MASK;
1111b7e2b536SPali Rohár prev_d1d2 = ((val >> CLK_TBG_DIV1_SHIFT) & CLK_TBG_DIV1_MASK) *
1112b7e2b536SPali Rohár ((val >> CLK_TBG_DIV2_SHIFT) & CLK_TBG_DIV2_MASK);
1113b7e2b536SPali Rohár } else {
1114b7e2b536SPali Rohár prev_clock_idx = PARENT_CLOCK_XTAL;
1115b7e2b536SPali Rohár prev_d1d2 = 1;
1116b7e2b536SPali Rohár }
1117b7e2b536SPali Rohár
1118b7e2b536SPali Rohár /* Note that uart_clock_base->parent_rates[i] may not be available */
1119b7e2b536SPali Rohár prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx];
1120b7e2b536SPali Rohár
1121b7e2b536SPali Rohár /* Recalculate UART1 divisor so UART1 baudrate does not change */
1122b7e2b536SPali Rohár if (prev_clock_rate) {
1123b7e2b536SPali Rohár divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) *
1124b7e2b536SPali Rohár parent_clock_rate * prev_d1d2,
1125b7e2b536SPali Rohár prev_clock_rate * d1 * d2);
1126b7e2b536SPali Rohár if (divisor < 1)
1127b7e2b536SPali Rohár divisor = 1;
1128b7e2b536SPali Rohár else if (divisor > BRDV_BAUD_MAX)
1129b7e2b536SPali Rohár divisor = BRDV_BAUD_MAX;
1130b7e2b536SPali Rohár val = (val & ~BRDV_BAUD_MASK) | divisor;
1131b7e2b536SPali Rohár }
1132b7e2b536SPali Rohár
1133b7e2b536SPali Rohár if (parent_clock_idx != PARENT_CLOCK_XTAL) {
1134b7e2b536SPali Rohár /* Do not use XTAL, select TBG clock and TBG d1 * d2 divisors */
1135b7e2b536SPali Rohár val |= CLK_NO_XTAL;
1136b7e2b536SPali Rohár val &= ~(CLK_TBG_DIV1_MASK << CLK_TBG_DIV1_SHIFT);
1137b7e2b536SPali Rohár val |= d1 << CLK_TBG_DIV1_SHIFT;
1138b7e2b536SPali Rohár val &= ~(CLK_TBG_DIV2_MASK << CLK_TBG_DIV2_SHIFT);
1139b7e2b536SPali Rohár val |= d2 << CLK_TBG_DIV2_SHIFT;
1140b7e2b536SPali Rohár val &= ~(CLK_TBG_SEL_MASK << CLK_TBG_SEL_SHIFT);
1141b7e2b536SPali Rohár val |= parent_clock_idx << CLK_TBG_SEL_SHIFT;
1142b7e2b536SPali Rohár } else {
1143b7e2b536SPali Rohár /* Use XTAL, TBG bits are then ignored */
1144b7e2b536SPali Rohár val &= ~CLK_NO_XTAL;
1145b7e2b536SPali Rohár }
1146b7e2b536SPali Rohár
1147b7e2b536SPali Rohár writel(val, uart_clock_base->reg1);
1148b7e2b536SPali Rohár
1149b7e2b536SPali Rohár /* Recalculate UART2 divisor so UART2 baudrate does not change */
1150b7e2b536SPali Rohár if (prev_clock_rate) {
1151b7e2b536SPali Rohár val = readl(uart_clock_base->reg2);
1152b7e2b536SPali Rohár divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) *
1153b7e2b536SPali Rohár parent_clock_rate * prev_d1d2,
1154b7e2b536SPali Rohár prev_clock_rate * d1 * d2);
1155b7e2b536SPali Rohár if (divisor < 1)
1156b7e2b536SPali Rohár divisor = 1;
1157b7e2b536SPali Rohár else if (divisor > BRDV_BAUD_MAX)
1158b7e2b536SPali Rohár divisor = BRDV_BAUD_MAX;
1159b7e2b536SPali Rohár val = (val & ~BRDV_BAUD_MASK) | divisor;
1160b7e2b536SPali Rohár writel(val, uart_clock_base->reg2);
1161b7e2b536SPali Rohár }
1162b7e2b536SPali Rohár
1163b7e2b536SPali Rohár uart_clock_base->configured = true;
1164b7e2b536SPali Rohár
1165b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1166b7e2b536SPali Rohár
1167b7e2b536SPali Rohár return 0;
1168b7e2b536SPali Rohár }
1169b7e2b536SPali Rohár
mvebu_uart_clock_enable(struct clk_hw * hw)1170b7e2b536SPali Rohár static int mvebu_uart_clock_enable(struct clk_hw *hw)
1171b7e2b536SPali Rohár {
1172b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1173b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base =
1174b7e2b536SPali Rohár to_uart_clock_base(uart_clock);
1175b7e2b536SPali Rohár unsigned long flags;
1176b7e2b536SPali Rohár u32 val;
1177b7e2b536SPali Rohár
1178b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags);
1179b7e2b536SPali Rohár
1180b7e2b536SPali Rohár val = readl(uart_clock_base->reg1);
1181b7e2b536SPali Rohár
1182b7e2b536SPali Rohár if (uart_clock->clock_idx == 0)
1183b7e2b536SPali Rohár val &= ~UART1_CLK_DIS;
1184b7e2b536SPali Rohár else
1185b7e2b536SPali Rohár val &= ~UART2_CLK_DIS;
1186b7e2b536SPali Rohár
1187b7e2b536SPali Rohár writel(val, uart_clock_base->reg1);
1188b7e2b536SPali Rohár
1189b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1190b7e2b536SPali Rohár
1191b7e2b536SPali Rohár return 0;
1192b7e2b536SPali Rohár }
1193b7e2b536SPali Rohár
mvebu_uart_clock_disable(struct clk_hw * hw)1194b7e2b536SPali Rohár static void mvebu_uart_clock_disable(struct clk_hw *hw)
1195b7e2b536SPali Rohár {
1196b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1197b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base =
1198b7e2b536SPali Rohár to_uart_clock_base(uart_clock);
1199b7e2b536SPali Rohár unsigned long flags;
1200b7e2b536SPali Rohár u32 val;
1201b7e2b536SPali Rohár
1202b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags);
1203b7e2b536SPali Rohár
1204b7e2b536SPali Rohár val = readl(uart_clock_base->reg1);
1205b7e2b536SPali Rohár
1206b7e2b536SPali Rohár if (uart_clock->clock_idx == 0)
1207b7e2b536SPali Rohár val |= UART1_CLK_DIS;
1208b7e2b536SPali Rohár else
1209b7e2b536SPali Rohár val |= UART2_CLK_DIS;
1210b7e2b536SPali Rohár
1211b7e2b536SPali Rohár writel(val, uart_clock_base->reg1);
1212b7e2b536SPali Rohár
1213b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1214b7e2b536SPali Rohár }
1215b7e2b536SPali Rohár
mvebu_uart_clock_is_enabled(struct clk_hw * hw)1216b7e2b536SPali Rohár static int mvebu_uart_clock_is_enabled(struct clk_hw *hw)
1217b7e2b536SPali Rohár {
1218b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1219b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base =
1220b7e2b536SPali Rohár to_uart_clock_base(uart_clock);
1221b7e2b536SPali Rohár u32 val;
1222b7e2b536SPali Rohár
1223b7e2b536SPali Rohár val = readl(uart_clock_base->reg1);
1224b7e2b536SPali Rohár
1225b7e2b536SPali Rohár if (uart_clock->clock_idx == 0)
1226b7e2b536SPali Rohár return !(val & UART1_CLK_DIS);
1227b7e2b536SPali Rohár else
1228b7e2b536SPali Rohár return !(val & UART2_CLK_DIS);
1229b7e2b536SPali Rohár }
1230b7e2b536SPali Rohár
mvebu_uart_clock_save_context(struct clk_hw * hw)1231b7e2b536SPali Rohár static int mvebu_uart_clock_save_context(struct clk_hw *hw)
1232b7e2b536SPali Rohár {
1233b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1234b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base =
1235b7e2b536SPali Rohár to_uart_clock_base(uart_clock);
1236b7e2b536SPali Rohár unsigned long flags;
1237b7e2b536SPali Rohár
1238b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags);
1239b7e2b536SPali Rohár uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1);
1240b7e2b536SPali Rohár uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2);
1241b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1242b7e2b536SPali Rohár
1243b7e2b536SPali Rohár return 0;
1244b7e2b536SPali Rohár }
1245b7e2b536SPali Rohár
mvebu_uart_clock_restore_context(struct clk_hw * hw)1246b7e2b536SPali Rohár static void mvebu_uart_clock_restore_context(struct clk_hw *hw)
1247b7e2b536SPali Rohár {
1248b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1249b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base =
1250b7e2b536SPali Rohár to_uart_clock_base(uart_clock);
1251b7e2b536SPali Rohár unsigned long flags;
1252b7e2b536SPali Rohár
1253b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags);
1254b7e2b536SPali Rohár writel(uart_clock->pm_context_reg1, uart_clock_base->reg1);
1255b7e2b536SPali Rohár writel(uart_clock->pm_context_reg2, uart_clock_base->reg2);
1256b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags);
1257b7e2b536SPali Rohár }
1258b7e2b536SPali Rohár
mvebu_uart_clock_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1259b7e2b536SPali Rohár static unsigned long mvebu_uart_clock_recalc_rate(struct clk_hw *hw,
1260b7e2b536SPali Rohár unsigned long parent_rate)
1261b7e2b536SPali Rohár {
1262b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1263b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base =
1264b7e2b536SPali Rohár to_uart_clock_base(uart_clock);
1265b7e2b536SPali Rohár
1266b7e2b536SPali Rohár return parent_rate / uart_clock_base->div;
1267b7e2b536SPali Rohár }
1268b7e2b536SPali Rohár
mvebu_uart_clock_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)1269b7e2b536SPali Rohár static long mvebu_uart_clock_round_rate(struct clk_hw *hw, unsigned long rate,
1270b7e2b536SPali Rohár unsigned long *parent_rate)
1271b7e2b536SPali Rohár {
1272b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw);
1273b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base =
1274b7e2b536SPali Rohár to_uart_clock_base(uart_clock);
1275b7e2b536SPali Rohár
1276b7e2b536SPali Rohár return *parent_rate / uart_clock_base->div;
1277b7e2b536SPali Rohár }
1278b7e2b536SPali Rohár
mvebu_uart_clock_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1279b7e2b536SPali Rohár static int mvebu_uart_clock_set_rate(struct clk_hw *hw, unsigned long rate,
1280b7e2b536SPali Rohár unsigned long parent_rate)
1281b7e2b536SPali Rohár {
1282b7e2b536SPali Rohár /*
1283b7e2b536SPali Rohár * We must report success but we can do so unconditionally because
1284b7e2b536SPali Rohár * mvebu_uart_clock_round_rate returns values that ensure this call is a
1285b7e2b536SPali Rohár * nop.
1286b7e2b536SPali Rohár */
1287b7e2b536SPali Rohár
1288b7e2b536SPali Rohár return 0;
1289b7e2b536SPali Rohár }
1290b7e2b536SPali Rohár
1291b7e2b536SPali Rohár static const struct clk_ops mvebu_uart_clock_ops = {
1292b7e2b536SPali Rohár .prepare = mvebu_uart_clock_prepare,
1293b7e2b536SPali Rohár .enable = mvebu_uart_clock_enable,
1294b7e2b536SPali Rohár .disable = mvebu_uart_clock_disable,
1295b7e2b536SPali Rohár .is_enabled = mvebu_uart_clock_is_enabled,
1296b7e2b536SPali Rohár .save_context = mvebu_uart_clock_save_context,
1297b7e2b536SPali Rohár .restore_context = mvebu_uart_clock_restore_context,
1298b7e2b536SPali Rohár .round_rate = mvebu_uart_clock_round_rate,
1299b7e2b536SPali Rohár .set_rate = mvebu_uart_clock_set_rate,
1300b7e2b536SPali Rohár .recalc_rate = mvebu_uart_clock_recalc_rate,
1301b7e2b536SPali Rohár };
1302b7e2b536SPali Rohár
mvebu_uart_clock_register(struct device * dev,struct mvebu_uart_clock * uart_clock,const char * name,const char * parent_name)1303b7e2b536SPali Rohár static int mvebu_uart_clock_register(struct device *dev,
1304b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock,
1305b7e2b536SPali Rohár const char *name,
1306b7e2b536SPali Rohár const char *parent_name)
1307b7e2b536SPali Rohár {
1308b7e2b536SPali Rohár struct clk_init_data init = { };
1309b7e2b536SPali Rohár
1310b7e2b536SPali Rohár uart_clock->clk_hw.init = &init;
1311b7e2b536SPali Rohár
1312b7e2b536SPali Rohár init.name = name;
1313b7e2b536SPali Rohár init.ops = &mvebu_uart_clock_ops;
1314b7e2b536SPali Rohár init.flags = 0;
1315b7e2b536SPali Rohár init.num_parents = 1;
1316b7e2b536SPali Rohár init.parent_names = &parent_name;
1317b7e2b536SPali Rohár
1318b7e2b536SPali Rohár return devm_clk_hw_register(dev, &uart_clock->clk_hw);
1319b7e2b536SPali Rohár }
1320b7e2b536SPali Rohár
mvebu_uart_clock_probe(struct platform_device * pdev)1321b7e2b536SPali Rohár static int mvebu_uart_clock_probe(struct platform_device *pdev)
1322b7e2b536SPali Rohár {
1323b7e2b536SPali Rohár static const char *const uart_clk_names[] = { "uart_1", "uart_2" };
1324b7e2b536SPali Rohár static const char *const parent_clk_names[] = { "TBG-A-P", "TBG-B-P",
1325b7e2b536SPali Rohár "TBG-A-S", "TBG-B-S",
1326b7e2b536SPali Rohár "xtal" };
1327b7e2b536SPali Rohár struct clk *parent_clks[ARRAY_SIZE(parent_clk_names)];
1328b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base;
1329b7e2b536SPali Rohár struct clk_hw_onecell_data *hw_clk_data;
1330b7e2b536SPali Rohár struct device *dev = &pdev->dev;
1331b7e2b536SPali Rohár int i, parent_clk_idx, ret;
1332b7e2b536SPali Rohár unsigned long div, rate;
1333b7e2b536SPali Rohár struct resource *res;
1334b7e2b536SPali Rohár unsigned int d1, d2;
1335b7e2b536SPali Rohár
1336b7e2b536SPali Rohár BUILD_BUG_ON(ARRAY_SIZE(uart_clk_names) !=
1337b7e2b536SPali Rohár ARRAY_SIZE(uart_clock_base->clocks));
1338b7e2b536SPali Rohár BUILD_BUG_ON(ARRAY_SIZE(parent_clk_names) !=
1339b7e2b536SPali Rohár ARRAY_SIZE(uart_clock_base->parent_rates));
1340b7e2b536SPali Rohár
1341b7e2b536SPali Rohár uart_clock_base = devm_kzalloc(dev,
1342b7e2b536SPali Rohár sizeof(*uart_clock_base),
1343b7e2b536SPali Rohár GFP_KERNEL);
1344b7e2b536SPali Rohár if (!uart_clock_base)
1345b7e2b536SPali Rohár return -ENOMEM;
1346b7e2b536SPali Rohár
1347b7e2b536SPali Rohár res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1348b7e2b536SPali Rohár if (!res) {
1349b7e2b536SPali Rohár dev_err(dev, "Couldn't get first register\n");
1350b7e2b536SPali Rohár return -ENOENT;
1351b7e2b536SPali Rohár }
1352b7e2b536SPali Rohár
1353b7e2b536SPali Rohár /*
1354b7e2b536SPali Rohár * UART Clock Control register (reg1 / UART_BRDV) is in the address
1355b7e2b536SPali Rohár * space of UART1 (standard UART variant), controls parent clock and
1356b7e2b536SPali Rohár * dividers for both UART1 and UART2 and is supplied via DT as the first
1357b7e2b536SPali Rohár * resource. Therefore use ioremap() rather than ioremap_resource() to
1358b7e2b536SPali Rohár * avoid conflicts with UART1 driver. Access to UART_BRDV is protected
1359b7e2b536SPali Rohár * by a lock shared between clock and UART driver.
1360b7e2b536SPali Rohár */
1361b7e2b536SPali Rohár uart_clock_base->reg1 = devm_ioremap(dev, res->start,
1362b7e2b536SPali Rohár resource_size(res));
136347b95e8aSWei Yongjun if (!uart_clock_base->reg1)
136447b95e8aSWei Yongjun return -ENOMEM;
1365b7e2b536SPali Rohár
1366b7e2b536SPali Rohár res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1367b7e2b536SPali Rohár if (!res) {
1368b7e2b536SPali Rohár dev_err(dev, "Couldn't get second register\n");
1369b7e2b536SPali Rohár return -ENOENT;
1370b7e2b536SPali Rohár }
1371b7e2b536SPali Rohár
1372b7e2b536SPali Rohár /*
1373b7e2b536SPali Rohár * UART 2 Baud Rate Divisor register (reg2 / UART_BRDV) is in address
1374b7e2b536SPali Rohár * space of UART2 (extended UART variant), controls only one UART2
1375b7e2b536SPali Rohár * specific divider and is supplied via DT as second resource.
1376b7e2b536SPali Rohár * Therefore use ioremap() rather than ioremap_resource() to avoid
1377b7e2b536SPali Rohár * conflicts with UART2 driver. Access to UART_BRDV is protected by a
1378b7e2b536SPali Rohár * by lock shared between clock and UART driver.
1379b7e2b536SPali Rohár */
1380b7e2b536SPali Rohár uart_clock_base->reg2 = devm_ioremap(dev, res->start,
1381b7e2b536SPali Rohár resource_size(res));
138247b95e8aSWei Yongjun if (!uart_clock_base->reg2)
138347b95e8aSWei Yongjun return -ENOMEM;
1384b7e2b536SPali Rohár
1385b7e2b536SPali Rohár hw_clk_data = devm_kzalloc(dev,
1386b7e2b536SPali Rohár struct_size(hw_clk_data, hws,
1387b7e2b536SPali Rohár ARRAY_SIZE(uart_clk_names)),
1388b7e2b536SPali Rohár GFP_KERNEL);
1389b7e2b536SPali Rohár if (!hw_clk_data)
1390b7e2b536SPali Rohár return -ENOMEM;
1391b7e2b536SPali Rohár
1392b7e2b536SPali Rohár hw_clk_data->num = ARRAY_SIZE(uart_clk_names);
1393b7e2b536SPali Rohár for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) {
1394b7e2b536SPali Rohár hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw;
1395b7e2b536SPali Rohár uart_clock_base->clocks[i].clock_idx = i;
1396b7e2b536SPali Rohár }
1397b7e2b536SPali Rohár
1398b7e2b536SPali Rohár parent_clk_idx = -1;
1399b7e2b536SPali Rohár
1400b7e2b536SPali Rohár for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) {
1401b7e2b536SPali Rohár parent_clks[i] = devm_clk_get(dev, parent_clk_names[i]);
1402b7e2b536SPali Rohár if (IS_ERR(parent_clks[i])) {
1403b7e2b536SPali Rohár if (PTR_ERR(parent_clks[i]) == -EPROBE_DEFER)
1404b7e2b536SPali Rohár return -EPROBE_DEFER;
1405b7e2b536SPali Rohár dev_warn(dev, "Couldn't get the parent clock %s: %ld\n",
1406b7e2b536SPali Rohár parent_clk_names[i], PTR_ERR(parent_clks[i]));
1407b7e2b536SPali Rohár continue;
1408b7e2b536SPali Rohár }
1409b7e2b536SPali Rohár
1410b7e2b536SPali Rohár ret = clk_prepare_enable(parent_clks[i]);
1411b7e2b536SPali Rohár if (ret) {
1412b7e2b536SPali Rohár dev_warn(dev, "Couldn't enable parent clock %s: %d\n",
1413b7e2b536SPali Rohár parent_clk_names[i], ret);
1414b7e2b536SPali Rohár continue;
1415b7e2b536SPali Rohár }
1416b7e2b536SPali Rohár rate = clk_get_rate(parent_clks[i]);
1417b7e2b536SPali Rohár uart_clock_base->parent_rates[i] = rate;
1418b7e2b536SPali Rohár
1419b7e2b536SPali Rohár if (i != PARENT_CLOCK_XTAL) {
1420b7e2b536SPali Rohár /*
1421b7e2b536SPali Rohár * Calculate the smallest TBG d1 and d2 divisors that
1422b7e2b536SPali Rohár * still can provide 9600 baudrate.
1423b7e2b536SPali Rohár */
1424694b7112SPali Rohár d1 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR *
1425b7e2b536SPali Rohár BRDV_BAUD_MAX);
1426b7e2b536SPali Rohár if (d1 < 1)
1427b7e2b536SPali Rohár d1 = 1;
1428b7e2b536SPali Rohár else if (d1 > CLK_TBG_DIV1_MAX)
1429b7e2b536SPali Rohár d1 = CLK_TBG_DIV1_MAX;
1430b7e2b536SPali Rohár
1431694b7112SPali Rohár d2 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR *
1432b7e2b536SPali Rohár BRDV_BAUD_MAX * d1);
1433b7e2b536SPali Rohár if (d2 < 1)
1434b7e2b536SPali Rohár d2 = 1;
1435b7e2b536SPali Rohár else if (d2 > CLK_TBG_DIV2_MAX)
1436b7e2b536SPali Rohár d2 = CLK_TBG_DIV2_MAX;
1437b7e2b536SPali Rohár } else {
1438b7e2b536SPali Rohár /*
1439b7e2b536SPali Rohár * When UART clock uses XTAL clock as a source then it
1440b7e2b536SPali Rohár * is not possible to use d1 and d2 divisors.
1441b7e2b536SPali Rohár */
1442b7e2b536SPali Rohár d1 = d2 = 1;
1443b7e2b536SPali Rohár }
1444b7e2b536SPali Rohár
1445b7e2b536SPali Rohár /* Skip clock source which cannot provide 9600 baudrate */
1446694b7112SPali Rohár if (rate > 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX * d1 * d2)
1447b7e2b536SPali Rohár continue;
1448b7e2b536SPali Rohár
1449b7e2b536SPali Rohár /*
1450b7e2b536SPali Rohár * Choose TBG clock source with the smallest divisors. Use XTAL
1451b7e2b536SPali Rohár * clock source only in case TBG is not available as XTAL cannot
1452b7e2b536SPali Rohár * be used for baudrates higher than 230400.
1453b7e2b536SPali Rohár */
1454b7e2b536SPali Rohár if (parent_clk_idx == -1 ||
1455b7e2b536SPali Rohár (i != PARENT_CLOCK_XTAL && div > d1 * d2)) {
1456b7e2b536SPali Rohár parent_clk_idx = i;
1457b7e2b536SPali Rohár div = d1 * d2;
1458b7e2b536SPali Rohár }
1459b7e2b536SPali Rohár }
1460b7e2b536SPali Rohár
1461b7e2b536SPali Rohár for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) {
1462b7e2b536SPali Rohár if (i == parent_clk_idx || IS_ERR(parent_clks[i]))
1463b7e2b536SPali Rohár continue;
1464b7e2b536SPali Rohár clk_disable_unprepare(parent_clks[i]);
1465b7e2b536SPali Rohár devm_clk_put(dev, parent_clks[i]);
1466b7e2b536SPali Rohár }
1467b7e2b536SPali Rohár
1468b7e2b536SPali Rohár if (parent_clk_idx == -1) {
1469b7e2b536SPali Rohár dev_err(dev, "No usable parent clock\n");
1470b7e2b536SPali Rohár return -ENOENT;
1471b7e2b536SPali Rohár }
1472b7e2b536SPali Rohár
1473b7e2b536SPali Rohár uart_clock_base->parent_idx = parent_clk_idx;
1474b7e2b536SPali Rohár uart_clock_base->div = div;
1475b7e2b536SPali Rohár
1476b7e2b536SPali Rohár dev_notice(dev, "Using parent clock %s as base UART clock\n",
1477b7e2b536SPali Rohár __clk_get_name(parent_clks[parent_clk_idx]));
1478b7e2b536SPali Rohár
1479b7e2b536SPali Rohár for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) {
1480b7e2b536SPali Rohár ret = mvebu_uart_clock_register(dev,
1481b7e2b536SPali Rohár &uart_clock_base->clocks[i],
1482b7e2b536SPali Rohár uart_clk_names[i],
1483b7e2b536SPali Rohár __clk_get_name(parent_clks[parent_clk_idx]));
1484b7e2b536SPali Rohár if (ret) {
1485b7e2b536SPali Rohár dev_err(dev, "Can't register UART clock %d: %d\n",
1486b7e2b536SPali Rohár i, ret);
1487b7e2b536SPali Rohár return ret;
1488b7e2b536SPali Rohár }
1489b7e2b536SPali Rohár }
1490b7e2b536SPali Rohár
1491b7e2b536SPali Rohár return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1492b7e2b536SPali Rohár hw_clk_data);
1493b7e2b536SPali Rohár }
1494b7e2b536SPali Rohár
1495b7e2b536SPali Rohár static const struct of_device_id mvebu_uart_clock_of_match[] = {
1496b7e2b536SPali Rohár { .compatible = "marvell,armada-3700-uart-clock", },
1497b7e2b536SPali Rohár { }
1498b7e2b536SPali Rohár };
1499b7e2b536SPali Rohár
1500b7e2b536SPali Rohár static struct platform_driver mvebu_uart_clock_platform_driver = {
1501b7e2b536SPali Rohár .probe = mvebu_uart_clock_probe,
1502b7e2b536SPali Rohár .driver = {
1503b7e2b536SPali Rohár .name = "mvebu-uart-clock",
1504b7e2b536SPali Rohár .of_match_table = mvebu_uart_clock_of_match,
1505b7e2b536SPali Rohár },
1506b7e2b536SPali Rohár };
1507b7e2b536SPali Rohár
mvebu_uart_init(void)150830530791SWilson Ding static int __init mvebu_uart_init(void)
150930530791SWilson Ding {
151030530791SWilson Ding int ret;
151130530791SWilson Ding
151230530791SWilson Ding ret = uart_register_driver(&mvebu_uart_driver);
151330530791SWilson Ding if (ret)
151430530791SWilson Ding return ret;
151530530791SWilson Ding
1516b7e2b536SPali Rohár ret = platform_driver_register(&mvebu_uart_clock_platform_driver);
1517b7e2b536SPali Rohár if (ret) {
151830530791SWilson Ding uart_unregister_driver(&mvebu_uart_driver);
151930530791SWilson Ding return ret;
152030530791SWilson Ding }
1521b7e2b536SPali Rohár
1522b7e2b536SPali Rohár ret = platform_driver_register(&mvebu_uart_platform_driver);
1523b7e2b536SPali Rohár if (ret) {
1524b7e2b536SPali Rohár platform_driver_unregister(&mvebu_uart_clock_platform_driver);
1525b7e2b536SPali Rohár uart_unregister_driver(&mvebu_uart_driver);
1526b7e2b536SPali Rohár return ret;
1527b7e2b536SPali Rohár }
1528b7e2b536SPali Rohár
1529b7e2b536SPali Rohár return 0;
1530b7e2b536SPali Rohár }
153130530791SWilson Ding arch_initcall(mvebu_uart_init);
1532