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Searched refs:iobase (Results 126 – 150 of 418) sorted by relevance

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/openbmc/linux/drivers/mmc/host/
H A Dmvsdio.c58 void __iomem *iobase = host->base; in mvsd_setup_data() local
139 void __iomem *iobase = host->base; in mvsd_request() local
244 void __iomem *iobase = host->base; in mvsd_finish_cmd() local
289 void __iomem *iobase = host->base; in mvsd_finish_data() local
347 void __iomem *iobase = host->base; in mvsd_irq() local
513 void __iomem *iobase = host->base; in mvsd_timeout_timer() local
554 void __iomem *iobase = host->base; in mvsd_enable_sdio_irq() local
572 void __iomem *iobase = host->base; in mvsd_power_up() local
586 void __iomem *iobase = host->base; in mvsd_power_down() local
601 void __iomem *iobase = host->base; in mvsd_set_ios() local
[all …]
H A Dau1xmmc.c93 void __iomem *iobase; member
138 #define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
139 #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
140 #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
145 #define HOST_CMD(h) ((h)->iobase + SD_CMD)
148 #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
965 host->iobase = ioremap(r->start, 0x3c); in au1xmmc_probe()
966 if (!host->iobase) { in au1xmmc_probe()
1075 " (mode=%s)\n", pdev->id, host->iobase, in au1xmmc_probe()
1107 iounmap((void *)host->iobase); in au1xmmc_probe()
[all …]
/openbmc/linux/drivers/net/wireless/intersil/orinoco/
H A Dhermes.c158 hw->iobase); in hermes_doicmd_wait()
166 hw->iobase, reg); in hermes_doicmd_wait()
190 hw->iobase = address; in hermes_struct_init()
266 "0x%04x.\n", hw->iobase, cmd); in hermes_docmd_wait()
272 hw->iobase, err, cmd); in hermes_docmd_wait()
287 hw->iobase, cmd); in hermes_docmd_wait()
294 "command 0x%04x completion.\n", hw->iobase, cmd); in hermes_docmd_wait()
340 hw->iobase); in hermes_allocate()
347 hw->iobase); in hermes_allocate()
513 hw->iobase, __func__, rid, rtype); in hermes_read_ltv()
[all …]
/openbmc/u-boot/drivers/net/
H A Dax88180.h358 return le16_to_cpu(readw(addr + (void *)dev->iobase)); in INW()
367 writew(cpu_to_le16(command), addr + (void *)dev->iobase); in OUTW()
372 return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase)); in READ_RXBUF()
377 writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase); in WRITE_TXBUF()
382 writel(cpu_to_le32(command), addr + (void *)dev->iobase); in OUTW()
387 return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase)); in READ_RXBUF()
392 writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase); in WRITE_TXBUF()
H A Dxilinx_axi_emac.c91 struct axi_regs *iobase; member
190 struct axi_regs *regs = priv->iobase; in phyread()
216 struct axi_regs *regs = priv->iobase; in phywrite()
245 struct axi_regs *regs = priv->iobase; in axiemac_phy_init()
290 struct axi_regs *regs = priv->iobase; in setup_phy()
372 struct axi_regs *regs = priv->iobase; in axi_ethernet_init()
423 struct axi_regs *regs = priv->iobase; in axiemac_write_hwaddr()
462 struct axi_regs *regs = priv->iobase; in axiemac_start()
718 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); in axi_emac_ofdata_to_platdata()
719 priv->iobase = (struct axi_regs *)pdata->iobase; in axi_emac_ofdata_to_platdata()
[all …]
H A Dftgmac100.c75 struct ftgmac100 *iobase; member
104 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_mdio_read()
133 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_mdio_write()
191 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_phy_adjust_link()
250 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_reset()
266 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_set_mac()
284 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_stop()
298 struct ftgmac100 *ftgmac100 = priv->iobase; in ftgmac100_start()
473 struct ftgmac100 *ftgmac100 = priv->iobase; in BUILD_WAIT_FOR_BIT()
542 pdata->iobase = devfdt_get_addr(dev); in ftgmac100_ofdata_to_platdata()
[all …]
H A Dnatsemi.c254 return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); in INW()
260 return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); in INL()
266 *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); in OUTW()
272 *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); in OUTL()
294 u32 iobase, status, chip_config; in natsemi_initialize() local
305 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); in natsemi_initialize()
306 iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */ in natsemi_initialize()
329 dev->iobase = bus_to_phys(iobase); in natsemi_initialize()
331 printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase); in natsemi_initialize()
445 dev->iobase + ee_addr, write_cmd, value);
[all …]
H A Ddc2114x.c174 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); in INL()
179 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); in OUTL()
198 unsigned int iobase; in dc21x4x_initialize() local
255 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); in dc21x4x_initialize()
256 iobase &= PCI_BASE_ADDRESS_IO_MASK; in dc21x4x_initialize()
259 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); in dc21x4x_initialize()
260 iobase &= PCI_BASE_ADDRESS_MEM_MASK; in dc21x4x_initialize()
262 debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); in dc21x4x_initialize()
279 dev->iobase = pci_io_to_phys(devbusfn, iobase); in dc21x4x_initialize()
281 dev->iobase = pci_mem_to_phys(devbusfn, iobase); in dc21x4x_initialize()
H A Dcalxedaxgmac.c317 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; in init_rx_desc()
333 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; in init_tx_desc()
341 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_reset()
359 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_hwmacaddr()
369 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_init()
428 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_tx()
456 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_rx()
481 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; in xgmac_halt()
525 dev->iobase = (int)base_addr; in calxedaxgmac_initialize()
/openbmc/linux/drivers/comedi/drivers/
H A Dpcmad.c61 status = inb(dev->iobase + PCMAD_STATUS); in pcmad_ai_eoc()
79 outb(chan, dev->iobase + PCMAD_CONVERT); in pcmad_ai_insn_read()
85 val = inb(dev->iobase + PCMAD_LSB) | in pcmad_ai_insn_read()
86 (inb(dev->iobase + PCMAD_MSB) << 8); in pcmad_ai_insn_read()
H A Dadv_pci1724.c79 status = inl(dev->iobase + PCI1724_SYNC_CTRL_REG); in adv_pci1724_dac_idle()
99 outl(0, dev->iobase + PCI1724_SYNC_CTRL_REG); in adv_pci1724_insn_write()
109 dev->iobase + PCI1724_DAC_CTRL_REG); in adv_pci1724_insn_write()
129 dev->iobase = pci_resource_start(pcidev, 2); in adv_pci1724_auto_attach()
130 board_id = inl(dev->iobase + PCI1724_BOARD_ID_REG); in adv_pci1724_auto_attach()
H A Ddas08_cs.c54 unsigned long iobase; in das08_cs_auto_attach() local
64 iobase = link->resource[0]->start; in das08_cs_auto_attach()
70 return das08_common_attach(dev, iobase); in das08_cs_auto_attach()
H A Damplc_pci224.c393 outw(1 << chan, dev->iobase + PCI224_DACCEN); in pci224_ao_set_data()
399 dev->iobase + PCI224_DACCON); in pci224_ao_set_data()
411 outw(mangled, dev->iobase + PCI224_DACDATA); in pci224_ao_set_data()
413 inw(dev->iobase + PCI224_SOFTTRIG); in pci224_ao_set_data()
474 dev->iobase + PCI224_DACCON); in pci224_ao_stop()
514 dacstat = inw(dev->iobase + PCI224_DACCON); in pci224_ao_handle_fifo()
557 dev->iobase + PCI224_DACDATA); in pci224_ao_handle_fifo()
879 dev->iobase + PCI224_DACCON); in pci224_ao_cmd()
1047 outw(0, dev->iobase + PCI224_DACCEN); in pci224_auto_attach()
1048 outw(0, dev->iobase + PCI224_FIFOSIZ); in pci224_auto_attach()
[all …]
H A Daddi_watchdog.h7 void addi_watchdog_reset(unsigned long iobase);
8 int addi_watchdog_init(struct comedi_subdevice *s, unsigned long iobase);
H A Dpcl726.c252 outb((val >> 8) & 0xff, dev->iobase + PCL726_AO_MSB_REG(chan)); in pcl726_ao_insn_write()
253 outb(val & 0xff, dev->iobase + PCL726_AO_LSB_REG(chan)); in pcl726_ao_insn_write()
268 val = inb(dev->iobase + PCL727_DI_LSB_REG); in pcl726_di_insn_bits()
269 val |= (inb(dev->iobase + PCL727_DI_MSB_REG) << 8); in pcl726_di_insn_bits()
271 val = inb(dev->iobase + PCL726_DI_LSB_REG); in pcl726_di_insn_bits()
272 val |= (inb(dev->iobase + PCL726_DI_MSB_REG) << 8); in pcl726_di_insn_bits()
286 unsigned long io = dev->iobase; in pcl726_do_insn_bits()
H A Dni_atmio.c285 unsigned long iobase; in ni_atmio_attach() local
292 iobase = it->options[0]; in ni_atmio_attach()
295 if (iobase == 0) { in ni_atmio_attach()
300 iobase = pnp_port_start(isapnp_dev, 0); in ni_atmio_attach()
305 ret = comedi_request_region(dev, iobase, 0x20); in ni_atmio_attach()
H A Ddyna_pci10xx.c55 status = inw_p(dev->iobase); in dyna_pci10xx_ai_eoc()
81 outw_p(0x0000 + range + chan, dev->iobase + 2); in dyna_pci10xx_insn_read_ai()
89 d = inw_p(dev->iobase); in dyna_pci10xx_insn_read_ai()
113 outw_p(data[n], dev->iobase); in dyna_pci10xx_insn_write_ao()
176 dev->iobase = pci_resource_start(pcidev, 2); in dyna_pci10xx_auto_attach()
H A Dcontec_pci_dio.c35 outw(s->state, dev->iobase + PIO1616L_DO_REG); in contec_do_insn_bits()
46 data[1] = inw(dev->iobase + PIO1616L_DI_REG); in contec_di_insn_bits()
61 dev->iobase = pci_resource_start(pcidev, 0); in contec_auto_attach()
/openbmc/u-boot/drivers/clk/
H A Dclk_pic32.c87 void __iomem *iobase; member
96 v = readl(priv->iobase + SPLLCON); in pic32_get_pll_rate()
122 v = readl(priv->iobase + OSCCON); in pic32_get_sysclk()
158 reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10; in pic32_get_pbclk()
193 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; in pic32_set_refclk()
237 reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20; in pic32_get_refclk()
400 priv->iobase = ioremap(addr, size); in pic32_clk_probe()
401 if (!priv->iobase) in pic32_clk_probe()
/openbmc/linux/drivers/firmware/broadcom/
H A Dbcm47xx_nvram.c140 void __iomem *iobase; in bcm47xx_nvram_init_from_mem() local
143 iobase = ioremap(base, lim); in bcm47xx_nvram_init_from_mem()
144 if (!iobase) in bcm47xx_nvram_init_from_mem()
147 err = bcm47xx_nvram_find_and_copy(iobase, lim); in bcm47xx_nvram_init_from_mem()
149 iounmap(iobase); in bcm47xx_nvram_init_from_mem()
/openbmc/linux/drivers/gpio/
H A Dgpio-sch.c42 unsigned short iobase; member
78 reg_val = !!(inb(sch->iobase + offset) & BIT(bit)); in sch_gpio_reg_get()
92 reg_val = inb(sch->iobase + offset); in sch_gpio_reg_set()
95 outb(reg_val | BIT(bit), sch->iobase + offset); in sch_gpio_reg_set()
97 outb((reg_val & ~BIT(bit)), sch->iobase + offset); in sch_gpio_reg_set()
270 core_status = inl(sch->iobase + CORE_BANK_OFFSET + GTS); in sch_gpio_gpe_handler()
271 resume_status = inl(sch->iobase + RESUME_BANK_OFFSET + GTS); in sch_gpio_gpe_handler()
340 sch->iobase = res->start; in sch_gpio_probe()
/openbmc/u-boot/arch/x86/include/asm/
H A Dpnp_def.h67 static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase) in pnp_set_iobase() argument
69 pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); in pnp_set_iobase()
70 pnp_write_config(dev, index + 1, iobase & 0xff); in pnp_set_iobase()
/openbmc/qemu/hw/misc/
H A Ddebugexit.c22 uint32_t iobase; member
54 isa->iobase, &isa->io); in debug_exit_realizefn()
58 DEFINE_PROP_UINT32("iobase", ISADebugExitState, iobase, 0x501),
/openbmc/linux/drivers/net/wireless/marvell/libertas/
H A Dif_cs.c49 void __iomem *iobase; member
98 unsigned int val = ioread8(card->iobase + reg); in if_cs_read8()
105 unsigned int val = ioread16(card->iobase + reg); in if_cs_read16()
119 ioread16_rep(card->iobase + reg, buf, count); in if_cs_read16_rep()
126 iowrite8(val, card->iobase + reg); in if_cs_write8()
133 iowrite16(val, card->iobase + reg); in if_cs_write16()
145 iowrite16_rep(card->iobase + reg, buf, count); in if_cs_write16_rep()
785 if (card->iobase) in if_cs_release()
786 ioport_unmap(card->iobase); in if_cs_release()
836 if (!card->iobase) { in if_cs_probe()
[all …]
/openbmc/linux/arch/nios2/kernel/
H A Dtime.c245 void __iomem *iobase; in nios2_clockevent_init() local
249 ret = nios2_timer_get_base_and_freq(timer, &iobase, &freq); in nios2_clockevent_init()
259 nios2_ce.timer.base = iobase; in nios2_clockevent_init()
284 void __iomem *iobase; in nios2_clocksource_init() local
288 ret = nios2_timer_get_base_and_freq(timer, &iobase, &freq); in nios2_clocksource_init()
292 nios2_cs.timer.base = iobase; in nios2_clocksource_init()

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