130f57471SLouis Su /* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
230f57471SLouis Su /*
330f57471SLouis Su *
430f57471SLouis Su * This program is free software; you can distribute it and/or modify it
530f57471SLouis Su * under the terms of the GNU General Public License (Version 2) as
630f57471SLouis Su * published by the Free Software Foundation.
730f57471SLouis Su *
830f57471SLouis Su * This program is distributed in the hope it will be useful, but WITHOUT
930f57471SLouis Su * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1030f57471SLouis Su * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1130f57471SLouis Su * for more details.
1230f57471SLouis Su *
1330f57471SLouis Su * You should have received a copy of the GNU General Public License along
1430f57471SLouis Su * with this program; if not, write to the Free Software Foundation, Inc.,
1530f57471SLouis Su * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1630f57471SLouis Su *
1730f57471SLouis Su */
1830f57471SLouis Su
1930f57471SLouis Su #ifndef _AX88180_H_
2030f57471SLouis Su #define _AX88180_H_
2130f57471SLouis Su
22*cafb14feSMike Frysinger #include <asm/io.h>
2330f57471SLouis Su #include <asm/types.h>
2430f57471SLouis Su #include <config.h>
2530f57471SLouis Su
2630f57471SLouis Su typedef enum _ax88180_link_state {
2730f57471SLouis Su INS_LINK_DOWN,
2830f57471SLouis Su INS_LINK_UP,
2930f57471SLouis Su INS_LINK_UNKNOWN
3030f57471SLouis Su } ax88180_link_state;
3130f57471SLouis Su
3230f57471SLouis Su struct ax88180_private {
3330f57471SLouis Su unsigned char BusWidth;
3430f57471SLouis Su unsigned char PadSize;
3530f57471SLouis Su unsigned short PhyAddr;
3630f57471SLouis Su unsigned short PhyID0;
3725667068SHoan Hoang unsigned short PhyID1;
3830f57471SLouis Su unsigned short FirstTxDesc;
3930f57471SLouis Su unsigned short NextTxDesc;
4030f57471SLouis Su ax88180_link_state LinkState;
4130f57471SLouis Su };
4230f57471SLouis Su
4330f57471SLouis Su #define BUS_WIDTH_16 1
4430f57471SLouis Su #define BUS_WIDTH_32 2
4530f57471SLouis Su
4630f57471SLouis Su #define ENABLE_JUMBO 1
4730f57471SLouis Su #define DISABLE_JUMBO 0
4830f57471SLouis Su
4930f57471SLouis Su #define ENABLE_BURST 1
5030f57471SLouis Su #define DISABLE_BURST 0
5130f57471SLouis Su
5230f57471SLouis Su #define NORMAL_RX_MODE 0
5330f57471SLouis Su #define RX_LOOPBACK_MODE 1
5430f57471SLouis Su #define RX_INIFINIT_LOOP_MODE 2
5530f57471SLouis Su #define TX_INIFINIT_LOOP_MODE 3
5630f57471SLouis Su
5730f57471SLouis Su #define DEFAULT_ETH_MTU 1500
5830f57471SLouis Su
5930f57471SLouis Su /* Jumbo packet size 4086 bytes included 4 bytes CRC*/
6030f57471SLouis Su #define MAX_JUMBO_MTU 4072
6130f57471SLouis Su
6230f57471SLouis Su /* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
6330f57471SLouis Su #define MAX_TX_JUMBO_SIZE 4086
6430f57471SLouis Su
6530f57471SLouis Su /* Max Rx Jumbo size is 15K Bytes */
6630f57471SLouis Su #define MAX_RX_SIZE 0x3C00
6730f57471SLouis Su
6825667068SHoan Hoang #define MARVELL_ALASKA_PHYSID0 0x141
6925667068SHoan Hoang #define MARVELL_88E1118_PHYSID1 0xE40
7030f57471SLouis Su
71f9abdfe0SMike Frysinger #define CICADA_CIS8201_PHYSID0 0x000F
7230f57471SLouis Su
7330f57471SLouis Su #define MEDIA_AUTO 0
7430f57471SLouis Su #define MEDIA_1000FULL 1
7530f57471SLouis Su #define MEDIA_1000HALF 2
7630f57471SLouis Su #define MEDIA_100FULL 3
7730f57471SLouis Su #define MEDIA_100HALF 4
7830f57471SLouis Su #define MEDIA_10FULL 5
7930f57471SLouis Su #define MEDIA_10HALF 6
8030f57471SLouis Su #define MEDIA_UNKNOWN 7
8130f57471SLouis Su
8230f57471SLouis Su #define AUTO_MEDIA 0
8330f57471SLouis Su #define FORCE_MEDIA 1
8430f57471SLouis Su
8530f57471SLouis Su #define TXDP_MASK 3
8630f57471SLouis Su #define TXDP0 0
8730f57471SLouis Su #define TXDP1 1
8830f57471SLouis Su #define TXDP2 2
8930f57471SLouis Su #define TXDP3 3
9030f57471SLouis Su
9130f57471SLouis Su #define CMD_MAP_SIZE 0x100
9230f57471SLouis Su
9330f57471SLouis Su #if defined (CONFIG_DRIVER_AX88180_16BIT)
9430f57471SLouis Su #define AX88180_MEMORY_SIZE 0x00004000
9530f57471SLouis Su #define START_BASE 0x1000
9630f57471SLouis Su
9730f57471SLouis Su #define RX_BUF_SIZE 0x1000
9830f57471SLouis Su #define TX_BUF_SIZE 0x0F00
9930f57471SLouis Su
10030f57471SLouis Su #define TX_BASE START_BASE
10130f57471SLouis Su #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
10230f57471SLouis Su #define RX_BASE (CMD_BASE + CMD_MAP_SIZE)
10330f57471SLouis Su #else
10430f57471SLouis Su #define AX88180_MEMORY_SIZE 0x00010000
10530f57471SLouis Su
10630f57471SLouis Su #define RX_BUF_SIZE 0x8000
10730f57471SLouis Su #define TX_BUF_SIZE 0x7C00
10830f57471SLouis Su
10930f57471SLouis Su #define RX_BASE 0x0000
11030f57471SLouis Su #define TX_BASE (RX_BASE + RX_BUF_SIZE)
11130f57471SLouis Su #define CMD_BASE (TX_BASE + TX_BUF_SIZE)
11230f57471SLouis Su #endif
11330f57471SLouis Su
11430f57471SLouis Su /* AX88180 Memory Mapping Definition */
11530f57471SLouis Su #define RXBUFFER_START RX_BASE
11630f57471SLouis Su #define RX_PACKET_LEN_OFFSET 0
11730f57471SLouis Su #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
11830f57471SLouis Su #define TXBUFFER_START TX_BASE
11930f57471SLouis Su
12030f57471SLouis Su /* AX88180 MAC Register Definition */
12130f57471SLouis Su #define DECODE (0)
12230f57471SLouis Su #define DECODE_EN 0x00000001
12330f57471SLouis Su #define BASE (6)
12430f57471SLouis Su #define CMD (CMD_BASE + 0x0000)
12530f57471SLouis Su #define WAKEMOD 0x00000001
12630f57471SLouis Su #define TXEN 0x00000100
12730f57471SLouis Su #define RXEN 0x00000200
12830f57471SLouis Su #define DEFAULT_CMD WAKEMOD
12930f57471SLouis Su #define IMR (CMD_BASE + 0x0004)
13030f57471SLouis Su #define IMR_RXBUFFOVR 0x00000001
13130f57471SLouis Su #define IMR_WATCHDOG 0x00000002
13230f57471SLouis Su #define IMR_TX 0x00000008
13330f57471SLouis Su #define IMR_RX 0x00000010
13430f57471SLouis Su #define IMR_PHY 0x00000020
13530f57471SLouis Su #define CLEAR_IMR 0x00000000
13630f57471SLouis Su #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\
13730f57471SLouis Su IMR_RXBUFFOVR | IMR_WATCHDOG)
13830f57471SLouis Su #define ISR (CMD_BASE + 0x0008)
13930f57471SLouis Su #define ISR_RXBUFFOVR 0x00000001
14030f57471SLouis Su #define ISR_WATCHDOG 0x00000002
14130f57471SLouis Su #define ISR_TX 0x00000008
14230f57471SLouis Su #define ISR_RX 0x00000010
14330f57471SLouis Su #define ISR_PHY 0x00000020
14430f57471SLouis Su #define TXCFG (CMD_BASE + 0x0010)
14530f57471SLouis Su #define AUTOPAD_CRC 0x00000050
14630f57471SLouis Su #define DEFAULT_TXCFG AUTOPAD_CRC
14730f57471SLouis Su #define TXCMD (CMD_BASE + 0x0014)
14830f57471SLouis Su #define TXCMD_TXDP_MASK 0x00006000
14930f57471SLouis Su #define TXCMD_TXDP0 0x00000000
15030f57471SLouis Su #define TXCMD_TXDP1 0x00002000
15130f57471SLouis Su #define TXCMD_TXDP2 0x00004000
15230f57471SLouis Su #define TXCMD_TXDP3 0x00006000
15330f57471SLouis Su #define TX_START_WRITE 0x00008000
15430f57471SLouis Su #define TX_STOP_WRITE 0x00000000
15530f57471SLouis Su #define DEFAULT_TXCMD 0x00000000
15630f57471SLouis Su #define TXBS (CMD_BASE + 0x0018)
15730f57471SLouis Su #define TXDP0_USED 0x00000001
15830f57471SLouis Su #define TXDP1_USED 0x00000002
15930f57471SLouis Su #define TXDP2_USED 0x00000004
16030f57471SLouis Su #define TXDP3_USED 0x00000008
16130f57471SLouis Su #define DEFAULT_TXBS 0x00000000
16230f57471SLouis Su #define TXDES0 (CMD_BASE + 0x0020)
16330f57471SLouis Su #define TXDPx_ENABLE 0x00008000
16430f57471SLouis Su #define TXDPx_LEN_MASK 0x00001FFF
16530f57471SLouis Su #define DEFAULT_TXDES0 0x00000000
16630f57471SLouis Su #define TXDES1 (CMD_BASE + 0x0024)
16730f57471SLouis Su #define TXDPx_ENABLE 0x00008000
16830f57471SLouis Su #define TXDPx_LEN_MASK 0x00001FFF
16930f57471SLouis Su #define DEFAULT_TXDES1 0x00000000
17030f57471SLouis Su #define TXDES2 (CMD_BASE + 0x0028)
17130f57471SLouis Su #define TXDPx_ENABLE 0x00008000
17230f57471SLouis Su #define TXDPx_LEN_MASK 0x00001FFF
17330f57471SLouis Su #define DEFAULT_TXDES2 0x00000000
17430f57471SLouis Su #define TXDES3 (CMD_BASE + 0x002C)
17530f57471SLouis Su #define TXDPx_ENABLE 0x00008000
17630f57471SLouis Su #define TXDPx_LEN_MASK 0x00001FFF
17730f57471SLouis Su #define DEFAULT_TXDES3 0x00000000
17830f57471SLouis Su #define RXCFG (CMD_BASE + 0x0030)
17930f57471SLouis Su #define RXBUFF_PROTECT 0x00000001
18030f57471SLouis Su #define RXTCPCRC_CHECK 0x00000010
18130f57471SLouis Su #define RXFLOW_ENABLE 0x00000100
18230f57471SLouis Su #define DEFAULT_RXCFG RXBUFF_PROTECT
18330f57471SLouis Su #define RXCURT (CMD_BASE + 0x0034)
18430f57471SLouis Su #define DEFAULT_RXCURT 0x00000000
18530f57471SLouis Su #define RXBOUND (CMD_BASE + 0x0038)
186b4dbacf6SWolfgang Denk #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */
18730f57471SLouis Su #define MACCFG0 (CMD_BASE + 0x0040)
18830f57471SLouis Su #define MACCFG0_BIT3_0 0x00000007
18930f57471SLouis Su #define IPGT_VAL 0x00000150
19030f57471SLouis Su #define TXFLOW_ENABLE 0x00001000
19130f57471SLouis Su #define SPEED100 0x00008000
19230f57471SLouis Su #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0)
19330f57471SLouis Su #define MACCFG1 (CMD_BASE + 0x0044)
19430f57471SLouis Su #define RGMII_EN 0x00000002
19530f57471SLouis Su #define RXFLOW_EN 0x00000020
19630f57471SLouis Su #define FULLDUPLEX 0x00000040
19730f57471SLouis Su #define MAX_JUMBO_LEN 0x00000780
19830f57471SLouis Su #define RXJUMBO_EN 0x00000800
19930f57471SLouis Su #define GIGA_MODE_EN 0x00001000
20030f57471SLouis Su #define RXCRC_CHECK 0x00002000
20130f57471SLouis Su #define RXPAUSE_DA_CHECK 0x00004000
20230f57471SLouis Su
20330f57471SLouis Su #define JUMBO_LEN_4K 0x00000200
20430f57471SLouis Su #define JUMBO_LEN_15K 0x00000780
20530f57471SLouis Su #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \
20630f57471SLouis Su RGMII_EN)
20730f57471SLouis Su #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK)
20830f57471SLouis Su #define MACCFG2 (CMD_BASE + 0x0048)
20930f57471SLouis Su #define MACCFG2_BIT15_8 0x00000100
21030f57471SLouis Su #define JAM_LIMIT_MASK 0x000000FC
21130f57471SLouis Su #define DEFAULT_JAM_LIMIT 0x00000064
21230f57471SLouis Su #define DEFAULT_MACCFG2 MACCFG2_BIT15_8
21330f57471SLouis Su #define MACCFG3 (CMD_BASE + 0x004C)
21430f57471SLouis Su #define IPGR2_VAL 0x0000000E
21530f57471SLouis Su #define IPGR1_VAL 0x00000600
21630f57471SLouis Su #define NOABORT 0x00008000
21730f57471SLouis Su #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL)
21830f57471SLouis Su #define TXPAUT (CMD_BASE + 0x0054)
21930f57471SLouis Su #define DEFAULT_TXPAUT 0x001FE000
22030f57471SLouis Su #define RXBTHD0 (CMD_BASE + 0x0058)
22130f57471SLouis Su #define DEFAULT_RXBTHD0 0x00000300
22230f57471SLouis Su #define RXBTHD1 (CMD_BASE + 0x005C)
22330f57471SLouis Su #define DEFAULT_RXBTHD1 0x00000600
22430f57471SLouis Su #define RXFULTHD (CMD_BASE + 0x0060)
22530f57471SLouis Su #define DEFAULT_RXFULTHD 0x00000100
22630f57471SLouis Su #define MISC (CMD_BASE + 0x0068)
22730f57471SLouis Su /* Normal operation mode */
22830f57471SLouis Su #define MISC_NORMAL 0x00000003
22930f57471SLouis Su /* Clear bit 0 to reset MAC */
23030f57471SLouis Su #define MISC_RESET_MAC 0x00000002
23130f57471SLouis Su /* Clear bit 1 to reset PHY */
23230f57471SLouis Su #define MISC_RESET_PHY 0x00000001
23330f57471SLouis Su /* Clear bit 0 and 1 to reset MAC and PHY */
23430f57471SLouis Su #define MISC_RESET_MAC_PHY 0x00000000
23530f57471SLouis Su #define DEFAULT_MISC MISC_NORMAL
23630f57471SLouis Su #define MACID0 (CMD_BASE + 0x0070)
23730f57471SLouis Su #define MACID1 (CMD_BASE + 0x0074)
23830f57471SLouis Su #define MACID2 (CMD_BASE + 0x0078)
23930f57471SLouis Su #define TXLEN (CMD_BASE + 0x007C)
24030f57471SLouis Su #define DEFAULT_TXLEN 0x000005FC
24130f57471SLouis Su #define RXFILTER (CMD_BASE + 0x0080)
24230f57471SLouis Su #define RX_RXANY 0x00000001
24330f57471SLouis Su #define RX_MULTICAST 0x00000002
24430f57471SLouis Su #define RX_UNICAST 0x00000004
24530f57471SLouis Su #define RX_BROADCAST 0x00000008
24630f57471SLouis Su #define RX_MULTI_HASH 0x00000010
24730f57471SLouis Su #define DISABLE_RXFILTER 0x00000000
24830f57471SLouis Su #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST)
24930f57471SLouis Su #define MDIOCTRL (CMD_BASE + 0x0084)
25030f57471SLouis Su #define PHY_ADDR_MASK 0x0000001F
25130f57471SLouis Su #define REG_ADDR_MASK 0x00001F00
25230f57471SLouis Su #define READ_PHY 0x00004000
25330f57471SLouis Su #define WRITE_PHY 0x00008000
25430f57471SLouis Su #define MDIODP (CMD_BASE + 0x0088)
25530f57471SLouis Su #define GPIOCTRL (CMD_BASE + 0x008C)
25630f57471SLouis Su #define RXINDICATOR (CMD_BASE + 0x0090)
25730f57471SLouis Su #define RX_START_READ 0x00000001
25830f57471SLouis Su #define RX_STOP_READ 0x00000000
25930f57471SLouis Su #define DEFAULT_RXINDICATOR RX_STOP_READ
26030f57471SLouis Su #define TXST (CMD_BASE + 0x0094)
26130f57471SLouis Su #define MDCCLKPAT (CMD_BASE + 0x00A0)
26230f57471SLouis Su #define RXIPCRCCNT (CMD_BASE + 0x00A4)
26330f57471SLouis Su #define RXCRCCNT (CMD_BASE + 0x00A8)
26430f57471SLouis Su #define TXFAILCNT (CMD_BASE + 0x00AC)
26530f57471SLouis Su #define PROMDP (CMD_BASE + 0x00B0)
26630f57471SLouis Su #define PROMCTRL (CMD_BASE + 0x00B4)
26730f57471SLouis Su #define RELOAD_EEPROM 0x00000200
26830f57471SLouis Su #define MAXRXLEN (CMD_BASE + 0x00B8)
26930f57471SLouis Su #define HASHTAB0 (CMD_BASE + 0x00C0)
27030f57471SLouis Su #define HASHTAB1 (CMD_BASE + 0x00C4)
27130f57471SLouis Su #define HASHTAB2 (CMD_BASE + 0x00C8)
27230f57471SLouis Su #define HASHTAB3 (CMD_BASE + 0x00CC)
27330f57471SLouis Su #define DOGTHD0 (CMD_BASE + 0x00E0)
27430f57471SLouis Su #define DEFAULT_DOGTHD0 0x0000FFFF
27530f57471SLouis Su #define DOGTHD1 (CMD_BASE + 0x00E4)
27630f57471SLouis Su #define START_WATCHDOG_TIMER 0x00008000
27730f57471SLouis Su #define DEFAULT_DOGTHD1 0x00000FFF
27830f57471SLouis Su #define SOFTRST (CMD_BASE + 0x00EC)
27930f57471SLouis Su #define SOFTRST_NORMAL 0x00000003
28030f57471SLouis Su #define SOFTRST_RESET_MAC 0x00000002
28130f57471SLouis Su
28230f57471SLouis Su /* Marvell 88E1111 Gigabit PHY Register Definition */
28330f57471SLouis Su #define M88_SSR 0x0011
28430f57471SLouis Su #define SSR_SPEED_MASK 0xC000
28530f57471SLouis Su #define SSR_SPEED_1000 0x8000
28630f57471SLouis Su #define SSR_SPEED_100 0x4000
28730f57471SLouis Su #define SSR_SPEED_10 0x0000
28830f57471SLouis Su #define SSR_DUPLEX 0x2000
28930f57471SLouis Su #define SSR_MEDIA_RESOLVED_OK 0x0800
29030f57471SLouis Su
29130f57471SLouis Su #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX)
29230f57471SLouis Su #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX)
29330f57471SLouis Su #define SSR_1000HALF SSR_SPEED_1000
29430f57471SLouis Su #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX)
29530f57471SLouis Su #define SSR_100HALF SSR_SPEED_100
29630f57471SLouis Su #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX)
29730f57471SLouis Su #define SSR_10HALF SSR_SPEED_10
29830f57471SLouis Su #define M88_IER 0x0012
29930f57471SLouis Su #define LINK_CHANGE_INT 0x0400
30030f57471SLouis Su #define M88_ISR 0x0013
30130f57471SLouis Su #define LINK_CHANGE_STATUS 0x0400
30225667068SHoan Hoang #define M88E1111_EXT_SCR 0x0014
30330f57471SLouis Su #define RGMII_RXCLK_DELAY 0x0080
30430f57471SLouis Su #define RGMII_TXCLK_DELAY 0x0002
30530f57471SLouis Su #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
30625667068SHoan Hoang #define M88E1111_EXT_SSR 0x001B
30730f57471SLouis Su #define HWCFG_MODE_MASK 0x000F
30830f57471SLouis Su #define RGMII_COPPER_MODE 0x000B
30930f57471SLouis Su
31025667068SHoan Hoang /* Marvell 88E1118 Gigabit PHY Register Definition */
31125667068SHoan Hoang #define M88E1118_CR 0x14
31225667068SHoan Hoang #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
31325667068SHoan Hoang #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
31425667068SHoan Hoang #define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
31525667068SHoan Hoang M88E1118_CR_RGMII_RXCLK_DELAY)
31625667068SHoan Hoang #define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
31725667068SHoan Hoang #define M88E1118_LEDCTL_LED2INT 0x200
31825667068SHoan Hoang #define M88E1118_LEDCTL_LED2BLNK 0x400
31925667068SHoan Hoang #define M88E1118_LEDCTL_LED0DUALMODE1 0xc
32025667068SHoan Hoang #define M88E1118_LEDCTL_LED0DUALMODE2 0xd
32125667068SHoan Hoang #define M88E1118_LEDCTL_LED0DUALMODE3 0xe
32225667068SHoan Hoang #define M88E1118_LEDCTL_LED0DUALMODE4 0xf
32325667068SHoan Hoang #define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
32425667068SHoan Hoang M88E1118_LEDCTL_LED0DUALMODE4)
32525667068SHoan Hoang
32625667068SHoan Hoang #define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
32725667068SHoan Hoang #define M88E1118_LEDMIX_LED050 0x4
32825667068SHoan Hoang #define M88E1118_LEDMIX_LED150 0x8
32925667068SHoan Hoang
33025667068SHoan Hoang #define M88E1118_PAGE_SEL 0x16 /* Reg page select */
33125667068SHoan Hoang
33230f57471SLouis Su /* CICADA CIS8201 Gigabit PHY Register Definition */
33330f57471SLouis Su #define CIS_IMR 0x0019
33430f57471SLouis Su #define CIS_INT_ENABLE 0x8000
33530f57471SLouis Su #define CIS_LINK_CHANGE_INT 0x2000
33630f57471SLouis Su #define CIS_ISR 0x001A
33730f57471SLouis Su #define CIS_INT_PENDING 0x8000
33830f57471SLouis Su #define CIS_LINK_CHANGE_STATUS 0x2000
33930f57471SLouis Su #define CIS_AUX_CTRL_STATUS 0x001C
34030f57471SLouis Su #define CIS_AUTONEG_COMPLETE 0x8000
34130f57471SLouis Su #define CIS_SPEED_MASK 0x0018
34230f57471SLouis Su #define CIS_SPEED_1000 0x0010
34330f57471SLouis Su #define CIS_SPEED_100 0x0008
34430f57471SLouis Su #define CIS_SPEED_10 0x0000
34530f57471SLouis Su #define CIS_DUPLEX 0x0020
34630f57471SLouis Su
34730f57471SLouis Su #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX)
34830f57471SLouis Su #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX)
34930f57471SLouis Su #define CIS_1000HALF CIS_SPEED_1000
35030f57471SLouis Su #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX)
35130f57471SLouis Su #define CIS_100HALF CIS_SPEED_100
35230f57471SLouis Su #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX)
35330f57471SLouis Su #define CIS_10HALF CIS_SPEED_10
35430f57471SLouis Su #define CIS_SMI_PRIORITY 0x0004
35530f57471SLouis Su
INW(struct eth_device * dev,unsigned long addr)35630f57471SLouis Su static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
35730f57471SLouis Su {
358*cafb14feSMike Frysinger return le16_to_cpu(readw(addr + (void *)dev->iobase));
35930f57471SLouis Su }
36030f57471SLouis Su
36114f637f8SHoan Hoang /*
36214f637f8SHoan Hoang Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
36314f637f8SHoan Hoang */
36414f637f8SHoan Hoang #if defined (CONFIG_DRIVER_AX88180_16BIT)
OUTW(struct eth_device * dev,unsigned short command,unsigned long addr)36530f57471SLouis Su static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
36630f57471SLouis Su {
367*cafb14feSMike Frysinger writew(cpu_to_le16(command), addr + (void *)dev->iobase);
36830f57471SLouis Su }
36930f57471SLouis Su
READ_RXBUF(struct eth_device * dev)37030f57471SLouis Su static inline unsigned short READ_RXBUF (struct eth_device *dev)
37130f57471SLouis Su {
372*cafb14feSMike Frysinger return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase));
37330f57471SLouis Su }
37430f57471SLouis Su
WRITE_TXBUF(struct eth_device * dev,unsigned short data)37530f57471SLouis Su static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
37630f57471SLouis Su {
377*cafb14feSMike Frysinger writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase);
37830f57471SLouis Su }
37930f57471SLouis Su #else
OUTW(struct eth_device * dev,unsigned short command,unsigned long addr)38014f637f8SHoan Hoang static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
38114f637f8SHoan Hoang {
382*cafb14feSMike Frysinger writel(cpu_to_le32(command), addr + (void *)dev->iobase);
38314f637f8SHoan Hoang }
38414f637f8SHoan Hoang
READ_RXBUF(struct eth_device * dev)38530f57471SLouis Su static inline unsigned long READ_RXBUF (struct eth_device *dev)
38630f57471SLouis Su {
387*cafb14feSMike Frysinger return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase));
38830f57471SLouis Su }
38930f57471SLouis Su
WRITE_TXBUF(struct eth_device * dev,unsigned long data)39030f57471SLouis Su static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
39130f57471SLouis Su {
392*cafb14feSMike Frysinger writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase);
39330f57471SLouis Su }
39430f57471SLouis Su #endif
39530f57471SLouis Su
39630f57471SLouis Su #endif /* _AX88180_H_ */
397