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/openbmc/linux/sound/soc/intel/skylake/
H A Dskl.h120 struct skl_dsp_cores cores; member
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sdx55-pas.yaml14 on the Qualcomm DSP Hexagon cores.
H A Dti,omap-remoteproc.yaml17 The processor cores in the sub-system are usually behind an IOMMU, and may
23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
166 serve as Watchdog timers for the processor cores. This
/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,spm.yaml15 the peripheral logic surrounding the application cores in Qualcomm platforms.
H A Dqcom,rpm-master-stats.yaml23 how many times a given sleep state was entered and which cores are actively
/openbmc/google-misc/subprojects/metrics-ipmi-blobs/
H A Dmetricblob.proto27 float idle_process_time = 2; // Idle process time across all cores
/openbmc/linux/arch/xtensa/
H A DKconfig237 like the open cores ethernet driver and the serial interface.
265 bool "Secondary cores use alternative reset vector"
269 Secondary cores may be configured to use alternative reset vector,
270 or all cores may use primary reset vector.
318 Normally cores with windowed registers option use windowed ABI and
319 cores without it use call0 ABI.
345 Assume default userspace ABI. For XEA2 cores it is windowed ABI.
374 raise an illegal instruction exception on cores with XEA2 when
/openbmc/linux/arch/x86/events/
H A Drapl.c397 RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01");
403 RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules");
412 RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10");
/openbmc/linux/drivers/bus/
H A DKconfig62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
114 cores. This bus is for per-CPU tightly coupled devices such as the
/openbmc/qemu/tests/vm/
H A Dconf_example_aarch64.yml26 qemu_args: "-smp cpus=16,sockets=2,cores=8
H A Dconf_example_x86.yml27 qemu_args: "-smp cpus=8,sockets=2,cores=4
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Drenesas,rcar-sysc.yaml15 cores and various coprocessors.
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,liointc.yaml15 can route local I/O interrupt to interrupt lines of cores.
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-cpu-debug.yaml61 constrained to keep CPU cores powered.
/openbmc/linux/Documentation/arch/arm/samsung/
H A Doverview.rst9 ARM9 through to the newest ARM cores. This document shows an overview of
H A Dbootloader-interface.rst79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
/openbmc/phosphor-mrw-tools/docs/
H A Dmrw-xml-requirements.md15 like the BMC chip and processor cores.
21 **Note**: The BMC and cores will be automatically added without the need to set
/openbmc/qemu/hw/loongarch/
H A Dvirt.c361 num / (ms->smp.cores * ms->smp.threads), in fdt_add_cpu_nodes()
362 (num / ms->smp.threads) % ms->smp.cores, in fdt_add_cpu_nodes()
367 num / ms->smp.cores, in fdt_add_cpu_nodes()
368 num % ms->smp.cores); in fdt_add_cpu_nodes()
1353 n / (ms->smp.cores * ms->smp.threads); in virt_possible_cpu_arch_ids()
1356 n / ms->smp.threads % ms->smp.cores; in virt_possible_cpu_arch_ids()
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dfsl-spi.txt15 - clock-frequency : input clock frequency to non FSL_SOC cores
/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dsocionext,uniphier-system-cache.yaml30 The number of interrupts should match to the number of CPU cores.
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml23 T-Head C906/C910 CPU cores include an implementation of CLINT too, however
/openbmc/linux/tools/power/cpupower/lib/
H A Dcpupower.c166 cpu_top->pkgs = cpu_top->cores = 0; in get_cpu_topology()
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Drenesas,rst.yaml21 CPU cores (on R-Car Gen2 and Gen3, and on RZ/G).
/openbmc/linux/Documentation/arch/x86/
H A Dresctrl.rst435 caches on a socket, multiple cores could share an L2 cache. So instead
483 external bandwidth. Consider an SKL SKU with 24 cores on a package and
491 this would be dependent on number of cores the benchmark is run on.
499 threads start using more cores in an rdtgroup, the actual bandwidth may
677 with affinity to the cores (or a subset of the cores) associated
683 application self needs to ensure it remains affine to the correct cores.
939 also get 50% of memory bandwidth assuming that the cores 4-7 are SMT
940 siblings and only the real time threads are scheduled on the cores 4-7.
1069 * cores associated with the pseudo-locked region. Here the cpu
1345 A single socket system which has real time tasks running on cores 4-7
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/openbmc/u-boot/board/freescale/t1040qds/
H A DREADME9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache

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