18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2a40e693cSJeeja KP /*
3*bb0f78e5SBhaskar Chowdhury * skl.h - HD Audio skylake definitions.
4a40e693cSJeeja KP *
5a40e693cSJeeja KP * Copyright (C) 2015 Intel Corp
6a40e693cSJeeja KP * Author: Jeeja KP <jeeja.kp@intel.com>
7a40e693cSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8a40e693cSJeeja KP *
9a40e693cSJeeja KP * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10a40e693cSJeeja KP */
11a40e693cSJeeja KP
12a40e693cSJeeja KP #ifndef __SOUND_SOC_SKL_H
13a40e693cSJeeja KP #define __SOUND_SOC_SKL_H
14a40e693cSJeeja KP
15a40e693cSJeeja KP #include <sound/hda_register.h>
16a40e693cSJeeja KP #include <sound/hdaudio_ext.h>
1700deadb5SRakesh Ughreja #include <sound/hda_codec.h>
18d14700a0SVinod Koul #include <sound/soc.h>
19bc2bd45bSSriram Periyasamy #include "skl-ssp-clk.h"
20bcc2a2dcSCezary Rojewski #include "skl-sst-ipc.h"
21a40e693cSJeeja KP
22a40e693cSJeeja KP #define SKL_SUSPEND_DELAY 2000
23a40e693cSJeeja KP
2443762355SPradeep Tewani #define SKL_MAX_ASTATE_CFG 3
2543762355SPradeep Tewani
2651a01b8cSDharageswari R #define AZX_PCIREG_PGCTL 0x44
2751a01b8cSDharageswari R #define AZX_PGCTL_LSRMD_MASK (1 << 4)
28fc9fdd61SSanyog Kale #define AZX_PGCTL_ADSPPGD BIT(2)
290c8ba9d2SJayachandran B #define AZX_PCIREG_CGCTL 0x48
300c8ba9d2SJayachandran B #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)
31fc9fdd61SSanyog Kale #define AZX_CGCTL_ADSPDCGE BIT(1)
32a26a3f53SPardha Saradhi K /* D0I3C Register fields */
33a26a3f53SPardha Saradhi K #define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */
34a26a3f53SPardha Saradhi K #define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */
3501f50d69SSriram Periyasamy #define SKL_MAX_DMACTRL_CFG 18
3601f50d69SSriram Periyasamy #define DMA_CLK_CONTROLS 1
3701f50d69SSriram Periyasamy #define DMA_TRANSMITION_START 2
3801f50d69SSriram Periyasamy #define DMA_TRANSMITION_STOP 3
390c8ba9d2SJayachandran B
407a1954deSCezary Rojewski #define AZX_VS_EM2_DUM BIT(23)
41fc9fdd61SSanyog Kale #define AZX_REG_VS_EM2_L1SEN BIT(13)
42fc9fdd61SSanyog Kale
435cdf6c09SVinod Koul struct skl_debug;
445cdf6c09SVinod Koul
4543762355SPradeep Tewani struct skl_astate_param {
4643762355SPradeep Tewani u32 kcps;
4743762355SPradeep Tewani u32 clk_src;
4843762355SPradeep Tewani };
4943762355SPradeep Tewani
5043762355SPradeep Tewani struct skl_astate_config {
5143762355SPradeep Tewani u32 count;
52936b9df7SGustavo A. R. Silva struct skl_astate_param astate_table[];
5343762355SPradeep Tewani };
5443762355SPradeep Tewani
5543762355SPradeep Tewani struct skl_fw_config {
5643762355SPradeep Tewani struct skl_astate_config *astate_cfg;
5743762355SPradeep Tewani };
5843762355SPradeep Tewani
59bcc2a2dcSCezary Rojewski struct skl_dev {
6000deadb5SRakesh Ughreja struct hda_bus hbus;
61a40e693cSJeeja KP struct pci_dev *pci;
62a40e693cSJeeja KP
63ab1b732dSVinod Koul unsigned int init_done:1; /* delayed init status */
64a40e693cSJeeja KP struct platform_device *dmic_dev;
65cc18c5fdSVinod Koul struct platform_device *i2s_dev;
66bc2bd45bSSriram Periyasamy struct platform_device *clk_dev;
6756b03b4cSKuninori Morimoto struct snd_soc_component *component;
68c3ae22e3SGuneshwor Singh struct snd_soc_dai_driver *dais;
69473eb87aSJeeja KP
70c286b3f9SJeeja KP struct nhlt_acpi_table *nhlt; /* nhlt ptr */
71e4e2d2f4SJeeja KP
72e4e2d2f4SJeeja KP struct list_head ppl_list;
73b8c722ddSJeeja KP struct list_head bind_list;
74aecf6fd8SVinod Koul
75aecf6fd8SVinod Koul const char *fw_name;
764b235c43SVinod Koul char tplg_name[64];
774b235c43SVinod Koul unsigned short pci_id;
784557c305SJeeja KP
794557c305SJeeja KP int supend_active;
80ab1b732dSVinod Koul
81ab1b732dSVinod Koul struct work_struct probe_work;
825cdf6c09SVinod Koul
835cdf6c09SVinod Koul struct skl_debug *debugfs;
84822c3b04SShreyas NC u8 nr_modules;
85822c3b04SShreyas NC struct skl_module **modules;
86c3ae22e3SGuneshwor Singh bool use_tplg_pcm;
8743762355SPradeep Tewani struct skl_fw_config cfg;
88752c93aaSPankaj Bharadiya struct snd_soc_acpi_mach *mach;
89bcc2a2dcSCezary Rojewski
90bcc2a2dcSCezary Rojewski struct device *dev;
91bcc2a2dcSCezary Rojewski struct sst_dsp *dsp;
92bcc2a2dcSCezary Rojewski
93bcc2a2dcSCezary Rojewski /* boot */
94bcc2a2dcSCezary Rojewski wait_queue_head_t boot_wait;
95bcc2a2dcSCezary Rojewski bool boot_complete;
96bcc2a2dcSCezary Rojewski
97bcc2a2dcSCezary Rojewski /* module load */
98bcc2a2dcSCezary Rojewski wait_queue_head_t mod_load_wait;
99bcc2a2dcSCezary Rojewski bool mod_load_complete;
100bcc2a2dcSCezary Rojewski bool mod_load_status;
101bcc2a2dcSCezary Rojewski
102bcc2a2dcSCezary Rojewski /* IPC messaging */
103bcc2a2dcSCezary Rojewski struct sst_generic_ipc ipc;
104bcc2a2dcSCezary Rojewski
105bcc2a2dcSCezary Rojewski /* callback for miscbdge */
106bcc2a2dcSCezary Rojewski void (*enable_miscbdcge)(struct device *dev, bool enable);
107bcc2a2dcSCezary Rojewski /* Is CGCTL.MISCBDCGE disabled */
108bcc2a2dcSCezary Rojewski bool miscbdcg_disabled;
109bcc2a2dcSCezary Rojewski
110bcc2a2dcSCezary Rojewski /* Populate module information */
111bcc2a2dcSCezary Rojewski struct list_head uuid_list;
112bcc2a2dcSCezary Rojewski
113bcc2a2dcSCezary Rojewski /* Is firmware loaded */
114bcc2a2dcSCezary Rojewski bool fw_loaded;
115bcc2a2dcSCezary Rojewski
116bcc2a2dcSCezary Rojewski /* first boot ? */
117bcc2a2dcSCezary Rojewski bool is_first_boot;
118bcc2a2dcSCezary Rojewski
119bcc2a2dcSCezary Rojewski /* multi-core */
120bcc2a2dcSCezary Rojewski struct skl_dsp_cores cores;
121bcc2a2dcSCezary Rojewski
122bcc2a2dcSCezary Rojewski /* library info */
123bcc2a2dcSCezary Rojewski struct skl_lib_info lib_info[SKL_MAX_LIB];
124bcc2a2dcSCezary Rojewski int lib_count;
125bcc2a2dcSCezary Rojewski
126bcc2a2dcSCezary Rojewski /* Callback to update D0i3C register */
127bcc2a2dcSCezary Rojewski void (*update_d0i3c)(struct device *dev, bool enable);
128bcc2a2dcSCezary Rojewski
129bcc2a2dcSCezary Rojewski struct skl_d0i3_data d0i3;
130bcc2a2dcSCezary Rojewski
131bcc2a2dcSCezary Rojewski const struct skl_dsp_ops *dsp_ops;
132bcc2a2dcSCezary Rojewski
133bcc2a2dcSCezary Rojewski /* Callback to update dynamic clock and power gating registers */
134bcc2a2dcSCezary Rojewski void (*clock_power_gating)(struct device *dev, bool enable);
135a40e693cSJeeja KP };
136a40e693cSJeeja KP
13700deadb5SRakesh Ughreja #define skl_to_bus(s) (&(s)->hbus.core)
138bcc2a2dcSCezary Rojewski #define bus_to_skl(bus) container_of(bus, struct skl_dev, hbus.core)
13900deadb5SRakesh Ughreja
14000deadb5SRakesh Ughreja #define skl_to_hbus(s) (&(s)->hbus)
141bcc2a2dcSCezary Rojewski #define hbus_to_skl(hbus) container_of((hbus), struct skl_dev, (hbus))
142a40e693cSJeeja KP
143a40e693cSJeeja KP /* to pass dai dma data */
144a40e693cSJeeja KP struct skl_dma_params {
145a40e693cSJeeja KP u32 format;
146a40e693cSJeeja KP u8 stream_tag;
147a40e693cSJeeja KP };
148a40e693cSJeeja KP
149f65cf7d6SYong Zhi struct skl_machine_pdata {
150c3ae22e3SGuneshwor Singh bool use_tplg_pcm; /* use dais and dai links from topology */
151f65cf7d6SYong Zhi };
152f65cf7d6SYong Zhi
153bc23ca35SJeeja KP struct skl_dsp_ops {
154bc23ca35SJeeja KP int id;
155363d4538SDharageswari R unsigned int num_cores;
156bc23ca35SJeeja KP struct skl_dsp_loader_ops (*loader_ops)(void);
157bc23ca35SJeeja KP int (*init)(struct device *dev, void __iomem *mmio_base,
158bc23ca35SJeeja KP int irq, const char *fw_name,
159bc23ca35SJeeja KP struct skl_dsp_loader_ops loader_ops,
160bcc2a2dcSCezary Rojewski struct skl_dev **skl_sst);
161bcc2a2dcSCezary Rojewski int (*init_fw)(struct device *dev, struct skl_dev *skl);
162bcc2a2dcSCezary Rojewski void (*cleanup)(struct device *dev, struct skl_dev *skl);
163bc23ca35SJeeja KP };
164bc23ca35SJeeja KP
165a40e693cSJeeja KP int skl_platform_unregister(struct device *dev);
166a40e693cSJeeja KP int skl_platform_register(struct device *dev);
167a40e693cSJeeja KP
168bcc2a2dcSCezary Rojewski int skl_nhlt_update_topology_bin(struct skl_dev *skl);
169bcc2a2dcSCezary Rojewski int skl_init_dsp(struct skl_dev *skl);
170bcc2a2dcSCezary Rojewski int skl_free_dsp(struct skl_dev *skl);
171bcc2a2dcSCezary Rojewski int skl_suspend_late_dsp(struct skl_dev *skl);
172bcc2a2dcSCezary Rojewski int skl_suspend_dsp(struct skl_dev *skl);
173bcc2a2dcSCezary Rojewski int skl_resume_dsp(struct skl_dev *skl);
174bcc2a2dcSCezary Rojewski void skl_cleanup_resources(struct skl_dev *skl);
17573a67581SVinod Koul const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
176a26a3f53SPardha Saradhi K void skl_update_d0i3c(struct device *dev, bool enable);
177bcc2a2dcSCezary Rojewski int skl_nhlt_create_sysfs(struct skl_dev *skl);
178bcc2a2dcSCezary Rojewski void skl_nhlt_remove_sysfs(struct skl_dev *skl);
179bcc2a2dcSCezary Rojewski void skl_get_clks(struct skl_dev *skl, struct skl_ssp_clk *ssp_clks);
180bc2bd45bSSriram Periyasamy struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id);
181bcc2a2dcSCezary Rojewski int skl_dsp_set_dma_control(struct skl_dev *skl, u32 *caps,
18201f50d69SSriram Periyasamy u32 caps_size, u32 node_id);
183a26a3f53SPardha Saradhi K
184d14700a0SVinod Koul struct skl_module_cfg;
185d14700a0SVinod Koul
1865cdf6c09SVinod Koul #ifdef CONFIG_DEBUG_FS
187bcc2a2dcSCezary Rojewski struct skl_debug *skl_debugfs_init(struct skl_dev *skl);
188bcc2a2dcSCezary Rojewski void skl_debugfs_exit(struct skl_dev *skl);
189d14700a0SVinod Koul void skl_debug_init_module(struct skl_debug *d,
190d14700a0SVinod Koul struct snd_soc_dapm_widget *w,
191d14700a0SVinod Koul struct skl_module_cfg *mconfig);
1925cdf6c09SVinod Koul #else
skl_debugfs_init(struct skl_dev * skl)193bcc2a2dcSCezary Rojewski static inline struct skl_debug *skl_debugfs_init(struct skl_dev *skl)
1945cdf6c09SVinod Koul {
1955cdf6c09SVinod Koul return NULL;
1965cdf6c09SVinod Koul }
1975b8e4c1cSAmadeusz Sławiński
skl_debugfs_exit(struct skl_dev * skl)198bcc2a2dcSCezary Rojewski static inline void skl_debugfs_exit(struct skl_dev *skl)
1995b8e4c1cSAmadeusz Sławiński {}
2005b8e4c1cSAmadeusz Sławiński
skl_debug_init_module(struct skl_debug * d,struct snd_soc_dapm_widget * w,struct skl_module_cfg * mconfig)201d14700a0SVinod Koul static inline void skl_debug_init_module(struct skl_debug *d,
202d14700a0SVinod Koul struct snd_soc_dapm_widget *w,
203d14700a0SVinod Koul struct skl_module_cfg *mconfig)
204d14700a0SVinod Koul {}
2055cdf6c09SVinod Koul #endif
2065cdf6c09SVinod Koul
207a40e693cSJeeja KP #endif /* __SOUND_SOC_SKL_H */
208