| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/ |
| H A D | dce100_resource.c | 473 return &tg110->base; in dce100_timing_generator_create()
488 return &enc110->base; in dce100_stream_encoder_create()
572 return &dce_mi->base; in dce100_mem_input_create()
593 return &transform->base; in dce100_transform_create()
608 return &ipp->base; in dce100_ipp_create()
638 return &enc110->base; in dce100_link_encoder_create()
670 return &opp->base; in dce100_opp_create()
742 return &clk_src->base; in dce100_clock_source_create()
1060 if (!pool->base.irqs) in dce100_resource_construct()
1069 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
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| /openbmc/linux/drivers/gpu/ipu-v3/ |
| H A D | ipu-dp.c | 56 void __iomem *base; member
63 void __iomem *base; member
151 flow->base + DP_CSC_0); in ipu_dp_csc_init()
153 flow->base + DP_CSC_1); in ipu_dp_csc_init()
161 flow->base + DP_CSC_0); in ipu_dp_csc_init()
163 flow->base + DP_CSC_1); in ipu_dp_csc_init()
171 flow->base + DP_CSC_0); in ipu_dp_csc_init()
173 flow->base + DP_CSC_1); in ipu_dp_csc_init()
357 priv->base = devm_ioremap(dev, base, PAGE_SIZE); in ipu_dp_init()
358 if (!priv->base) in ipu_dp_init()
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-davinci.c | 52 void __iomem *base; member
62 void __iomem *base; member
236 base + DAVINCI_TIMER_REG_TGCR); in davinci_timer_init()
247 void __iomem *base; in davinci_timer_register() local
265 if (!base) { in davinci_timer_register()
271 davinci_timer_init(base); in davinci_timer_register()
283 clockevent->base = base; in davinci_timer_register()
311 davinci_clocksource.base = base; in davinci_timer_register()
316 davinci_clocksource_init_tim12(base); in davinci_timer_register()
320 davinci_clocksource_init_tim34(base); in davinci_timer_register()
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| H A D | timer-fttmr010.c | 100 void __iomem *base; member
164 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
166 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
187 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
189 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
244 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_periodic()
246 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_periodic()
305 fttmr010->base = of_iomap(np, 0); in fttmr010_common_init()
306 if (!fttmr010->base) { in fttmr010_common_init()
346 writel(val, fttmr010->base + TIMER_CR); in fttmr010_common_init()
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| /openbmc/linux/drivers/watchdog/ |
| H A D | davinci_wdt.c | 65 void __iomem *base; member
80 iowrite32(0, davinci_wdt->base + TCR); in davinci_wdt_start()
82 iowrite32(0, davinci_wdt->base + TGCR); in davinci_wdt_start()
86 iowrite32(0, davinci_wdt->base + TIM12); in davinci_wdt_start()
87 iowrite32(0, davinci_wdt->base + TIM34); in davinci_wdt_start()
149 iowrite32(0, davinci_wdt->base + TCR); in davinci_wdt_restart()
158 iowrite32(0, davinci_wdt->base + TIM12); in davinci_wdt_restart()
159 iowrite32(0, davinci_wdt->base + TIM34); in davinci_wdt_restart()
160 iowrite32(0, davinci_wdt->base + PRD12); in davinci_wdt_restart()
226 if (IS_ERR(davinci_wdt->base)) in davinci_wdt_probe()
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| /openbmc/linux/arch/x86/boot/ |
| H A D | string.c | 124 if (!base) in simple_strtoull()
125 base = simple_guess_base(cp); in simple_strtoull()
134 if (value >= base) in simple_strtoull()
234 if (*base == 0) { in _parse_integer_fixup_radix()
237 *base = 16; in _parse_integer_fixup_radix()
239 *base = 8; in _parse_integer_fixup_radix()
241 *base = 10; in _parse_integer_fixup_radix()
257 unsigned int base, in _parse_integer() argument
277 if (val >= base) in _parse_integer()
287 res = res * base + val; in _parse_integer()
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-cpu.c | 142 div0 = readl(base + E4210_DIV_CPU0); in exynos_set_safe_div()
144 writel(div0, base + E4210_DIV_CPU0); in exynos_set_safe_div()
212 writel(div0, base + E4210_DIV_CPU0); in exynos_cpuclk_pre_rate_change()
270 div0 = readl(base + E5433_DIV_CPU0); in exynos5433_set_safe_div()
272 writel(div0, base + E5433_DIV_CPU0); in exynos5433_set_safe_div()
326 writel(div0, base + E5433_DIV_CPU0); in exynos5433_cpuclk_pre_rate_change()
329 writel(div1, base + E5433_DIV_CPU1); in exynos5433_cpuclk_pre_rate_change()
365 void __iomem *base; in exynos_cpuclk_notifier_cb() local
369 base = cpuclk->ctrl_base; in exynos_cpuclk_notifier_cb()
388 void __iomem *base; in exynos5433_cpuclk_notifier_cb() local
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| /openbmc/linux/drivers/net/ethernet/mellanox/mlxbf_gige/ |
| H A D | mlxbf_gige_rx.c | 17 void __iomem *base = priv->base; in mlxbf_gige_set_mac_rx_filter() local
21 writeq(dmac, base + MLXBF_GIGE_RX_MAC_FILTER + in mlxbf_gige_set_mac_rx_filter()
25 control = readq(base + MLXBF_GIGE_CONTROL); in mlxbf_gige_set_mac_rx_filter()
27 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_set_mac_rx_filter()
33 void __iomem *base = priv->base; in mlxbf_gige_get_mac_rx_filter() local
42 void __iomem *base = priv->base; in mlxbf_gige_enable_promisc() local
47 control = readq(base + MLXBF_GIGE_CONTROL); in mlxbf_gige_enable_promisc()
49 writeq(control, base + MLXBF_GIGE_CONTROL); in mlxbf_gige_enable_promisc()
61 void __iomem *base = priv->base; in mlxbf_gige_disable_promisc() local
135 data = readq(priv->base + MLXBF_GIGE_RX); in mlxbf_gige_rx_init()
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
| H A D | auxg94.c | 28 struct nvkm_i2c_aux base; member
80 struct nvkm_i2c *i2c = aux->base.pad->i2c; in g94_i2c_aux_xfer()
82 const u32 base = aux->ch * 0x50; in g94_i2c_aux_xfer() local
93 stat = nvkm_rd32(device, 0x00e4e8 + base); in g94_i2c_aux_xfer()
95 AUX_TRACE(&aux->base, "sink not detected"); in g94_i2c_aux_xfer()
110 ctrl = nvkm_rd32(device, 0x00e4e4 + base); in g94_i2c_aux_xfer()
114 nvkm_wr32(device, 0x00e4e0 + base, addr); in g94_i2c_aux_xfer()
129 ctrl = nvkm_rd32(device, 0x00e4e4 + base); in g94_i2c_aux_xfer()
132 AUX_ERR(&aux->base, "timeout %08x", ctrl); in g94_i2c_aux_xfer()
176 *paux = &aux->base; in g94_i2c_aux_new_()
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| H A D | busnv50.c | 30 struct nvkm_i2c_bus base; member
36 nv50_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) in nv50_i2c_bus_drive_scl() argument
38 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_drive_scl()
48 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_drive_sda()
56 nv50_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) in nv50_i2c_bus_sense_scl() argument
58 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_sense_scl()
64 nv50_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) in nv50_i2c_bus_sense_sda() argument
66 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_sense_sda()
72 nv50_i2c_bus_init(struct nvkm_i2c_bus *base) in nv50_i2c_bus_init() argument
74 struct nv50_i2c_bus *bus = nv50_i2c_bus(base); in nv50_i2c_bus_init()
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-vt8500.c | 73 void __iomem *base = priv->base; in vt8500_irq_mask() local
94 void __iomem *base = priv->base; in vt8500_irq_unmask() local
97 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_unmask()
105 void __iomem *base = priv->base; in vt8500_irq_set_type() local
146 writel(0x00, base + VT8500_ICPC_FIQ); in vt8500_init_irq_hw()
170 void __iomem *base; in vt8500_handle_irq() local
174 base = intc[i].base; in vt8500_handle_irq()
175 irqnr = readl_relaxed(base) & 0x3F; in vt8500_handle_irq()
202 intc[active_cnt].base = of_iomap(np, 0); in vt8500_irq_init()
206 if (!intc[active_cnt].base) { in vt8500_irq_init()
[all …]
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| /openbmc/linux/drivers/gpu/drm/lima/ |
| H A D | lima_gem.c | 25 struct device *dev = bo->base.base.dev->dev; in lima_heap_alloc()
32 if (bo->heap_size >= bo->base.base.size) in lima_heap_alloc()
35 new_size = min(new_size, bo->base.base.size); in lima_heap_alloc()
37 dma_resv_lock(bo->base.base.resv, NULL); in lima_heap_alloc()
45 dma_resv_unlock(bo->base.base.resv); in lima_heap_alloc()
59 dma_resv_unlock(bo->base.base.resv); in lima_heap_alloc()
65 dma_resv_unlock(bo->base.base.resv); in lima_heap_alloc()
236 bo->base.base.funcs = &lima_gem_funcs; in lima_gem_create_object()
238 return &bo->base.base; in lima_gem_create_object()
276 &bo->base.base, in lima_gem_sync_bo()
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/ |
| H A D | nv50.c | 33 struct nvkm_instmem base; member
46 struct nvkm_instobj base; member
68 imem->addr = base; in nv50_instobj_wr32_slow()
88 imem->addr = base; in nv50_instobj_rd32_slow()
141 mutex_lock(&imem->base.mutex); in nv50_instobj_kmap()
163 mutex_lock(&imem->base.mutex); in nv50_instobj_kmap()
168 mutex_lock(&imem->base.mutex); in nv50_instobj_kmap()
210 iobj->base.memory.ptrs = NULL; in nv50_instobj_release()
364 *pmemory = &iobj->base.memory; in nv50_instobj_wrap()
366 nvkm_instobj_ctor(&nv50_instobj_func, &imem->base, &iobj->base); in nv50_instobj_wrap()
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| /openbmc/u-boot/drivers/serial/ |
| H A D | serial_stm32.c | 56 u32 cr1 = plat->base + CR1_OFFSET(stm32f4); in stm32_serial_setconfig()
103 fdt_addr_t base = plat->base; in stm32_serial_getc() local
111 setbits_le32(base + ICR_OFFSET, in stm32_serial_getc()
114 readl(base + RDR_OFFSET(stm32f4)); in stm32_serial_getc()
118 return readl(base + RDR_OFFSET(stm32f4)); in stm32_serial_getc()
130 writel(c, base + TDR_OFFSET(stm32f4)); in _stm32_serial_putc()
146 fdt_addr_t base = plat->base; in stm32_serial_pending() local
219 plat->base = devfdt_get_addr(dev); in stm32_serial_ofdata_to_platdata()
220 if (plat->base == FDT_ADDR_T_NONE) in stm32_serial_ofdata_to_platdata()
268 _stm32_serial_init(base, uart_info); in _debug_uart_init()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_dio_link_encoder.c | 44 enc10->base.ctx
46 enc10->base.ctx->logger
199 enc10->base.funcs = &dcn32_link_enc_funcs; in dcn32_link_encoder_construct()
200 enc10->base.ctx = init_data->ctx; in dcn32_link_encoder_construct()
201 enc10->base.id = init_data->encoder; in dcn32_link_encoder_construct()
203 enc10->base.hpd_source = init_data->hpd_source; in dcn32_link_encoder_construct()
204 enc10->base.connector = init_data->connector; in dcn32_link_encoder_construct()
211 enc10->base.features = *enc_features; in dcn32_link_encoder_construct()
224 enc10->base.output_signals = in dcn32_link_encoder_construct()
239 switch (enc10->base.transmitter) { in dcn32_link_encoder_construct()
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| /openbmc/linux/arch/x86/mm/ |
| H A D | amdtopology.c | 83 u64 base, limit; in amd_numa_init() local
96 base, limit); in amd_numa_init()
102 i, base); in amd_numa_init()
122 if (limit <= base) in amd_numa_init()
125 base >>= 16; in amd_numa_init()
126 base <<= 24; in amd_numa_init()
128 if (base < start) in amd_numa_init()
129 base = start; in amd_numa_init()
132 if (limit == base) { in amd_numa_init()
136 if (limit < base) { in amd_numa_init()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn316/ |
| H A D | dcn316_resource.c | 919 return &dpp->base; in dcn31_dpp_create()
939 return &opp->base; in dcn31_opp_create()
1012 return &mpc30->base; in dcn31_mpc_create()
1066 return &tgn10->base; in dcn31_timing_generator_create()
1246 return &enc1->base; in dcn316_stream_encoder_create()
1398 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); in dcn316_resource_destruct()
1425 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn316_resource_destruct()
1567 return &dsc->base; in dcn31_dsc_create()
1741 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
1742 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
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| /openbmc/linux/drivers/media/platform/mediatek/jpeg/ |
| H A D | mtk_jpeg_dec_hw.c | 248 writel(0, base + JPGDEC_REG_TRIG); in mtk_jpeg_dec_start()
255 writel(0x00, base + JPGDEC_REG_RESET); in mtk_jpeg_dec_soft_reset()
256 writel(0x01, base + JPGDEC_REG_RESET); in mtk_jpeg_dec_soft_reset()
261 writel(0x00, base + JPGDEC_REG_RESET); in mtk_jpeg_dec_hard_reset()
262 writel(0x10, base + JPGDEC_REG_RESET); in mtk_jpeg_dec_hard_reset()
267 mtk_jpeg_dec_soft_reset(base); in mtk_jpeg_dec_reset()
268 mtk_jpeg_dec_hard_reset(base); in mtk_jpeg_dec_reset()
348 writel(val, base + JPGDEC_REG_COMP_ID); in mtk_jpeg_dec_set_comp_id()
376 writel(val, base + JPGDEC_REG_QT_ID); in mtk_jpeg_dec_set_q_table()
403 writel(val, base + JPGDEC_REG_DU_NUM); in mtk_jpeg_dec_set_sampling_factor()
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| /openbmc/linux/include/sound/ |
| H A D | snd_wavefront.h | 55 #define mpu_data_port base
58 #define data_port base + 2
70 #define fx_status base + 8
71 #define fx_op base + 8
72 #define fx_lcr base + 9
73 #define fx_dsp_addr base + 0xa
74 #define fx_dsp_page base + 0xb
75 #define fx_dsp_lsb base + 0xc
76 #define fx_dsp_msb base + 0xd
77 #define fx_mod_addr base + 0xe
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| /openbmc/qemu/hw/tricore/ |
| H A D | tc27x_soc.c | 71 hwaddr base, hwaddr size) in make_rom() argument
82 hwaddr base, hwaddr size) in make_ram() argument
93 MemoryRegion *orig, hwaddr base) in make_alias() argument
147 sc->memmap[TC27XD_PSPRX].base); in tc27x_soc_init_memory_mapping()
149 sc->memmap[TC27XD_DSPRX].base); in tc27x_soc_init_memory_mapping()
169 sc->memmap[TC27XD_PFLASH0_U].base); in tc27x_soc_init_memory_mapping()
171 sc->memmap[TC27XD_PFLASH1_U].base); in tc27x_soc_init_memory_mapping()
173 sc->memmap[TC27XD_OLDA_U].base); in tc27x_soc_init_memory_mapping()
175 sc->memmap[TC27XD_BROM_U].base); in tc27x_soc_init_memory_mapping()
177 sc->memmap[TC27XD_LMURAM_U].base); in tc27x_soc_init_memory_mapping()
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| /openbmc/linux/drivers/pmdomain/ti/ |
| H A D | omap_prm.c | 54 u32 base; member
68 void __iomem *base; member
157 .name = "mpu", .base = 0x4a306300,
166 .name = "abe", .base = 0x4a306500,
186 .name = "cam", .base = 0x4a307000,
190 .name = "dss", .base = 0x4a307100,
194 .name = "gfx", .base = 0x4a307200,
215 .name = "emu", .base = 0x4a307900,
956 if (IS_ERR(prm->base)) in omap_prm_probe()
957 return PTR_ERR(prm->base); in omap_prm_probe()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_resource.c | 496 return &ipp->base; in dcn21_ipp_create()
511 return &dpp->base; in dcn21_dpp_create()
708 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); in dcn21_resource_destruct()
735 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); in dcn21_resource_destruct()
1056 return &opp->base; in dcn21_opp_create()
1077 return &tgn10->base; in dcn21_timing_generator_create()
1094 return &mpc20->base; in dcn21_mpc_create()
1119 return &dsc->base; in dcn21_dsc_create()
1170 return &enc1->base; in dcn21_stream_encoder_create()
1428 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
[all …]
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| /openbmc/linux/drivers/virtio/ |
| H A D | virtio_mmio.c | 89 void __iomem *base; member
153 void __iomem *base = vm_dev->base + VIRTIO_MMIO_CONFIG; in vm_get() local
163 ptr[i] = readb(base + offset + i); in vm_get()
169 b = readb(base + offset); in vm_get()
195 void __iomem *base = vm_dev->base + VIRTIO_MMIO_CONFIG; in vm_set() local
213 writeb(b, base + offset); in vm_set()
634 if (IS_ERR(vm_dev->base)) { in virtio_mmio_probe()
635 rc = PTR_ERR(vm_dev->base); in virtio_mmio_probe()
726 long long base, size; in vm_cmdline_set() local
736 &base, &irq, &consumed, in vm_cmdline_set()
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| /openbmc/u-boot/drivers/pch/ |
| H A D | pch9.c | 26 u32 base; in pch9_get_gpio_base() local
38 dm_pci_read_config32(dev, GPIO_BASE, &base); in pch9_get_gpio_base()
39 if (base == 0x00000000 || base == 0xffffffff) { in pch9_get_gpio_base()
50 *gbasep = base & 1 ? base & ~3 : base & ~15; in pch9_get_gpio_base()
57 u32 base; in pch9_get_io_base() local
59 dm_pci_read_config32(dev, IO_BASE, &base); in pch9_get_io_base()
60 if (base == 0x00000000 || base == 0xffffffff) { in pch9_get_io_base()
65 *iobasep = base & 1 ? base & ~3 : base & ~15; in pch9_get_io_base()
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| /openbmc/linux/arch/x86/kernel/cpu/mtrr/ |
| H A D | if.c | 54 base >>= PAGE_SHIFT; in mtrr_file_add()
73 base >>= PAGE_SHIFT; in mtrr_file_del()
146 base >>= PAGE_SHIFT; in mtrr_write()
159 unsigned long base; in mtrr_ioctl() local
196 err = get_user(sentry.base, &s32->base); in mtrr_ioctl()
209 err |= get_user(gentry.base, &g32->base); in mtrr_ioctl()
261 gentry.base = base << PAGE_SHIFT; in mtrr_ioctl()
305 gentry.base = base; in mtrr_ioctl()
327 err = put_user(gentry.base, &g32->base); in mtrr_ioctl()
362 unsigned long base, size; in mtrr_seq_show() local
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