11a59d1b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
206ff14c0STony Prisk /*
306ff14c0STony Prisk * arch/arm/mach-vt8500/irq.c
406ff14c0STony Prisk *
506ff14c0STony Prisk * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
606ff14c0STony Prisk * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
706ff14c0STony Prisk */
806ff14c0STony Prisk
906ff14c0STony Prisk /*
1006ff14c0STony Prisk * This file is copied and modified from the original irq.c provided by
1106ff14c0STony Prisk * Alexey Charkov. Minor changes have been made for Device Tree Support.
1206ff14c0STony Prisk */
1306ff14c0STony Prisk
1406ff14c0STony Prisk #include <linux/slab.h>
1506ff14c0STony Prisk #include <linux/io.h>
1606ff14c0STony Prisk #include <linux/irq.h>
1741a83e06SJoel Porquet #include <linux/irqchip.h>
1806ff14c0STony Prisk #include <linux/irqdomain.h>
1906ff14c0STony Prisk #include <linux/interrupt.h>
2006ff14c0STony Prisk #include <linux/bitops.h>
2106ff14c0STony Prisk
2206ff14c0STony Prisk #include <linux/of.h>
2306ff14c0STony Prisk #include <linux/of_irq.h>
2406ff14c0STony Prisk #include <linux/of_address.h>
2506ff14c0STony Prisk
2606ff14c0STony Prisk #include <asm/irq.h>
2706ff14c0STony Prisk #include <asm/exception.h>
2806ff14c0STony Prisk #include <asm/mach/irq.h>
2906ff14c0STony Prisk
3006ff14c0STony Prisk #define VT8500_ICPC_IRQ 0x20
3106ff14c0STony Prisk #define VT8500_ICPC_FIQ 0x24
3206ff14c0STony Prisk #define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
3306ff14c0STony Prisk #define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */
3406ff14c0STony Prisk
3506ff14c0STony Prisk /* ICPC */
3606ff14c0STony Prisk #define ICPC_MASK 0x3F
3706ff14c0STony Prisk #define ICPC_ROTATE BIT(6)
3806ff14c0STony Prisk
3906ff14c0STony Prisk /* IC_DCTR */
4006ff14c0STony Prisk #define ICDC_IRQ 0x00
4106ff14c0STony Prisk #define ICDC_FIQ 0x01
4206ff14c0STony Prisk #define ICDC_DSS0 0x02
4306ff14c0STony Prisk #define ICDC_DSS1 0x03
4406ff14c0STony Prisk #define ICDC_DSS2 0x04
4506ff14c0STony Prisk #define ICDC_DSS3 0x05
4606ff14c0STony Prisk #define ICDC_DSS4 0x06
4706ff14c0STony Prisk #define ICDC_DSS5 0x07
4806ff14c0STony Prisk
4906ff14c0STony Prisk #define VT8500_INT_DISABLE 0
5006ff14c0STony Prisk #define VT8500_INT_ENABLE BIT(3)
5106ff14c0STony Prisk
5206ff14c0STony Prisk #define VT8500_TRIGGER_HIGH 0
5306ff14c0STony Prisk #define VT8500_TRIGGER_RISING BIT(5)
5406ff14c0STony Prisk #define VT8500_TRIGGER_FALLING BIT(6)
5506ff14c0STony Prisk #define VT8500_EDGE ( VT8500_TRIGGER_RISING \
5606ff14c0STony Prisk | VT8500_TRIGGER_FALLING)
5706ff14c0STony Prisk
5806ff14c0STony Prisk /* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
5906ff14c0STony Prisk #define VT8500_INTC_MAX 2
6006ff14c0STony Prisk
6106ff14c0STony Prisk struct vt8500_irq_data {
6206ff14c0STony Prisk void __iomem *base; /* IO Memory base address */
6306ff14c0STony Prisk struct irq_domain *domain; /* Domain for this controller */
6406ff14c0STony Prisk };
6506ff14c0STony Prisk
6606ff14c0STony Prisk /* Global variable for accessing io-mem addresses */
6706ff14c0STony Prisk static struct vt8500_irq_data intc[VT8500_INTC_MAX];
6806ff14c0STony Prisk static u32 active_cnt = 0;
6906ff14c0STony Prisk
vt8500_irq_mask(struct irq_data * d)7006ff14c0STony Prisk static void vt8500_irq_mask(struct irq_data *d)
7106ff14c0STony Prisk {
7206ff14c0STony Prisk struct vt8500_irq_data *priv = d->domain->host_data;
7306ff14c0STony Prisk void __iomem *base = priv->base;
7406ff14c0STony Prisk void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
7506ff14c0STony Prisk u8 edge, dctr;
7606ff14c0STony Prisk u32 status;
7706ff14c0STony Prisk
7806ff14c0STony Prisk edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
7906ff14c0STony Prisk if (edge) {
8006ff14c0STony Prisk status = readl(stat_reg);
8106ff14c0STony Prisk
8206ff14c0STony Prisk status |= (1 << (d->hwirq & 0x1f));
8306ff14c0STony Prisk writel(status, stat_reg);
8406ff14c0STony Prisk } else {
8506ff14c0STony Prisk dctr = readb(base + VT8500_ICDC + d->hwirq);
8606ff14c0STony Prisk dctr &= ~VT8500_INT_ENABLE;
8706ff14c0STony Prisk writeb(dctr, base + VT8500_ICDC + d->hwirq);
8806ff14c0STony Prisk }
8906ff14c0STony Prisk }
9006ff14c0STony Prisk
vt8500_irq_unmask(struct irq_data * d)9106ff14c0STony Prisk static void vt8500_irq_unmask(struct irq_data *d)
9206ff14c0STony Prisk {
9306ff14c0STony Prisk struct vt8500_irq_data *priv = d->domain->host_data;
9406ff14c0STony Prisk void __iomem *base = priv->base;
9506ff14c0STony Prisk u8 dctr;
9606ff14c0STony Prisk
9706ff14c0STony Prisk dctr = readb(base + VT8500_ICDC + d->hwirq);
9806ff14c0STony Prisk dctr |= VT8500_INT_ENABLE;
9906ff14c0STony Prisk writeb(dctr, base + VT8500_ICDC + d->hwirq);
10006ff14c0STony Prisk }
10106ff14c0STony Prisk
vt8500_irq_set_type(struct irq_data * d,unsigned int flow_type)10206ff14c0STony Prisk static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
10306ff14c0STony Prisk {
10406ff14c0STony Prisk struct vt8500_irq_data *priv = d->domain->host_data;
10506ff14c0STony Prisk void __iomem *base = priv->base;
10606ff14c0STony Prisk u8 dctr;
10706ff14c0STony Prisk
10806ff14c0STony Prisk dctr = readb(base + VT8500_ICDC + d->hwirq);
10906ff14c0STony Prisk dctr &= ~VT8500_EDGE;
11006ff14c0STony Prisk
11106ff14c0STony Prisk switch (flow_type) {
11206ff14c0STony Prisk case IRQF_TRIGGER_LOW:
11306ff14c0STony Prisk return -EINVAL;
11406ff14c0STony Prisk case IRQF_TRIGGER_HIGH:
11506ff14c0STony Prisk dctr |= VT8500_TRIGGER_HIGH;
116d2aa914dSThomas Gleixner irq_set_handler_locked(d, handle_level_irq);
11706ff14c0STony Prisk break;
11806ff14c0STony Prisk case IRQF_TRIGGER_FALLING:
11906ff14c0STony Prisk dctr |= VT8500_TRIGGER_FALLING;
120d2aa914dSThomas Gleixner irq_set_handler_locked(d, handle_edge_irq);
12106ff14c0STony Prisk break;
12206ff14c0STony Prisk case IRQF_TRIGGER_RISING:
12306ff14c0STony Prisk dctr |= VT8500_TRIGGER_RISING;
124d2aa914dSThomas Gleixner irq_set_handler_locked(d, handle_edge_irq);
12506ff14c0STony Prisk break;
12606ff14c0STony Prisk }
12706ff14c0STony Prisk writeb(dctr, base + VT8500_ICDC + d->hwirq);
12806ff14c0STony Prisk
12906ff14c0STony Prisk return 0;
13006ff14c0STony Prisk }
13106ff14c0STony Prisk
13206ff14c0STony Prisk static struct irq_chip vt8500_irq_chip = {
13306ff14c0STony Prisk .name = "vt8500",
13406ff14c0STony Prisk .irq_ack = vt8500_irq_mask,
13506ff14c0STony Prisk .irq_mask = vt8500_irq_mask,
13606ff14c0STony Prisk .irq_unmask = vt8500_irq_unmask,
13706ff14c0STony Prisk .irq_set_type = vt8500_irq_set_type,
13806ff14c0STony Prisk };
13906ff14c0STony Prisk
vt8500_init_irq_hw(void __iomem * base)14006ff14c0STony Prisk static void __init vt8500_init_irq_hw(void __iomem *base)
14106ff14c0STony Prisk {
14206ff14c0STony Prisk u32 i;
14306ff14c0STony Prisk
14406ff14c0STony Prisk /* Enable rotating priority for IRQ */
14506ff14c0STony Prisk writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
14606ff14c0STony Prisk writel(0x00, base + VT8500_ICPC_FIQ);
14706ff14c0STony Prisk
14806ff14c0STony Prisk /* Disable all interrupts and route them to IRQ */
14906ff14c0STony Prisk for (i = 0; i < 64; i++)
15006ff14c0STony Prisk writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
15106ff14c0STony Prisk }
15206ff14c0STony Prisk
vt8500_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)15306ff14c0STony Prisk static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
15406ff14c0STony Prisk irq_hw_number_t hw)
15506ff14c0STony Prisk {
15606ff14c0STony Prisk irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
15706ff14c0STony Prisk
15806ff14c0STony Prisk return 0;
15906ff14c0STony Prisk }
16006ff14c0STony Prisk
16196009736SKrzysztof Kozlowski static const struct irq_domain_ops vt8500_irq_domain_ops = {
16206ff14c0STony Prisk .map = vt8500_irq_map,
16306ff14c0STony Prisk .xlate = irq_domain_xlate_onecell,
16406ff14c0STony Prisk };
16506ff14c0STony Prisk
vt8500_handle_irq(struct pt_regs * regs)1668783dd3aSStephen Boyd static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
16706ff14c0STony Prisk {
16806ff14c0STony Prisk u32 stat, i;
1690beb6504SMarc Zyngier int irqnr;
17006ff14c0STony Prisk void __iomem *base;
17106ff14c0STony Prisk
17206ff14c0STony Prisk /* Loop through each active controller */
17306ff14c0STony Prisk for (i=0; i<active_cnt; i++) {
17406ff14c0STony Prisk base = intc[i].base;
17506ff14c0STony Prisk irqnr = readl_relaxed(base) & 0x3F;
17606ff14c0STony Prisk /*
17706ff14c0STony Prisk Highest Priority register default = 63, so check that this
17806ff14c0STony Prisk is a real interrupt by checking the status register
17906ff14c0STony Prisk */
18006ff14c0STony Prisk if (irqnr == 63) {
18106ff14c0STony Prisk stat = readl_relaxed(base + VT8500_ICIS + 4);
18206ff14c0STony Prisk if (!(stat & BIT(31)))
18306ff14c0STony Prisk continue;
18406ff14c0STony Prisk }
18506ff14c0STony Prisk
186*0953fb26SMark Rutland generic_handle_domain_irq(intc[i].domain, irqnr);
18706ff14c0STony Prisk }
18806ff14c0STony Prisk }
18906ff14c0STony Prisk
vt8500_irq_init(struct device_node * node,struct device_node * parent)190e658718eSAxel Lin static int __init vt8500_irq_init(struct device_node *node,
191e658718eSAxel Lin struct device_node *parent)
19206ff14c0STony Prisk {
19306ff14c0STony Prisk int irq, i;
19406ff14c0STony Prisk struct device_node *np = node;
19506ff14c0STony Prisk
19606ff14c0STony Prisk if (active_cnt == VT8500_INTC_MAX) {
19706ff14c0STony Prisk pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
19806ff14c0STony Prisk __func__);
19906ff14c0STony Prisk goto out;
20006ff14c0STony Prisk }
20106ff14c0STony Prisk
20206ff14c0STony Prisk intc[active_cnt].base = of_iomap(np, 0);
20306ff14c0STony Prisk intc[active_cnt].domain = irq_domain_add_linear(node, 64,
20406ff14c0STony Prisk &vt8500_irq_domain_ops, &intc[active_cnt]);
20506ff14c0STony Prisk
20606ff14c0STony Prisk if (!intc[active_cnt].base) {
20706ff14c0STony Prisk pr_err("%s: Unable to map IO memory\n", __func__);
20806ff14c0STony Prisk goto out;
20906ff14c0STony Prisk }
21006ff14c0STony Prisk
21106ff14c0STony Prisk if (!intc[active_cnt].domain) {
21206ff14c0STony Prisk pr_err("%s: Unable to add irq domain!\n", __func__);
21306ff14c0STony Prisk goto out;
21406ff14c0STony Prisk }
21506ff14c0STony Prisk
21606ff14c0STony Prisk set_handle_irq(vt8500_handle_irq);
21706ff14c0STony Prisk
21806ff14c0STony Prisk vt8500_init_irq_hw(intc[active_cnt].base);
21906ff14c0STony Prisk
22006ff14c0STony Prisk pr_info("vt8500-irq: Added interrupt controller\n");
22106ff14c0STony Prisk
22206ff14c0STony Prisk active_cnt++;
22306ff14c0STony Prisk
22406ff14c0STony Prisk /* check if this is a slaved controller */
22506ff14c0STony Prisk if (of_irq_count(np) != 0) {
22606ff14c0STony Prisk /* check that we have the correct number of interrupts */
22706ff14c0STony Prisk if (of_irq_count(np) != 8) {
22806ff14c0STony Prisk pr_err("%s: Incorrect IRQ map for slaved controller\n",
22906ff14c0STony Prisk __func__);
23006ff14c0STony Prisk return -EINVAL;
23106ff14c0STony Prisk }
23206ff14c0STony Prisk
23306ff14c0STony Prisk for (i = 0; i < 8; i++) {
23406ff14c0STony Prisk irq = irq_of_parse_and_map(np, i);
23506ff14c0STony Prisk enable_irq(irq);
23606ff14c0STony Prisk }
23706ff14c0STony Prisk
23806ff14c0STony Prisk pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
23906ff14c0STony Prisk }
24006ff14c0STony Prisk out:
24106ff14c0STony Prisk return 0;
24206ff14c0STony Prisk }
24306ff14c0STony Prisk
24406ff14c0STony Prisk IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);
245