183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2ae74de0dSPatrice Chotard /*
3ae74de0dSPatrice Chotard * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4ae74de0dSPatrice Chotard * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5ae74de0dSPatrice Chotard */
6ae74de0dSPatrice Chotard
7ae74de0dSPatrice Chotard #include <common.h>
8ae74de0dSPatrice Chotard #include <clk.h>
9ae74de0dSPatrice Chotard #include <dm.h>
10*f828fa4dSPatrice Chotard #include <reset.h>
11ae74de0dSPatrice Chotard #include <serial.h>
12215c8bedSPatrick Delaunay #include <watchdog.h>
13215c8bedSPatrick Delaunay #include <asm/io.h>
14ae74de0dSPatrice Chotard #include <asm/arch/stm32.h>
15ae74de0dSPatrice Chotard #include "serial_stm32.h"
16ae74de0dSPatrice Chotard
_stm32_serial_setbrg(fdt_addr_t base,struct stm32_uart_info * uart_info,u32 clock_rate,int baudrate)17215c8bedSPatrick Delaunay static void _stm32_serial_setbrg(fdt_addr_t base,
18215c8bedSPatrick Delaunay struct stm32_uart_info *uart_info,
19215c8bedSPatrick Delaunay u32 clock_rate,
20215c8bedSPatrick Delaunay int baudrate)
21ae74de0dSPatrice Chotard {
22215c8bedSPatrick Delaunay bool stm32f4 = uart_info->stm32f4;
23ae74de0dSPatrice Chotard u32 int_div, mantissa, fraction, oversampling;
24ae74de0dSPatrice Chotard
25215c8bedSPatrick Delaunay int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
26ae74de0dSPatrice Chotard
27ae74de0dSPatrice Chotard if (int_div < 16) {
28ae74de0dSPatrice Chotard oversampling = 8;
29ae74de0dSPatrice Chotard setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
30ae74de0dSPatrice Chotard } else {
31ae74de0dSPatrice Chotard oversampling = 16;
32ae74de0dSPatrice Chotard clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
33ae74de0dSPatrice Chotard }
34ae74de0dSPatrice Chotard
35ae74de0dSPatrice Chotard mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
36ae74de0dSPatrice Chotard fraction = int_div % oversampling;
37ae74de0dSPatrice Chotard
38ae74de0dSPatrice Chotard writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
39215c8bedSPatrick Delaunay }
40215c8bedSPatrick Delaunay
stm32_serial_setbrg(struct udevice * dev,int baudrate)41215c8bedSPatrick Delaunay static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
42215c8bedSPatrick Delaunay {
43215c8bedSPatrick Delaunay struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
44215c8bedSPatrick Delaunay
45215c8bedSPatrick Delaunay _stm32_serial_setbrg(plat->base, plat->uart_info,
46215c8bedSPatrick Delaunay plat->clock_rate, baudrate);
47ae74de0dSPatrice Chotard
48ae74de0dSPatrice Chotard return 0;
49ae74de0dSPatrice Chotard }
50ae74de0dSPatrice Chotard
stm32_serial_setconfig(struct udevice * dev,uint serial_config)51fbd5c72dSPatrice Chotard static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
52bc709a41SPatrick Delaunay {
53bc709a41SPatrick Delaunay struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
54bc709a41SPatrick Delaunay bool stm32f4 = plat->uart_info->stm32f4;
55bc709a41SPatrick Delaunay u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
56bc709a41SPatrick Delaunay u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
57bc709a41SPatrick Delaunay u32 config = 0;
58fbd5c72dSPatrice Chotard uint parity = SERIAL_GET_PARITY(serial_config);
59fbd5c72dSPatrice Chotard uint bits = SERIAL_GET_BITS(serial_config);
60fbd5c72dSPatrice Chotard uint stop = SERIAL_GET_STOP(serial_config);
61bc709a41SPatrick Delaunay
62fbd5c72dSPatrice Chotard /*
63fbd5c72dSPatrice Chotard * only parity config is implemented, check if other serial settings
64fbd5c72dSPatrice Chotard * are the default one.
65fbd5c72dSPatrice Chotard * (STM32F4 serial IP didn't support parity setting)
66fbd5c72dSPatrice Chotard */
67fbd5c72dSPatrice Chotard if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
68fbd5c72dSPatrice Chotard return -ENOTSUPP; /* not supported in driver*/
69bc709a41SPatrick Delaunay
70bc709a41SPatrick Delaunay clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
71bc709a41SPatrick Delaunay /* update usart configuration (uart need to be disable)
72fbd5c72dSPatrice Chotard * PCE: parity check enable
73bc709a41SPatrick Delaunay * PS : '0' : Even / '1' : Odd
74bc709a41SPatrick Delaunay * M[1:0] = '00' : 8 Data bits
75bc709a41SPatrick Delaunay * M[1:0] = '01' : 9 Data bits with parity
76bc709a41SPatrick Delaunay */
77bc709a41SPatrick Delaunay switch (parity) {
78bc709a41SPatrick Delaunay default:
79bc709a41SPatrick Delaunay case SERIAL_PAR_NONE:
80bc709a41SPatrick Delaunay config = 0;
81bc709a41SPatrick Delaunay break;
82bc709a41SPatrick Delaunay case SERIAL_PAR_ODD:
83bc709a41SPatrick Delaunay config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
84bc709a41SPatrick Delaunay break;
85bc709a41SPatrick Delaunay case SERIAL_PAR_EVEN:
86bc709a41SPatrick Delaunay config = USART_CR1_PCE | USART_CR1_M0;
87bc709a41SPatrick Delaunay break;
88bc709a41SPatrick Delaunay }
89fbd5c72dSPatrice Chotard
90bc709a41SPatrick Delaunay clrsetbits_le32(cr1,
91bc709a41SPatrick Delaunay USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
92bc709a41SPatrick Delaunay USART_CR1_M0,
93bc709a41SPatrick Delaunay config);
94bc709a41SPatrick Delaunay setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
95bc709a41SPatrick Delaunay
96bc709a41SPatrick Delaunay return 0;
97bc709a41SPatrick Delaunay }
98bc709a41SPatrick Delaunay
stm32_serial_getc(struct udevice * dev)99ae74de0dSPatrice Chotard static int stm32_serial_getc(struct udevice *dev)
100ae74de0dSPatrice Chotard {
101ae74de0dSPatrice Chotard struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
102ae74de0dSPatrice Chotard bool stm32f4 = plat->uart_info->stm32f4;
103ae74de0dSPatrice Chotard fdt_addr_t base = plat->base;
1047b3b74d3SPatrice Chotard u32 isr = readl(base + ISR_OFFSET(stm32f4));
105ae74de0dSPatrice Chotard
106be1a6f77SPatrice Chotard if ((isr & USART_ISR_RXNE) == 0)
107ae74de0dSPatrice Chotard return -EAGAIN;
108ae74de0dSPatrice Chotard
109bc709a41SPatrick Delaunay if (isr & (USART_ISR_PE | USART_ISR_ORE)) {
1107b3b74d3SPatrice Chotard if (!stm32f4)
111bc709a41SPatrick Delaunay setbits_le32(base + ICR_OFFSET,
112bc709a41SPatrick Delaunay USART_ICR_PCECF | USART_ICR_ORECF);
1137b3b74d3SPatrice Chotard else
1147b3b74d3SPatrice Chotard readl(base + RDR_OFFSET(stm32f4));
1157b3b74d3SPatrice Chotard return -EIO;
1167b3b74d3SPatrice Chotard }
1177b3b74d3SPatrice Chotard
118ae74de0dSPatrice Chotard return readl(base + RDR_OFFSET(stm32f4));
119ae74de0dSPatrice Chotard }
120ae74de0dSPatrice Chotard
_stm32_serial_putc(fdt_addr_t base,struct stm32_uart_info * uart_info,const char c)121215c8bedSPatrick Delaunay static int _stm32_serial_putc(fdt_addr_t base,
122215c8bedSPatrick Delaunay struct stm32_uart_info *uart_info,
123215c8bedSPatrick Delaunay const char c)
124ae74de0dSPatrice Chotard {
125215c8bedSPatrick Delaunay bool stm32f4 = uart_info->stm32f4;
126ae74de0dSPatrice Chotard
127be1a6f77SPatrice Chotard if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
128ae74de0dSPatrice Chotard return -EAGAIN;
129ae74de0dSPatrice Chotard
130ae74de0dSPatrice Chotard writel(c, base + TDR_OFFSET(stm32f4));
131ae74de0dSPatrice Chotard
132ae74de0dSPatrice Chotard return 0;
133ae74de0dSPatrice Chotard }
134ae74de0dSPatrice Chotard
stm32_serial_putc(struct udevice * dev,const char c)135215c8bedSPatrick Delaunay static int stm32_serial_putc(struct udevice *dev, const char c)
136215c8bedSPatrick Delaunay {
137215c8bedSPatrick Delaunay struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
138215c8bedSPatrick Delaunay
139215c8bedSPatrick Delaunay return _stm32_serial_putc(plat->base, plat->uart_info, c);
140215c8bedSPatrick Delaunay }
141215c8bedSPatrick Delaunay
stm32_serial_pending(struct udevice * dev,bool input)142ae74de0dSPatrice Chotard static int stm32_serial_pending(struct udevice *dev, bool input)
143ae74de0dSPatrice Chotard {
144ae74de0dSPatrice Chotard struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
145ae74de0dSPatrice Chotard bool stm32f4 = plat->uart_info->stm32f4;
146ae74de0dSPatrice Chotard fdt_addr_t base = plat->base;
147ae74de0dSPatrice Chotard
148ae74de0dSPatrice Chotard if (input)
149ae74de0dSPatrice Chotard return readl(base + ISR_OFFSET(stm32f4)) &
150be1a6f77SPatrice Chotard USART_ISR_RXNE ? 1 : 0;
151ae74de0dSPatrice Chotard else
152ae74de0dSPatrice Chotard return readl(base + ISR_OFFSET(stm32f4)) &
153be1a6f77SPatrice Chotard USART_ISR_TXE ? 0 : 1;
154ae74de0dSPatrice Chotard }
155ae74de0dSPatrice Chotard
_stm32_serial_init(fdt_addr_t base,struct stm32_uart_info * uart_info)156215c8bedSPatrick Delaunay static void _stm32_serial_init(fdt_addr_t base,
157215c8bedSPatrick Delaunay struct stm32_uart_info *uart_info)
158215c8bedSPatrick Delaunay {
159215c8bedSPatrick Delaunay bool stm32f4 = uart_info->stm32f4;
160215c8bedSPatrick Delaunay u8 uart_enable_bit = uart_info->uart_enable_bit;
161215c8bedSPatrick Delaunay
162215c8bedSPatrick Delaunay /* Disable uart-> enable fifo -> enable uart */
163215c8bedSPatrick Delaunay clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
164215c8bedSPatrick Delaunay BIT(uart_enable_bit));
165215c8bedSPatrick Delaunay if (uart_info->has_fifo)
166215c8bedSPatrick Delaunay setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
167215c8bedSPatrick Delaunay setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
168215c8bedSPatrick Delaunay BIT(uart_enable_bit));
169215c8bedSPatrick Delaunay }
170215c8bedSPatrick Delaunay
stm32_serial_probe(struct udevice * dev)171ae74de0dSPatrice Chotard static int stm32_serial_probe(struct udevice *dev)
172ae74de0dSPatrice Chotard {
173ae74de0dSPatrice Chotard struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
174ae74de0dSPatrice Chotard struct clk clk;
175*f828fa4dSPatrice Chotard struct reset_ctl reset;
176ae74de0dSPatrice Chotard int ret;
177ae74de0dSPatrice Chotard
178ae74de0dSPatrice Chotard plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
179ae74de0dSPatrice Chotard
180ae74de0dSPatrice Chotard ret = clk_get_by_index(dev, 0, &clk);
181ae74de0dSPatrice Chotard if (ret < 0)
182ae74de0dSPatrice Chotard return ret;
183ae74de0dSPatrice Chotard
184ae74de0dSPatrice Chotard ret = clk_enable(&clk);
185ae74de0dSPatrice Chotard if (ret) {
186ae74de0dSPatrice Chotard dev_err(dev, "failed to enable clock\n");
187ae74de0dSPatrice Chotard return ret;
188ae74de0dSPatrice Chotard }
189ae74de0dSPatrice Chotard
190*f828fa4dSPatrice Chotard ret = reset_get_by_index(dev, 0, &reset);
191*f828fa4dSPatrice Chotard if (!ret) {
192*f828fa4dSPatrice Chotard reset_assert(&reset);
193*f828fa4dSPatrice Chotard udelay(2);
194*f828fa4dSPatrice Chotard reset_deassert(&reset);
195*f828fa4dSPatrice Chotard }
196*f828fa4dSPatrice Chotard
197ae74de0dSPatrice Chotard plat->clock_rate = clk_get_rate(&clk);
198ae74de0dSPatrice Chotard if (plat->clock_rate < 0) {
199ae74de0dSPatrice Chotard clk_disable(&clk);
200ae74de0dSPatrice Chotard return plat->clock_rate;
201ae74de0dSPatrice Chotard };
202ae74de0dSPatrice Chotard
203215c8bedSPatrick Delaunay _stm32_serial_init(plat->base, plat->uart_info);
204ae74de0dSPatrice Chotard
205ae74de0dSPatrice Chotard return 0;
206ae74de0dSPatrice Chotard }
207ae74de0dSPatrice Chotard
208ae74de0dSPatrice Chotard static const struct udevice_id stm32_serial_id[] = {
209ae74de0dSPatrice Chotard { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
210ae74de0dSPatrice Chotard { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
211ae74de0dSPatrice Chotard { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
212ae74de0dSPatrice Chotard {}
213ae74de0dSPatrice Chotard };
214ae74de0dSPatrice Chotard
stm32_serial_ofdata_to_platdata(struct udevice * dev)215ae74de0dSPatrice Chotard static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
216ae74de0dSPatrice Chotard {
217ae74de0dSPatrice Chotard struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
218ae74de0dSPatrice Chotard
219ae74de0dSPatrice Chotard plat->base = devfdt_get_addr(dev);
220ae74de0dSPatrice Chotard if (plat->base == FDT_ADDR_T_NONE)
221ae74de0dSPatrice Chotard return -EINVAL;
222ae74de0dSPatrice Chotard
223ae74de0dSPatrice Chotard return 0;
224ae74de0dSPatrice Chotard }
225ae74de0dSPatrice Chotard
226ae74de0dSPatrice Chotard static const struct dm_serial_ops stm32_serial_ops = {
227ae74de0dSPatrice Chotard .putc = stm32_serial_putc,
228ae74de0dSPatrice Chotard .pending = stm32_serial_pending,
229ae74de0dSPatrice Chotard .getc = stm32_serial_getc,
230ae74de0dSPatrice Chotard .setbrg = stm32_serial_setbrg,
231fbd5c72dSPatrice Chotard .setconfig = stm32_serial_setconfig
232ae74de0dSPatrice Chotard };
233ae74de0dSPatrice Chotard
234ae74de0dSPatrice Chotard U_BOOT_DRIVER(serial_stm32) = {
235ae74de0dSPatrice Chotard .name = "serial_stm32",
236ae74de0dSPatrice Chotard .id = UCLASS_SERIAL,
237ae74de0dSPatrice Chotard .of_match = of_match_ptr(stm32_serial_id),
238ae74de0dSPatrice Chotard .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
239ae74de0dSPatrice Chotard .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
240ae74de0dSPatrice Chotard .ops = &stm32_serial_ops,
241ae74de0dSPatrice Chotard .probe = stm32_serial_probe,
24246879196SBin Meng #if !CONFIG_IS_ENABLED(OF_CONTROL)
243ae74de0dSPatrice Chotard .flags = DM_FLAG_PRE_RELOC,
24446879196SBin Meng #endif
245ae74de0dSPatrice Chotard };
246215c8bedSPatrick Delaunay
247215c8bedSPatrick Delaunay #ifdef CONFIG_DEBUG_UART_STM32
248215c8bedSPatrick Delaunay #include <debug_uart.h>
_debug_uart_info(void)249215c8bedSPatrick Delaunay static inline struct stm32_uart_info *_debug_uart_info(void)
250215c8bedSPatrick Delaunay {
251215c8bedSPatrick Delaunay struct stm32_uart_info *uart_info;
252215c8bedSPatrick Delaunay
253215c8bedSPatrick Delaunay #if defined(CONFIG_STM32F4)
254215c8bedSPatrick Delaunay uart_info = &stm32f4_info;
255215c8bedSPatrick Delaunay #elif defined(CONFIG_STM32F7)
256215c8bedSPatrick Delaunay uart_info = &stm32f7_info;
257215c8bedSPatrick Delaunay #else
258215c8bedSPatrick Delaunay uart_info = &stm32h7_info;
259215c8bedSPatrick Delaunay #endif
260215c8bedSPatrick Delaunay return uart_info;
261215c8bedSPatrick Delaunay }
262215c8bedSPatrick Delaunay
_debug_uart_init(void)263215c8bedSPatrick Delaunay static inline void _debug_uart_init(void)
264215c8bedSPatrick Delaunay {
265215c8bedSPatrick Delaunay fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
266215c8bedSPatrick Delaunay struct stm32_uart_info *uart_info = _debug_uart_info();
267215c8bedSPatrick Delaunay
268215c8bedSPatrick Delaunay _stm32_serial_init(base, uart_info);
269215c8bedSPatrick Delaunay _stm32_serial_setbrg(base, uart_info,
270215c8bedSPatrick Delaunay CONFIG_DEBUG_UART_CLOCK,
271215c8bedSPatrick Delaunay CONFIG_BAUDRATE);
272215c8bedSPatrick Delaunay printf("DEBUG done\n");
273215c8bedSPatrick Delaunay }
274215c8bedSPatrick Delaunay
_debug_uart_putc(int c)275215c8bedSPatrick Delaunay static inline void _debug_uart_putc(int c)
276215c8bedSPatrick Delaunay {
277215c8bedSPatrick Delaunay fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
278215c8bedSPatrick Delaunay struct stm32_uart_info *uart_info = _debug_uart_info();
279215c8bedSPatrick Delaunay
280215c8bedSPatrick Delaunay while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
281215c8bedSPatrick Delaunay WATCHDOG_RESET();
282215c8bedSPatrick Delaunay }
283215c8bedSPatrick Delaunay
284215c8bedSPatrick Delaunay DEBUG_UART_FUNCS
285215c8bedSPatrick Delaunay #endif
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