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Searched refs:PLL (Results 151 – 175 of 294) sorted by relevance

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/openbmc/linux/drivers/clk/samsung/
H A Dclk-s3c64xx.c301 PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
303 PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
305 PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
H A Dclk-exynos7.c174 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
176 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
178 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
180 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
182 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
H A Dclk-fsd.c165 PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
167 PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
169 PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
171 PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
1480 PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll",
1640 PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
H A Dclk-exynosautov9.c353 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
355 PLL(pll_0822x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
357 PLL(pll_0822x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
359 PLL(pll_0822x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
361 PLL(pll_0822x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
1351 PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3288.c226 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
228 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
230 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
232 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
234 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
H A Dclk-rk3399.c219 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
221 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
223 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
225 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
227 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
229 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
231 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
H A Dclk-px30.c185 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
188 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
191 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
194 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
200 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0),
H A Dclk-rk3568.c314 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
317 [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
323 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
326 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
329 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
332 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
335 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
338 [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dadi,adau1701.txt15 the ADAU's PLL config pins are connected to.
H A Dpcm512x.txt26 given pll-in pin and PLL output on the given pll-out pin. An
H A Dmvebu-audio.txt14 first of those is dedicated for Audio PLL Configuration registers
H A Dfsl,sai.yaml54 - description: PLL clock source for 8kHz series
55 - description: PLL clock source for 11kHz series
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dqts-filter.sh107 * Altera SoCFPGA Clock and PLL configuration
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dairoha,en7523-scu.yaml18 PLL controller, which provides clocks for the CPU, the bus and
H A Dsamsung,exynos5410-clock.yaml18 - "fin_pll" - PLL input clock from XXTI
H A Dmaxim,max9485.txt6 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
H A Dimx6q-clock.yaml22 interrupt for oscillator read or PLL lock.
H A Damlogic,meson8b-clkc.txt17 * "ddr_pll": the DDR PLL clock
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dbrcm,bcm2835-dsi0.yaml30 - description: The DSI PLL clock feeding the DSI analog PHY
/openbmc/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,quadfs.txt4 This version contains a programmable PLL which can generate up to 216, 432
/openbmc/u-boot/doc/
H A DREADME.m68k112 CONFIG_SYS_MFD -- defines the PLL Multiplication Factor Divider
114 CONFIG_SYS_RFD -- defines the PLL Reduce Frequency Devider
/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dap80x-system-controller.txt26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,hdmi-phy.yaml38 - description: PLL reference clock
/openbmc/linux/drivers/clk/pistachio/
H A Dclk.h119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ macro
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h618-orangepi-zero3.dts50 /* Supplies VCC-PLL, so needs to be always on. */

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