clk: exynos7: Mark aclk_fsys1_200 as critical

This clock must be always enabled to allow access to any registers in
fsys1 CMU. Until proper solution based on runtime PM is applied
(similar to what w

clk: exynos7: Mark aclk_fsys1_200 as critical

This clock must be always enabled to allow access to any registers in
fsys1 CMU. Until proper solution based on runtime PM is applied
(similar to what was done for Exynos5433), mark that clock as critical
so it won't be disabled.

It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
UFS module is probed before pmic used to power that device.
In this case defer probe was happening and that clock was disabled by
UFS driver, causing whole boot to hang on next CMU access.

Fixes: 753195a749a6 ("clk: samsung: exynos7: Correct CMU_FSYS1 clocks names")
Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/linux-clk/20201024154346.9589-1-pawel.mikolaj.chmiel@gmail.com
[s.nawrocki: Added comment in the code]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: exynos7: Mark aclk_fsys1_200 as critical

commit 34138a59b92c1a30649a18ec442d2e61f3bc34dd upstream.

This clock must be always enabled to allow access to any registers in
fsys1 CMU. Until proper

clk: exynos7: Mark aclk_fsys1_200 as critical

commit 34138a59b92c1a30649a18ec442d2e61f3bc34dd upstream.

This clock must be always enabled to allow access to any registers in
fsys1 CMU. Until proper solution based on runtime PM is applied
(similar to what was done for Exynos5433), mark that clock as critical
so it won't be disabled.

It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
UFS module is probed before pmic used to power that device.
In this case defer probe was happening and that clock was disabled by
UFS driver, causing whole boot to hang on next CMU access.

Fixes: 753195a749a6 ("clk: samsung: exynos7: Correct CMU_FSYS1 clocks names")
Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/linux-clk/20201024154346.9589-1-pawel.mikolaj.chmiel@gmail.com
[s.nawrocki: Added comment in the code]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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clk: samsung: Add compile time PLL rate validators

Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. To avoid possible mistakes we can use compile
time v

clk: samsung: Add compile time PLL rate validators

Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. To avoid possible mistakes we can use compile
time validation.
The patch introduces such validators and expands all initializers
with additional input frequency parameter, required to validate rates.
Since S3C24xx PLLs requires different validators two new macros have
been introduced to deal with it. Also, since PLLs 4502 and 4508 have
different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE.

As the patch adds only compile time validators it should not have impact
on compiled code.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Fix PLL rates

Rates declared in PLL rate tables should match exactly rates calculated from
the PLL coefficients. If that is not the case, rate of the PLL's child clock
might b

clk: samsung: exynos7: Fix PLL rates

Rates declared in PLL rate tables should match exactly rates calculated from
the PLL coefficients. If that is not the case, rate of the PLL's child clock
might be set not as expected. For instance, if in the PLL rates table we have
a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
will return 393216003. If we now attempt to set rate of a PLL's child divider
clock to 393216000/2 its rate will be 131072001, rather than 196608000.
That is, the divider will be set to 3 instead of 2, because 393216003/2 is
greater than 196608000.

To fix this issue declared rates are changed to exactly match rates generated
by the PLL, as calculated from the P, M, S, K coefficients.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Constify all clock initializers

All of initialization data can be made const.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <

clk: samsung: exynos7: Constify all clock initializers

All of initialization data can be made const.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Don't gate CMU_{CCORE, FSYS0} blocks clock

This patch adds CLK_IS_CRITICAL flag to ACLK_CCORE_133 and ACLK_FSYS0_200
clocks. These clocks are critical for accessing CMU_CCORE

clk: samsung: exynos7: Don't gate CMU_{CCORE, FSYS0} blocks clock

This patch adds CLK_IS_CRITICAL flag to ACLK_CCORE_133 and ACLK_FSYS0_200
clocks. These clocks are critical for accessing CMU_CCORE and CMU_FSYS0
blocks registers. Let these clocks to be enabled all the time.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

clk: samsung: exynos7: Staticize file scope symbols

drivers/clk/samsung/clk-exynos7.c:896:33:
warning: symbol 'fixed_rate_clks_fsys0' was not declared. Should
it be static?
drivers/clk/samsung/clk-e

clk: samsung: exynos7: Staticize file scope symbols

drivers/clk/samsung/clk-exynos7.c:896:33:
warning: symbol 'fixed_rate_clks_fsys0' was not declared. Should
it be static?
drivers/clk/samsung/clk-exynos7.c:1010:33:
warning: symbol 'fixed_rate_clks_fsys1' was not declared. Should
it be static?

Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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clk: samsung: exynos7: Add required clock tree for UFS

Adding required mux/div/gate clocks for UFS controller
present on Exynos7.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: K

clk: samsung: exynos7: Add required clock tree for UFS

Adding required mux/div/gate clocks for UFS controller
present on Exynos7.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Add missing fixed_clks to cmu_info

FSYS0 fixed clocks are not added to fsys0_cmu_info, this makes
some of the usb clocks orphans. This fixes the same.

Signed-off-by: Alim Akh

clk: samsung: exynos7: Add missing fixed_clks to cmu_info

FSYS0 fixed clocks are not added to fsys0_cmu_info, this makes
some of the usb clocks orphans. This fixes the same.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct CMU_FSYS1 clocks names

This patch renames CMU_FSYS1 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys1_200.

Signed-off-by: Alim A

clk: samsung: exynos7: Correct CMU_FSYS1 clocks names

This patch renames CMU_FSYS1 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys1_200.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct CMU_FSYS0 clocks names

This patch renames CMU_FSYS0 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys0_200.

Signed-off-by: Alim A

clk: samsung: exynos7: Correct CMU_FSYS0 clocks names

This patch renames CMU_FSYS0 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys0_200.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct CMU_PERIS clocks names

This patch renames CMU_PERIS clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzyszto

clk: samsung: exynos7: Correct CMU_PERIS clocks names

This patch renames CMU_PERIS clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct CMU_PERIC1 clocks names

This patch renames CMU_PERIC1 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric1_66.

Signed-off-by: Alim

clk: samsung: exynos7: Correct CMU_PERIC1 clocks names

This patch renames CMU_PERIC1 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric1_66.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct CMU_PERIC0 clocks names

This patch renames CMU_PERIC0 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric0_66.

Signed-off-by: Alim

clk: samsung: exynos7: Correct CMU_PERIC0 clocks names

This patch renames CMU_PERIC0 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric0_66.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct CMU_CCORE clocks names

This patch renames CMU_CCORE clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzyszto

clk: samsung: exynos7: Correct CMU_CCORE clocks names

This patch renames CMU_CCORE clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct CMU_TOP1 clocks names

This patch renames CMU_TOP1 clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylweste

clk: samsung: exynos7: Correct CMU_TOP1 clocks names

This patch renames CMU_TOP1 clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct CMU_TOP0 clocks names

This patch renames CMU_TOP0 clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylweste

clk: samsung: exynos7: Correct CMU_TOP0 clocks names

This patch renames CMU_TOP0 clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC

This adds some of the missing GATE clocks of CMU_TOPC block.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwest

clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC

This adds some of the missing GATE clocks of CMU_TOPC block.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Change the CMU_TOPC block clock names

Corrects the CMU_TOPC block clock names as per user manual.
This does not change any functionalities.

Signed-off-by: Alim Akhtar <alim.a

clk: samsung: exynos7: Change the CMU_TOPC block clock names

Corrects the CMU_TOPC block clock names as per user manual.
This does not change any functionalities.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct nr_clk_ids for fsys1

nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
this patch corrects it.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off

clk: samsung: exynos7: Correct nr_clk_ids for fsys1

nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
this patch corrects it.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Correct nr_clk_ids for fsys0

This patch corrects the nr_clk_ids for fsys0 block
which is wrongly set to number of clocks of the TOP1 CMU.
This also adjusts the gate clocks ord

clk: samsung: exynos7: Correct nr_clk_ids for fsys0

This patch corrects the nr_clk_ids for fsys0 block
which is wrongly set to number of clocks of the TOP1 CMU.
This also adjusts the gate clocks order.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Fix CMU TOP1 block

As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
and the GATE clocks are at bit 16 in their respective registers.
For mmc1 and mmc0 clock MUXs

clk: samsung: exynos7: Fix CMU TOP1 block

As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
and the GATE clocks are at bit 16 in their respective registers.
For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1.
And their DIV and GATE clks are in xxx_TOP1_FSYS11 instead of TOP1_FSYS1.
This patch corrects it.
This also adds xxx_FSYS11 to be saved/restore during s2r cycles.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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clk: samsung: exynos7: Fix CMU TOPC block clock

Corrects the bit width of DIV_TOPC3 register.
These are wrongly set to 3 which should be 4 bit wide as per UM.
This also adjusts the MUX clock order.

clk: samsung: exynos7: Fix CMU TOPC block clock

Corrects the bit width of DIV_TOPC3 register.
These are wrongly set to 3 which should be 4 bit wide as per UM.
This also adjusts the MUX clock order.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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