118df02fbSDaniel MackDevicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
218df02fbSDaniel Mack
318df02fbSDaniel MackThis device exposes 4 clocks in total:
418df02fbSDaniel Mack
518df02fbSDaniel Mack- MAX9485_MCLKOUT: 	A gated, buffered output of the input clock of 27 MHz
618df02fbSDaniel Mack- MAX9485_CLKOUT:	A PLL that can be configured to 16 different discrete
718df02fbSDaniel Mack			frequencies
818df02fbSDaniel Mack- MAX9485_CLKOUT[1,2]:	Two gated outputs for MAX9485_CLKOUT
918df02fbSDaniel Mack
1018df02fbSDaniel MackMAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
1118df02fbSDaniel Mackrequests.
1218df02fbSDaniel Mack
1318df02fbSDaniel MackRequired properties:
1418df02fbSDaniel Mack- compatible:	"maxim,max9485"
15*47aab533SBjorn Helgaas- clocks:	Input clock, must provide 27.000 MHz
1618df02fbSDaniel Mack- clock-names:	Must be set to "xclk"
1718df02fbSDaniel Mack- #clock-cells: From common clock binding; shall be set to 1
1818df02fbSDaniel Mack
1918df02fbSDaniel MackOptional properties:
2018df02fbSDaniel Mack- reset-gpios:		GPIO descriptor connected to the #RESET input pin
2118df02fbSDaniel Mack- vdd-supply:		A regulator node for Vdd
2218df02fbSDaniel Mack- clock-output-names:	Name of output clocks, as defined in common clock
2318df02fbSDaniel Mack			bindings
2418df02fbSDaniel Mack
2518df02fbSDaniel MackIf not explicitly set, the output names are "mclkout", "clkout", "clkout1"
2618df02fbSDaniel Mackand "clkout2".
2718df02fbSDaniel Mack
2818df02fbSDaniel MackClocks are defined as preprocessor macros in the dt-binding header.
2918df02fbSDaniel Mack
3018df02fbSDaniel MackExample:
3118df02fbSDaniel Mack
3218df02fbSDaniel Mack	#include <dt-bindings/clock/maxim,max9485.h>
3318df02fbSDaniel Mack
3418df02fbSDaniel Mack	xo-27mhz: xo-27mhz {
3518df02fbSDaniel Mack		compatible = "fixed-clock";
3618df02fbSDaniel Mack		#clock-cells = <0>;
3718df02fbSDaniel Mack		clock-frequency = <27000000>;
3818df02fbSDaniel Mack	};
3918df02fbSDaniel Mack
4018df02fbSDaniel Mack	&i2c0 {
4118df02fbSDaniel Mack		max9485: audio-clock@63 {
4218df02fbSDaniel Mack			reg = <0x63>;
4318df02fbSDaniel Mack			compatible = "maxim,max9485";
4418df02fbSDaniel Mack			clock-names = "xclk";
4518df02fbSDaniel Mack			clocks = <&xo-27mhz>;
4618df02fbSDaniel Mack			reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
4718df02fbSDaniel Mack			vdd-supply = <&3v3-reg>;
4818df02fbSDaniel Mack			#clock-cells = <1>;
4918df02fbSDaniel Mack		};
5018df02fbSDaniel Mack	};
5118df02fbSDaniel Mack
5218df02fbSDaniel Mack	// Clock consumer node
5318df02fbSDaniel Mack
5418df02fbSDaniel Mack	foo@0 {
5518df02fbSDaniel Mack		compatible = "bar,foo";
5618df02fbSDaniel Mack		/* ... */
5718df02fbSDaniel Mack		clock-names = "foo-input-clk";
5818df02fbSDaniel Mack		clocks = <&max9485 MAX9485_CLKOUT1>;
5918df02fbSDaniel Mack	};
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